JP7195208B2 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

Info

Publication number
JP7195208B2
JP7195208B2 JP2019076289A JP2019076289A JP7195208B2 JP 7195208 B2 JP7195208 B2 JP 7195208B2 JP 2019076289 A JP2019076289 A JP 2019076289A JP 2019076289 A JP2019076289 A JP 2019076289A JP 7195208 B2 JP7195208 B2 JP 7195208B2
Authority
JP
Japan
Prior art keywords
wire
semiconductor chips
semiconductor
semiconductor device
circuit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019076289A
Other languages
English (en)
Other versions
JP2020174156A (ja
Inventor
寛之 益本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2019076289A priority Critical patent/JP7195208B2/ja
Priority to US16/818,515 priority patent/US11532590B2/en
Priority to DE102020204406.6A priority patent/DE102020204406A1/de
Priority to CN202010264074.1A priority patent/CN111816633A/zh
Publication of JP2020174156A publication Critical patent/JP2020174156A/ja
Application granted granted Critical
Publication of JP7195208B2 publication Critical patent/JP7195208B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/40155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40157—Connecting the strap to a bond pad of the item
    • H01L2224/40159—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H01L2224/40229—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40477—Connecting portions connected to auxiliary connecting means on the bonding areas being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/40479—Connecting portions connected to auxiliary connecting means on the bonding areas being a pre-ball (i.e. a ball formed by capillary bonding) on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4099—Auxiliary members for strap connectors, e.g. flow-barriers, spacers
    • H01L2224/40991—Auxiliary members for strap connectors, e.g. flow-barriers, spacers being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/431—Pre-treatment of the preform connector
    • H01L2224/4312—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H01L2224/48132—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/4814—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate the wire connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/171—Frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

本発明は、発電および送電から効率的なエネルギーの利用および再生まであらゆる場面で利用される半導体装置に関するものである。
多くのパワー半導体装置において、半導体チップと回路パターンとの接続、および複数の半導体チップ間の接続にＡｌまたはＣｕなどからなるワイヤが用いられている。しかし、半導体装置を小型化する際に、ワイヤの本数が減ってしまうことで、ワイヤ１本当たりの電流密度が増加し、ワイヤの発熱が過剰に発生するという問題があった。
配線の電流密度を抑制する方法は、例えば特許文献１に開示されている。特許文献１に記載の配線方法は、スタックした複数の半導体チップを配線する場合に適用される方法である。この方法では、金ワイヤを各半導体チップの側面に形成し、導電性ペーストを用いて複数の半導体チップ間を接続している。
特開２００９－２７０４１号公報
しかしながら、特許文献１に記載の方法を数十アンペア以上数百アンペア以下の電流が流れるパワー半導体装置に適用しようとすると、半導体チップと回路パターンとの間の接続、および複数の半導体チップ間の接続が導電性ペーストのみで行われるため、半導体チップと回路パターンとの間の接続、および複数の半導体チップ間の接続に関するインピーダンスが大きくなる。さらに、形成した導電性ペーストの形状不良または導体への接触不良、すなわち濡れ不良などにより断線する可能性があり、その結果、製品の特性が低下することから、製品品質の欠陥が生じやすくなるという問題があった。
そこで、本発明は、半導体装置において、信頼性を損なうことなく小型化を実現できる技術を提供することを目的とする。
本発明に係る半導体装置は、回路パターンを有する絶縁基板と、前記回路パターン上に搭載された複数の半導体チップと、複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続するワイヤと、前記ワイヤと一体に形成される導電体とを備え、前記導電体は、前記ワイヤに形成される導電材と、前記導電材を介して前記ワイヤに固定される板状導電材とを有するものである。
本発明によれば、複数の半導体チップ間、および半導体チップと回路パターンとの間に、ワイヤに加えて導電体が接続されるため、ワイヤ１本当たりの電流密度を減らすことができることから、ワイヤの本数を減らすことができる。
ワイヤに加えて導電体が接続されるため、複数の半導体チップ間、および半導体チップと回路パターンとの間の接続に関する配線のインピーダンスを低減することができるとともに、断線の可能性を低減することができる。以上より、半導体装置において、信頼性を損なうことなく小型化を実現することができる。
実施の形態１に係る半導体装置の断面図である。 半導体装置が備える半導体チップおよびその周辺の断面図である。 半導体チップおよびその周辺の平面図である。 実施の形態２に係る半導体装置が備える半導体チップおよびその周辺の断面図である。 半導体チップおよびその周辺の平面図である。 実施の形態３に係る半導体装置の製造方法を説明するための断面図である。 実施の形態３に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 実施の形態４に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 実施の形態５に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 実施の形態６に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 導電体を設けない場合の半導体チップおよびその周辺の平面図である。 実施の形態７に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 実施の形態８に係る半導体装置が備える半導体チップおよびその周辺の平面図である。 実施の形態９に係る半導体装置の製造方法を説明するための平面図である。 実施の形態１０に係る半導体装置が備える半導体チップおよびその周辺の平面図である。
＜実施の形態１＞
本発明の実施の形態１について、図面を用いて以下に説明する。図１は、実施の形態１に係る半導体装置の断面図である。図２は、半導体装置が備える半導体チップおよびその周辺の断面図であり、具体的には、図１において破線で囲まれた部分の拡大図である。図３は、半導体チップおよびその周辺の平面図である。
図１に示すように、半導体装置はパワーモジュールであり、ケース１、ベース板４、絶縁基板５、半導体チップ１０，１１、ワイヤ１４、導電体２０としての導電材１５、信号端子２、電極３、ゲル１２、および蓋１３を備えている。
ケース１は、平面視にて矩形枠状の周壁部１ａを備え、ベース板４、絶縁基板５、半導体チップ１０，１１、ワイヤ１４、および導電材１５を囲繞する。ベース板４は、例えばＣｕなどの金属により形成され、平面視にて矩形状に形成されている。ベース板４は、ケース１の底面に絶縁基板５の上面の一部が露出するように固定されている。
絶縁基板５はベース板４の上面にはんだ９により固定され、セラミック板７、回路パターン８、および金属パターン６を備えている。回路パターン８はセラミック板７の上面に形成され、金属パターン６はセラミック板７の下面に形成されている。
半導体チップ１０，１１は、ＳｉＣなどのワイドバンドギャップ半導体により形成され、はんだ９を介して回路パターン８の上面に搭載されている。半導体チップ１０は例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）であり、半導体チップ１１は例えばダイオードである。
信号端子２および電極３はケース１の周壁部１ａに取り付けられている。ワイヤ１４は、半導体チップ１０と信号端子２との間、半導体チップ１０，１１の間、半導体チップ１１と回路パターン８との間、および半導体チップ１１と電極３との間をそれぞれ接続している。
ゲル１２はケース１の内部に充填され、ベース板４の上面の一部、絶縁基板５、半導体チップ１０，１１、ワイヤ１４、および導電材１５を封止する。蓋１３は、ケース１の周壁部１ａにおける上端部の内周部に取り付けられている。
次に、導電材１５について説明する。図２と図３に示すように、導電材１５は、半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間をそれぞれ接続する複数のワイヤ１４の長手方向の上側に沿って当該ワイヤ１４と一体に形成されている。ここで、導電材１５の線膨張係数はワイヤ１４の線膨張係数よりも小さいため、半導体チップ１０，１１の動作時におけるワイヤ１４の伸縮量を抑制できる。
次に、導電材１５の形成方法について説明する。最初に、複数のワイヤ１４をボンディングした後にディスペンサーなどでワイヤ１４の長手方向の上側に沿って導電性ペーストを塗布する。次に、例えば加熱処理を行って導電性ペーストを硬化することで導電材１５が形成される。これにより、導電材１５は複数のワイヤ１４を電気的に接続する。
なお、ワイヤ１４にアルミワイヤを採用する場合は、導電性ペーストとの濡れ性が確保することができない。そのため、Ａｌからなる基材と基材を被覆するＮｉまたはＣｕからなる被膜とを有するアルミワイヤを採用することが好ましい。
また、半導体チップ１０，１１の表面の金属と導電性ペーストに関して濡れ性の良い組み合わせ（例えばチップ表面：ＣｕまたはＡｕ、導電性ペースト：はんだの組み合わせ）を選択することで、半導体チップ１０，１１におけるワイヤ１４との接続箇所の周辺部に対しても導電性ペーストを塗布することが可能である。
以上のように、実施の形態１に係る半導体装置は、回路パターン８を有する絶縁基板５と、回路パターン８上に搭載された複数の半導体チップ１０，１１と、複数の半導体チップ１０，１１間、および半導体チップ１０，１１と回路パターン８との間をそれぞれ接続するワイヤ１４と、ワイヤ１４と一体に形成される導電体２０とを備える。
複数の半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間に、ワイヤ１４に加えて導電体２０としての導電材１５が接続されるため、ワイヤ１本当たりの電流密度を減らすことができることから、ワイヤ１４の本数を減らすことができる。
ワイヤ１４に加えて導電材１５が接続されるため、複数の半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間の接続に関するインピーダンスを低減することができるとともに、断線の可能性を低減することができる。以上より、半導体装置において、信頼性を損なうことなく小型化を実現することができる。
また、本数の少ないワイヤ１４でも電流密度を低く抑えることができるため、半導体装置の設計自由度の向上を図ることができる。
導電体２０は、ワイヤ１４に導電性ペーストを塗布し硬化することで形成されるため、ワイヤ１４に導電体２０を容易に形成することができる。
導電材１５を、半導体チップ１０，１１におけるワイヤ１４との接続箇所の周辺部にも形成した場合は、半導体チップ１０，１１が発熱した直後に導電材１５を通して熱を逃がすため、発熱直後の温度上昇の低減効果が得られる。また、半導体装置の信頼性の面ではＰ／Ｃ性を向上させることができる。
半導体チップ１０，１１の動作時（温度変化時）にそれらの界面に応力が発生するが、導電材１５の線膨張係数はワイヤ１４の線膨張係数よりも小さい場合、半導体チップ１０，１１の動作時におけるワイヤ１４の伸縮量を抑制できるため、半導体チップ１０，１１とワイヤ１４の界面に発生する機械的ストレスを抑制でき、Ｐ／Ｃ性をさらに向上させることができる。
＜実施の形態２＞
次に、実施の形態２に係る半導体装置について説明する。図４は、実施の形態２に係る半導体装置が備える半導体チップ１０，１１およびその周辺の断面図である。図５は、半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態２において、実施の形態１で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図４と図５に示すように、実施の形態２では、半導体装置はワイヤ１４に代えてリボンワイヤ２４を備えている。リボンワイヤ２４はＡｌとＣｕなどの異種金属を接合した複合材からなる。
導電体２０としての導電材１５は、半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間をそれぞれ接続するリボンワイヤ２４の長手方向の上側に沿って当該リボンワイヤ２４と一体に形成されている。リボンワイヤ２４に対する導電材１５の形成方法は、実施の形態１の場合と同様であるため説明を省略する。
以上のように、実施の形態２に係る半導体装置では、ワイヤはリボンワイヤ２４であるため、実施の形態１の場合と同様の効果が得られる。
＜実施の形態３＞
次に、実施の形態３に係る半導体装置について説明する。図６は、実施の形態３に係る半導体装置の製造方法を説明するための断面図である。具体的には、図６（ａ）は、半導体チップ１０，１１および回路パターン８に接続されるワイヤ１４に導電性ペースト１５ａを塗布する工程を示す断面図である。図６（ｂ）は、半導体チップ１０，１１および回路パターン８に接続されるワイヤ１４に導電体２１を形成する工程を示す断面図である。図７は、実施の形態３に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態３において、実施の形態１，２で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図６（ａ），（ｂ）と図７に示すように、実施の形態３では、導電体２１は、ワイヤ１４に形成される導電材１５と、導電材１５を介してワイヤ１４に固定される板状導電材１６とを有する。
導電体２１は、半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間をそれぞれ接続するワイヤ１４と一体に形成されている。具体的には、導電材１５は、半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間をそれぞれ接続するワイヤ１４のうち、半導体チップ１０，１１および回路パターン８に位置する箇所に形成されている。板状導電材１６は、複数の導電材１５に載置され、複数の導電材１５を介して複数のワイヤ１４に固定されている。
次に、導電体２１の形成方法について説明する。最初に、図６（ａ）に示すように、複数のワイヤ１４をボンディングした後に、半導体チップ１０，１１の間、および半導体チップ１１と回路パターン８との間をそれぞれ接続するワイヤ１４のうち、半導体チップ１０，１１および回路パターン８に位置する箇所に、ディスペンサー５０により導電性ペースト１５ａを塗布する。次に、図６（ｂ）に示すように、導電性ペースト１５ａを介してワイヤ１４に板状導電材１６を載置する。次に、例えば加熱処理を行って導電性ペースト１５ａを硬化することで、板状導電材１６が導電材１５を介して複数のワイヤ１４に固定され導電体２１が形成される。これにより、導電体２１は複数のワイヤ１４を電気的に接続する。なお、実施の形態３に係る半導体装置は、実施の形態１，２で説明した導電体２０も備えていてもよい。
以上のように、実施の形態３に係る半導体装置では、導電体２１は、ワイヤ１４に形成される導電材１５と、導電材１５を介してワイヤ１４に固定される板状導電材１６とを有する。したがって、実施の形態１の場合と同様の効果を得ることができる。なお、板状導電材１６として厚みのある板状導電材を採用することで、半導体チップ１０，１１の動作時における電流密度の軽減効果の増加が見込める。
導電体２１は、ワイヤ１４に導電性ペースト１５ａを塗布した後、導電性ペースト１５ａを介してワイヤ１４に板状導電材１６を載置し、導電性ペースト１５ａを硬化することで形成されるため、ワイヤ１４に導電体２１を容易に形成することができる。
＜実施の形態４＞
次に、実施の形態４に係る半導体装置について説明する。図８は、実施の形態４に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態４において、実施の形態１～３で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図８に示すように、実施の形態４では、並列接続された複数の半導体チップ１０，１１に対し１つの導電体２１が接続されている。具体的には、半導体チップ１０，１１が３組並列接続され、３組の半導体チップ１０，１１と回路パターン８に対して１つの導電体２１が接続されている。なお、ワイヤ１４に対する導電体２１の形成方法は、実施の形態３の場合と同様であるため説明を省略する。
以上のように、実施の形態４に係る半導体装置では、複数の半導体チップ１０，１１は、複数組、並列接続され、複数組の複数の半導体チップ間１０，１１は、１つの導電体２１により接続されるため、実施の形態３の場合と同様の効果を得ることができる。
＜実施の形態５＞
次に、実施の形態５に係る半導体装置について説明する。図９は、実施の形態５に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態５において、実施の形態１～４で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図９に示すように、実施の形態５では、並列接続された複数組の複数の半導体チップ１０，１１に対し個別に導電体が接続されている。具体的には、半導体チップ１０，１１が３組並列接続され、３組の半導体チップ１０，１１と回路パターン８に対して３つの導電体２１がそれぞれ接続されている。なお、ワイヤ１４に対する導電体２１の形成方法は、実施の形態３の場合と同様であるため説明を省略する。
以上のように、実施の形態５に係る半導体装置では、並列接続された複数組の複数の半導体チップ１０，１１に対し個別に導電体２１が接続されるため、実施の形態３の場合と同様の効果を得ることができる。
＜実施の形態６＞
次に、実施の形態６に係る半導体装置について説明する。図１０は、実施の形態６に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。図１１は、導電体２２を設けない場合の半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態６において、実施の形態１～５で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図１０に示すように、実施の形態６では、並列接続された複数組の複数の半導体チップ１０，１１に対し、隣り合う半導体チップ１０間および隣り合う半導体チップ１１間のワイヤ１４を導電体２２により導通させている。具体的には、導電体２２は、隣り合う半導体チップ１０および隣り合う半導体チップ１１において、一方の半導体チップ１０，１１における他方の半導体チップ１０，１１側に位置するワイヤ１４と、他方の半導体チップ１０，１１における一方の半導体チップ１０，１１側に位置するワイヤ１４とに一体に形成されている。導電体２２は、導電材１５（図６参照）と板状導電材１７とを有している。
導電体２２を設けない場合はリンギングを抑制するために、図１１に示すように、並列接続された３組の半導体チップ１０間にリンギング抑制用のワイヤ１４ａを接続するという対策が施される。しかし、リンギング抑制用のワイヤ１４ａを接続するためのスペースを確保する必要があり、半導体装置の小型化の妨げとなる。
これに対して、実施の形態６に係る半導体装置では、導電体２２は、隣り合う半導体チップ１０，１１において、一方の半導体チップ１０，１１における他方の半導体チップ１０，１１側に位置するワイヤ１４と、他方の半導体チップ１０，１１における一方の半導体チップ１０，１１側に位置するワイヤ１４とに一体に形成される。
したがって、リンギング抑制用のワイヤ１４ａを接続するためのスペースを確保する必要がなくなる。これにより、リンギング対策を行う場合にも、半導体装置の小型化を実現することができる。
＜実施の形態７＞
次に、実施の形態７に係る半導体装置について説明する。図１２は、実施の形態７に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態７において、実施の形態１～６で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図１２に示すように、実施の形態７は、実施の形態５と実施の形態６を組み合わせた構成である。すなわち、実施の形態７では、並列接続された複数組の複数の半導体チップ１０，１１に対し個別に導電体２１が接続されるとともに、並列接続された複数組の複数の半導体チップ１０，１１に対し、隣り合う半導体チップ１０間および隣り合う半導体チップ１１間のワイヤ１４を導電体２２により導通させている。
以上のように、実施の形態７に係る半導体装置は上記の構成を備えるため、実施の形態５の場合と実施の形態６の場合の効果を得ることができる。
＜実施の形態８＞
次に、実施の形態８に係る半導体装置について説明する。図１３は、実施の形態８に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態８において、実施の形態１～７で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図１３に示すように、実施の形態８では、複数のワイヤ１４は連続的に、かつ、互いに角度をつけて配線され、導電体２１は、連続的に配線された複数のワイヤ１４の長手方向に沿ってワイヤ１４と一体に形成されている。
半導体チップ１０，１１と回路パターン８にワイヤ１４を接続する際、θで示すように角度をつける必要がある場合がある。ワイヤ１４を接続する際に角度をつける場合、ワイヤ１４とワイヤボンドツールとの接触を避けるために、角度をつけない場合と比べてワイヤ１４の本数が減る傾向にあることから、ワイヤ１４の電流密度が増えることがある。
これに対して、実施の形態８に係る半導体装置では、ワイヤ１４は複数であり、複数のワイヤ１４は連続的に、かつ、互いに角度をつけて配線され、導電体２１は、連続的に配線された複数のワイヤ１４の長手方向に沿ってワイヤ１４と一体に形成される。したがって、実施の形態１の場合と同様の効果が得られることから、本数の少ないワイヤ１４でも電流密度を低く抑えることができる。
＜実施の形態９＞
次に、実施の形態９に係る半導体装置について説明する。図１４は、実施の形態９に係る半導体装置の製造方法を説明するための平面図である。具体的には、図１４（ａ）は、半導体チップ１１と回路パターン８との間に板状導電材１６を接続する前の状態を示す平面図である。図１４（ｂ）は、半導体チップ１１と回路パターン８との間に板状導電材１６を接続した後の状態を示す平面図である。なお、実施の形態９において、実施の形態１～８で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図１４（ｂ）に示すように、実施の形態９では、半導体チップ１１と回路パターン８との間をワイヤ１４で接続するのではなく、板状導電材１６で接続する。
半導体装置は、回路パターン８を有する絶縁基板５と、回路パターン８上に搭載された複数の半導体チップ１０，１１と、半導体チップ１１と回路パターン８との間を接続する板状導電材１６とを備えている。
次に、板状導電材１６の接続方法について説明する。図１４（ａ）に示すように、最初に、複数のワイヤ１４をボンディングした後に、実施の形態３の場合と同様の方法で半導体チップ１０，１１の間に導電体２１を形成する。次に、図１４（ｂ）に示すように、半導体チップ１１と回路パターン８との間の接続箇所に導電性ペーストを塗布した後、導電性ペーストを介して接続箇所に板状導電材１６を載置する。次に、例えば加熱処理を行って導電性ペーストを硬化することで、半導体チップ１１と回路パターン８との間に板状導電材１６が接続される。
なお、ワイヤ１４と一体化した導電体２１に代えて、半導体チップ１０，１１間をワイヤ１４と一体化した導電体２０で接続してもよい。また、半導体チップ１０，１１間をワイヤ１４と一体化した導電体２１で接続するのではなく、板状導電材１６で接続してもよい。また、半導体チップ１１と回路パターン８との間をワイヤ１４と一体化した導電体２０または導電体２１で接続し、半導体チップ１０，１１間を板状導電材１６で接続してもよい。
以上のように、実施の形態９に係る半導体装置は、回路パターン８を有する絶縁基板５と、回路パターン８上に搭載された複数の半導体チップ１０，１１と、複数の半導体チップ１０，１１間、および半導体チップ１１と回路パターン８との間をそれぞれ接続する板状導電材１６とを備える。
したがって、実施の形態１の場合と同様の効果を得ることができる。特に、ワイヤ１４を用いた配線が困難なレイアウトに対しても配線を形成することができるため、半導体装置における設計自由度の向上および小型化をさらに図ることができる。
板状導電材１６は、複数の半導体チップ１０，１１間の接続箇所、および半導体チップ１１と回路パターン８との間の接続箇所に導電性ペーストを塗布した後、導電性ペーストを介して接続箇所に板状導電材１６を載置し、導電性ペーストを硬化することで接続される。したがって、複数の半導体チップ１０，１１間の接続箇所、および半導体チップ１１と回路パターン８との間の接続箇所に板状導電材１６を容易に接続することができる。
複数の半導体チップ１０，１１間、および半導体チップ１１と回路パターン８との間をそれぞれ接続するワイヤ１４と、ワイヤ１４と一体に形成される導電体２０または導電体２１とをさらに備える。したがって、板状導電材１６と導電体２０または導電体２１を並存させることで、半導体装置の設計自由度がさらに向上する。
＜実施の形態１０＞
次に、実施の形態１０に係る半導体装置について説明する。図１５は、実施の形態１０に係る半導体装置が備える半導体チップ１０，１１およびその周辺の平面図である。なお、実施の形態１０において、実施の形態１～９で説明したものと同一の構成要素については同一符号を付して説明は省略する。
図１５に示すように、実施の形態１０では、並列接続された複数の半導体チップ１０，１１に対し１つの板状導電材１６が接続されている。具体的には、半導体チップ１０，１１が３組並列接続され、３組の半導体チップ１０，１１と回路パターン８に対して１つの板状導電材１６が接続されている。なお、板状導電材１６の接続方法は、実施の形態９の場合と同様であるため説明を省略する。
また、実施の形態９の場合と同様に、例えば、回路パターン８側に配置された２組の複数の半導体チップ１０，１１間、および半導体チップ１０，１１と回路パターン８との間を１つの板状導電材１６で接続し、残りの１組の複数の半導体チップ１０，１１間をワイヤ１４と一体化した導電体２０または導電体２１で接続してもよい。すなわち、１つの板状導電材１６と導電体２０または導電体２１は並存していてもよい。
以上のように、実施の形態１０に係る半導体装置では、複数の半導体チップ１０，１１は複数組、並列接続され、複数組の複数の半導体チップ１０，１１間、および半導体チップ１０，１１と回路パターン８との間は、１つの板状導電材１６により接続される。
さらに、複数の半導体チップ１０，１１間、および半導体チップ１０，１１と回路パターン８との間をそれぞれ接続するワイヤ１４と、ワイヤ１４と一体に形成される導電体２０または導電体２１とをさらに備える。以上より、実施の形態９の場合と同様の効果を得ることができる。
なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。
５ 絶縁基板、８ 回路パターン、１０，１１ 半導体チップ、１４ ワイヤ、１５ 導電材、１６，１７ 板状導電材、２０，２１，２２ 導電体、２４ リボンワイヤ。

Claims (12)

  1. 回路パターンを有する絶縁基板と、
    前記回路パターン上に搭載された複数の半導体チップと、
    複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続するワイヤと、
    前記ワイヤと一体に形成される導電体と、
    を備え、
    前記導電体は、前記ワイヤに形成される導電材と、前記導電材を介して前記ワイヤに固定される板状導電材とを有する、半導体装置。
  2. 前記導電体は、前記半導体チップにおける前記ワイヤとの接続箇所の周辺部にも形成される、請求項１に記載の半導体装置。
  3. 前記導電材の線膨張係数は前記ワイヤの線膨張係数よりも小さい、請求項１に記載の半導体装置。
  4. 前記ワイヤは、Ａｌからなる基材と前記基材を被覆するＮｉまたはＣｕからなる被膜とを有する、請求項１に記載の半導体装置。
  5. 前記ワイヤはリボンワイヤである、請求項１に記載の半導体装置。
  6. 複数の前記半導体チップは複数組、並列接続され、
    複数組の複数の前記半導体チップ間は、１つの前記導電体により接続される、請求項１に記載の半導体装置。
  7. 回路パターンを有する絶縁基板と、
    前記回路パターン上に搭載された複数の半導体チップと、
    複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続するワイヤと、
    前記ワイヤと一体に形成される導電体と、
    を備え、
    前記導電体は、隣り合う前記半導体チップにおいて、一方の前記半導体チップにおける他方の前記半導体チップ側に位置する前記ワイヤと、他方の前記半導体チップにおける一方の前記半導体チップ側に位置する前記ワイヤとに一体に形成され、
    前記導電体は、前記ワイヤに形成される導電材と、前記導電材を介して前記ワイヤに固定される板状導電材とを有する、半導体装置。
  8. 前記ワイヤは複数であり、
    複数の前記ワイヤは連続的に、かつ、互いに角度をつけて配線され、
    前記導電体は、連続的に配線された複数の前記ワイヤの長手方向に沿って前記ワイヤと一体に形成される、請求項１に記載の半導体装置。
  9. 回路パターンを有する絶縁基板と、
    前記回路パターン上に搭載された複数の半導体チップと、
    複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続する板状導電材と、
    を備え、
    複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続するワイヤと、
    前記ワイヤと一体に形成される導電体とをさらに備え、
    前記導電体は前記板状導電材と並存する、半導体装置。
  10. 複数の前記半導体チップはワイドバンドギャップ半導体により形成される、請求項１から請求項９のいずれか１項に記載の半導体装置。
  11. 請求項１に記載の半導体装置の製造方法であって、
    前記導電材は、前記ワイヤに導電性ペーストを塗布し硬化することで形成される、半導体装置の製造方法。
  12. 回路パターンを有する絶縁基板と、
    前記回路パターン上に搭載された複数の半導体チップと、
    複数の前記半導体チップ間、および前記半導体チップと前記回路パターンとの間をそれぞれ接続するワイヤと、
    前記ワイヤと一体に形成される導電体と、
    を備える半導体装置の製造方法であって、
    前記導電体は、前記ワイヤに導電性ペーストを塗布した後、前記導電性ペーストを介して前記ワイヤに板状導電材を載置し、前記導電性ペーストを硬化することで形成される、半導体装置の製造方法。
JP2019076289A 2019-04-12 2019-04-12 半導体装置および半導体装置の製造方法 Active JP7195208B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019076289A JP7195208B2 (ja) 2019-04-12 2019-04-12 半導体装置および半導体装置の製造方法
US16/818,515 US11532590B2 (en) 2019-04-12 2020-03-13 Semiconductor device and method for manufacturing semiconductor device
DE102020204406.6A DE102020204406A1 (de) 2019-04-12 2020-04-06 Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung
CN202010264074.1A CN111816633A (zh) 2019-04-12 2020-04-07 半导体装置及半导体装置的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019076289A JP7195208B2 (ja) 2019-04-12 2019-04-12 半導体装置および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2020174156A JP2020174156A (ja) 2020-10-22
JP7195208B2 true JP7195208B2 (ja) 2022-12-23

Family

ID=72613709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019076289A Active JP7195208B2 (ja) 2019-04-12 2019-04-12 半導体装置および半導体装置の製造方法

Country Status (4)

Country Link
US (1) US11532590B2 (ja)
JP (1) JP7195208B2 (ja)
CN (1) CN111816633A (ja)
DE (1) DE102020204406A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6952824B2 (ja) * 2020-04-06 2021-10-27 三菱電機株式会社 パワーモジュール及びこれを用いた電力用半導体装置
JP7282147B1 (ja) * 2021-12-01 2023-05-26 三菱電機株式会社 半導体装置および電力変換装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243778A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
JP2010178615A (ja) 2000-08-28 2010-08-12 Mitsubishi Electric Corp 半導体装置
JP2010283053A (ja) 2009-06-03 2010-12-16 Renesas Electronics Corp 半導体装置及びその製造方法
JP2015142059A (ja) 2014-01-30 2015-08-03 株式会社日立製作所 パワー半導体モジュール
WO2019044748A1 (ja) 2017-09-04 2019-03-07 三菱電機株式会社 半導体モジュール及び電力変換装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3877885A (en) * 1970-12-02 1975-04-15 Texas Instruments Inc Copper-clad aluminum wire and method of making
JPS5697655A (en) 1980-01-09 1981-08-06 Nippon Denso Co Ltd Power transmission
JPS6097655A (ja) * 1983-11-02 1985-05-31 Hitachi Ltd ボンデイング用ワイヤ
US7084656B1 (en) * 1993-11-16 2006-08-01 Formfactor, Inc. Probe for semiconductor devices
US6727579B1 (en) * 1994-11-16 2004-04-27 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US20020113322A1 (en) * 2000-06-12 2002-08-22 Shinichi Terashima Semiconductor device and method to produce the same
JP3590603B2 (ja) * 2000-11-02 2004-11-17 新日本製鐵株式会社 半導体装置およびその製造方法
US20060189119A1 (en) * 2005-01-24 2006-08-24 Michael Jin Encapsulation of circuit components to reduce thermal cycling stress
DE102005028951B4 (de) 2005-06-22 2018-05-30 Infineon Technologies Ag Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung
JP5110996B2 (ja) 2007-07-20 2012-12-26 新光電気工業株式会社 積層型半導体装置の製造方法
US7956469B2 (en) * 2007-07-27 2011-06-07 Nichia Corporation Light emitting device and method of manufacturing the same
JP2009071156A (ja) * 2007-09-14 2009-04-02 Toshiba Corp 半導体装置及びその製造方法
KR101144406B1 (ko) * 2009-03-17 2012-05-10 가부시키가이샤 닛데쓰 마이크로 메탈 반도체용 본딩 와이어
US9461023B2 (en) * 2011-10-28 2016-10-04 Bridgelux, Inc. Jetting a highly reflective layer onto an LED assembly
DE102012208251A1 (de) 2012-05-16 2013-11-21 Robert Bosch Gmbh Elektrische Kontaktierung für Halbleiter
JP6305302B2 (ja) 2014-10-02 2018-04-04 三菱電機株式会社 半導体装置およびその製造方法
SG10201509634UA (en) * 2015-11-23 2017-06-29 Heraeus Oriental Hitec Co Ltd Coated wire
WO2018189948A1 (ja) 2017-04-12 2018-10-18 三菱電機株式会社 半導体モジュール、半導体モジュールの製造方法および電力変換装置
US10629562B2 (en) * 2017-12-29 2020-04-21 Texas Instruments Incorporated Integrated circuit packaging
WO2019241737A1 (en) * 2018-06-14 2019-12-19 Caprice Gray Haley Coaxial wire
US20200203243A1 (en) * 2018-12-19 2020-06-25 Texas Instruments Incorporated Universal leaded/leadless chip scale package for microelecronic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243778A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
JP2010178615A (ja) 2000-08-28 2010-08-12 Mitsubishi Electric Corp 半導体装置
JP2010283053A (ja) 2009-06-03 2010-12-16 Renesas Electronics Corp 半導体装置及びその製造方法
JP2015142059A (ja) 2014-01-30 2015-08-03 株式会社日立製作所 パワー半導体モジュール
WO2019044748A1 (ja) 2017-09-04 2019-03-07 三菱電機株式会社 半導体モジュール及び電力変換装置

Also Published As

Publication number Publication date
DE102020204406A1 (de) 2020-10-15
US20200328178A1 (en) 2020-10-15
JP2020174156A (ja) 2020-10-22
CN111816633A (zh) 2020-10-23
US11532590B2 (en) 2022-12-20

Similar Documents

Publication Publication Date Title
US8451621B2 (en) Semiconductor component and method of manufacture
CN107615464B (zh) 电力用半导体装置的制造方法以及电力用半导体装置
JP5678884B2 (ja) 電力変換装置
JP6818649B2 (ja) 半導体装置及び半導体素子
JP2006253516A (ja) パワー半導体装置
JP6261642B2 (ja) 電力半導体装置
JP6988345B2 (ja) 半導体装置
JP6726112B2 (ja) 半導体装置および電力変換装置
JP2010283053A (ja) 半導体装置及びその製造方法
JP7204174B2 (ja) 半導体装置及び半導体装置の製造方法
JP7195208B2 (ja) 半導体装置および半導体装置の製造方法
JP2005064479A (ja) 回路モジュール
JP4349364B2 (ja) 半導体装置
JP7260278B2 (ja) 半導体サブアセンブリー及び半導体パワーモジュール
JP2015023226A (ja) ワイドギャップ半導体装置
JP6327105B2 (ja) 半導体装置
CN107611111B (zh) 半导体模块、电力转换装置
JP5840102B2 (ja) 電力用半導体装置
JP7419781B2 (ja) 半導体モジュール
CN111354709B (zh) 半导体装置及其制造方法
JP2001332664A (ja) 半導体装置およびその製造方法
JP5682511B2 (ja) 半導体モジュール
JP2008211168A (ja) 半導体装置および半導体モジュール
JP2006294729A (ja) 半導体装置
WO2017077729A1 (ja) 半導体モジュール及びその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210419

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220329

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220510

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220927

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221028

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20221115

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221213

R150 Certificate of patent or registration of utility model

Ref document number: 7195208

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150