CN111816633A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

Info

Publication number
CN111816633A
CN111816633A CN202010264074.1A CN202010264074A CN111816633A CN 111816633 A CN111816633 A CN 111816633A CN 202010264074 A CN202010264074 A CN 202010264074A CN 111816633 A CN111816633 A CN 111816633A
Authority
CN
China
Prior art keywords
semiconductor device
semiconductor
semiconductor chips
conductor
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010264074.1A
Other languages
English (en)
Inventor
益本宽之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN111816633A publication Critical patent/CN111816633A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/40155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40157—Connecting the strap to a bond pad of the item
    • H01L2224/40159—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H01L2224/40229—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40477—Connecting portions connected to auxiliary connecting means on the bonding areas being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/40479—Connecting portions connected to auxiliary connecting means on the bonding areas being a pre-ball (i.e. a ball formed by capillary bonding) on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4099—Auxiliary members for strap connectors, e.g. flow-barriers, spacers
    • H01L2224/40991—Auxiliary members for strap connectors, e.g. flow-barriers, spacers being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/431—Pre-treatment of the preform connector
    • H01L2224/4312—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H01L2224/438—Post-treatment of the connector
    • H01L2224/4382—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H01L2224/48132—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/4814—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate the wire connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/171—Frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

目的在于提供如下技术，即，针对半导体装置，能够在不损害可靠性的情况下实现小型化。半导体装置具有：绝缘基板(5)，其具有电路图案(8)；多个半导体芯片(10、11)，它们搭载于电路图案(8)之上；导线(14)，其将多个半导体芯片(10、11)之间、及半导体芯片(10、11)和电路图案(8)之间分别进行连接；以及作为导体的导电材料(15)，其与导线(14)形成为一体。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及在发电及送电至有效的能量利用及再生为止的所有情况下利用的半导体装置。
背景技术
在大量的功率半导体装置中，将由Al或Cu等构成的导线用于半导体芯片和电路图案的连接、及多个半导体芯片间的连接。但是，存在如下问题，即，在将半导体装置小型化时，导线的根数减少，由此每1根导线的电流密度增加，导线过度地产生发热。
例如专利文献1公开了对配线的电流密度进行抑制的方法。专利文献1所记载的配线方法是在对堆叠的多个半导体芯片进行配线的情况下应用的方法。在该方法中，在各半导体芯片的侧面形成金导线，使用导电性膏将多个半导体芯片之间连接。
专利文献1：日本特开2009-27041号公报
但是，如果想要将专利文献1所记载的方法用于流过大于或等于几十安培且小于或等于几百安培的电流的功率半导体装置，则由于仅通过导电性膏进行半导体芯片和电路图案之间的连接、及多个半导体芯片之间的连接，所以与半导体芯片和电路图案之间的连接、及多个半导体芯片之间的连接相关的阻抗变大。并且，存在如下问题，即，由于形成的导电性膏的形状不良或与导体的接触不良即润湿不良等，有可能产生断线，其结果，产品的特性降低，因此容易产生产品品质的缺陷。
发明内容
因此，本发明的目的在于提供如下技术，即，针对半导体装置，能够在不损害可靠性的情况下实现小型化。
本发明涉及的半导体装置具有：绝缘基板，其具有电路图案；
多个半导体芯片，它们搭载于所述电路图案之上；导线，其将多个所述半导体芯片之间、及所述半导体芯片和所述电路图案之间分别进行连接；以及导体，其与所述导线形成为一体。
发明的效果
根据本发明，由于在多个半导体芯片之间、及半导体芯片和电路图案之间，除了连接导线之外还连接导体，因此能够减少每1根导线的电流密度，所以能够减少导线的根数。
由于除了连接导线之外还连接导体，因此能够减少与多个半导体芯片之间、及半导体芯片和电路图案之间的连接相关的配线的阻抗，并且能够减少断线的可能性。由此，针对半导体装置，能够在不损害可靠性的情况下实现小型化。
附图说明
图1是实施方式1涉及的半导体装置的剖视图。
图2是半导体装置所具有的半导体芯片及其周边的剖视图。
图3是半导体芯片及其周边的俯视图。
图4是实施方式2涉及的半导体装置所具有的半导体芯片及其周边的剖视图。
图5是半导体芯片及其周边的俯视图。
图6是用于说明实施方式3涉及的半导体装置的制造方法的剖视图。
图7是实施方式3涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图8是实施方式4涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图9是实施方式5涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图10是实施方式6涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图11是没有设置导体的情况下的半导体芯片及其周边的俯视图。
图12是实施方式7涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图13是实施方式8涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
图14是用于说明实施方式9涉及的半导体装置的制造方法的俯视图。
图15是实施方式10涉及的半导体装置所具有的半导体芯片及其周边的俯视图。
标号的说明
5绝缘基板，8电路图案，10、11半导体芯片，14导线，15导电材料，16、17板状导电材料，20、21、22导体，24带状导线。
具体实施方式
<实施方式1>
下面，使用附图对本发明的实施方式1进行说明。图1是实施方式1涉及的半导体装置的剖视图。图2是半导体装置所具有的半导体芯片及其周边的剖视图，具体而言，是在图1中由虚线包围的部分的放大图。图3是半导体芯片及其周边的俯视图。
如图1所示，半导体装置为功率模块，其具有壳体1、基座板4、绝缘基板5、半导体芯片10、11、导线14、信号端子2、电极3、凝胶12、盖13及作为导体20的导电材料15。
壳体1具有在俯视观察时呈矩形框状的周壁部1a，该壳体1将基座板4、绝缘基板5、半导体芯片10、11、导线14、及导电材料15围绕起来。基座板4例如由Cu等金属形成，在俯视观察时形成为矩形状。基座板4以绝缘基板5的上表面的一部分露出的方式固定于壳体1的底面。
绝缘基板5通过焊料9固定于基座板4的上表面，绝缘基板5具有陶瓷板7、电路图案8、及金属图案6。电路图案8形成于陶瓷板7的上表面，金属图案6形成于陶瓷板7的下表面。
半导体芯片10、11由SiC等宽带隙半导体形成，经由焊料9搭载于电路图案8的上表面。半导体芯片10例如为IGBT(Insulated Gate Bipolar Transistor)，半导体芯片11例如为二极管。
信号端子2及电极3安装于壳体1的周壁部1a。导线14将半导体芯片10和信号端子2之间、半导体芯片10、11之间、半导体芯片11和电路图案8之间、及半导体芯片11和电极3之间分别进行连接。
凝胶12填充于壳体1的内部，将基座板4的上表面的一部分、绝缘基板5、半导体芯片10、11、导线14、及导电材料15封装。盖13安装于壳体1的周壁部1a中的上端部的内周部。
下面，对导电材料15进行说明。如图2和图3所示，导电材料15沿多个导线14的长度方向的上侧与该导线14形成为一体，该多个导线14将半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接。这里，由于导电材料15的线膨胀系数比导线14的线膨胀系数小，因此能够对半导体芯片10、11工作时的导线14的伸缩量进行抑制。
下面，对导电材料15的形成方法进行说明。首先，在将多个导线14键合后通过滴涂器等沿导线14的长度方向的上侧对导电性膏进行涂敷。接着，例如通过进行加热处理而使导电性膏固化，从而形成导电材料15。由此，导电材料15将多个导线14电连接。
此外，在将铝导线用于导线14的情况下，不能够确保与导电性膏的润湿性。因此，优选采用具有由Al构成的基材和覆盖基材的由Ni或Cu构成的覆膜的铝导线。
另外，通过选择半导体芯片10、11的表面的金属与导电性膏润湿性良好的组合(例如芯片表面：Cu或Au，导电性膏：焊料的组合)，针对半导体芯片10、11的与导线14的连接部位的周边部也能够对导电性膏进行涂敷。
如上所述，实施方式1涉及的半导体装置具有：绝缘基板5，其具有电路图案8；多个半导体芯片10、11，它们搭载于电路图案8之上；导线14，其将多个半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接；以及导体20，其与导线14形成为一体。
由于在多个半导体芯片10、11之间、及半导体芯片11和电路图案8之间，除了连接导线14之外还连接作为导体20的导电材料15，因此能够减少每1根导线的电流密度，所以能够减少导线14的根数。
由于除了连接导线14之外还连接导电材料15，因此能够减少与多个半导体芯片10、11之间、及半导体芯片11和电路图案8之间的连接相关的阻抗，并且能够减少断线的可能性。由此，针对半导体装置，能够在不损害可靠性的情况下实现小型化。
另外，即使是根数少的导线14也能够将电流密度抑制得低，能够实现半导体装置的设计自由度的提高。
由于导体20是通过将导电性膏涂敷于导线14并固化而形成的，因此能够容易地在导线14形成导体20。
当在半导体芯片10、11的与导线14的连接部位的周边部也形成有导电材料15的情况下，由于在半导体芯片10、11刚刚发热之后通过导电材料15将热量释放，因此得到刚刚发热之后的温度上升的降低效果。另外，在半导体装置的可靠性方面能够使P/C性提高。
虽然在半导体芯片10、11工作时(温度变化时)在它们的界面产生应力，但在导电材料15的线膨胀系数比导线14的线膨胀系数小的情况下，能够对半导体芯片10、11工作时的导线14的伸缩量进行抑制，因此能够对在半导体芯片10、11和导线14的界面产生的机械应力进行抑制，能够进一步使P/C性提高。
<实施方式2>
接着，对实施方式2涉及的半导体装置进行说明。图4是实施方式2涉及的半导体装置所具有的半导体芯片10、11及其周边的剖视图。图5是半导体芯片10、11及其周边的俯视图。此外，在实施方式2中，对与实施方式1中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图4和图5所示，在实施方式2中，替代导线14，半导体装置具有带状导线24。带状导线24由将Al和Cu等不同种类金属接合后的复合材料构成。
作为导体20的导电材料15沿带状导线24的长度方向的上侧与该带状导线24形成为一体，该带状导线24将半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接。由于相对于带状导线24的导电材料15的形成方法与实施方式1的情况相同，因此省略说明。
如上所述，就实施方式2涉及的半导体装置而言，由于导线为带状导线24，因此得到与实施方式1的情况相同的效果。
<实施方式3>
接着，对实施方式3涉及的半导体装置进行说明。图6是用于说明实施方式3涉及的半导体装置的制造方法的剖视图。具体而言，图6(a)是表示将导电性膏15a涂敷于与半导体芯片10、11及电路图案8连接的导线14的工序的剖视图。图6(b)是表示在与半导体芯片10、11及电路图案8连接的导线14形成导体21的工序的剖视图。图7是实施方式3涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式3中，对与实施方式1、2中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图6(a)、(b)和图7所示，在实施方式3中，导体21具有：导电材料15，其形成于导线14；以及板状导电材料16，其经由导电材料15固定于导线14。
导体21与将半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接的导线14形成为一体。具体而言，导电材料15形成于将半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接的导线14中的位于半导体芯片10、11及电路图案8处的部位。板状导电材料16载置于多个导电材料15，经由多个导电材料15固定于多个导线14。
下面，对导体21的形成方法进行说明。首先，如图6(a)所示，在将多个导线14键合后，在将半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接的导线14中的位于半导体芯片10、11及电路图案8处的部位，通过滴涂器50对导电性膏15a进行涂敷。接着，如图6(b)所示，经由导电性膏15a将板状导电材料16载置于导线14。接着，例如通过进行加热处理而使导电性膏15a固化，从而板状导电材料16经由导电材料15固定于多个导线14而形成导体21。由此，导体21将多个导线14电连接。此外，实施方式3涉及的半导体装置也可以具有在实施方式1、2中说明过的导体20。
如上所述，就实施方式3涉及的半导体装置而言，导体21具有：导电材料15，其形成于导线14；以及板状导电材料16，其经由导电材料15固定于导线14。因此，能够得到与实施方式1的情况相同的效果。此外，通过采用具有厚度的板状导电材料作为板状导电材料16，会预期半导体芯片10、11工作时的电流密度的减轻效果的增加。
由于导体21是通过在将导电性膏15a涂敷于导线14后，经由导电性膏15a将板状导电材料16载置于导线14，使导电性膏15a固化而形成的，因此能够容易地在导线14形成导体21。
<实施方式4>
接着，对实施方式4涉及的半导体装置进行说明。图8是实施方式4涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式4中，对与实施方式1～3中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图8所示，在实施方式4中，1个导体21连接于被并联连接的多个半导体芯片10、11。具体而言，3组半导体芯片10、11并联连接，1个导体21连接于3组半导体芯片10、11和电路图案8。此外，由于相对于导线14的导体21的形成方法与实施方式3的情况相同，因此省略说明。
如上所述，就实施方式4涉及的半导体装置而言，由于多个半导体芯片10、11以多组并联连接，通过1个导体21将多组的多个半导体芯片之间10、11连接，因此能够得到与实施方式3的情况相同的效果。
<实施方式5>
接着，对实施方式5涉及的半导体装置进行说明。图9是实施方式5涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式5中，对与实施方式1～4中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图9所示，在实施方式5中，导体单独地连接于被并联连接的多组的多个半导体芯片10、11。具体而言，3组半导体芯片10、11并联连接，3个导体21分别连接于3组半导体芯片10、11和电路图案8。此外，由于相对于导线14的导体21的形成方法与实施方式3的情况相同，因此省略说明。
如上所述，就实施方式5涉及的半导体装置而言，由于导体21单独地连接于被并联连接的多组的多个半导体芯片10、11，因此能够得到与实施方式3的情况相同的效果。
<实施方式6>
接着，对实施方式6涉及的半导体装置进行说明。图10是实施方式6涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。图11是没有设置导体22的情况下的半导体芯片10、11及其周边的俯视图。此外，在实施方式6中，对与实施方式1～5中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图10所示，在实施方式6中，对于被并联连接的多组的多个半导体芯片10、11，通过导体22使相邻的半导体芯片10之间及相邻的半导体芯片11之间的导线14导通。具体而言，导体22在相邻的半导体芯片10及相邻的半导体芯片11处，与一个半导体芯片10、11处的位于另一个半导体芯片10、11侧的导线14、另一个半导体芯片10、11处的位于一个半导体芯片10、11侧的导线14形成为一体。导体22具有导电材料15(参照图6)和板状导电材料17。
在没有设置导体22的情况下，为了对阻尼振荡进行抑制，如图11所示，实施将阻尼振荡抑制用的导线14a连接于被并联连接的3组半导体芯片10之间这一对策。但是，需要确保用于对阻尼振荡抑制用的导线14a进行连接的空间，成为半导体装置的小型化的妨碍。
相对于此，就实施方式6涉及的半导体装置而言，导体22在相邻的半导体芯片10、11处，与一个半导体芯片10、11处的位于另一个半导体芯片10、11侧的导线14、另一个半导体芯片10、11处的位于一个半导体芯片10、11侧的导线14形成为一体。
因此，不需要确保用于对阻尼振荡抑制用的导线14a进行连接的空间。由此，在采取阻尼振荡对策的情况下，也能够实现半导体装置的小型化。
<实施方式7>
接着，对实施方式7涉及的半导体装置进行说明。图12是实施方式7涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式7中，对与实施方式1～6中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图12所示，实施方式7是将实施方式5和实施方式6组合后的结构。即，在实施方式7中，导体21单独地连接于被并联连接的多组的多个半导体芯片10、11，并且对于被并联连接的多组的多个半导体芯片10、11，通过导体22使相邻的半导体芯片10之间及相邻的半导体芯片11之间的导线14导通。
如上所述，由于实施方式7涉及的半导体装置具有上述结构，因此能够得到实施方式5的情况下和实施方式6的情况下的效果。
<实施方式8>
接着，对实施方式8涉及的半导体装置进行说明。图13是实施方式8涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式8中，对与实施方式1～7中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图13所示，在实施方式8中，多个导线14连续地且彼此成角度地进行配线，导体21沿连续地配线的多个导线14的长度方向与导线14形成为一体。
在将导线14连接于半导体芯片10、11和电路图案8时，有时需要如θ所示地形成角度。在连接导线14时形成角度的情况下，为了避免导线14和导线键合工具的接触，与没有形成角度的情况相比导线14的根数趋于减少，因此有时导线14的电流密度增加。
相对于此，就实施方式8涉及的半导体装置而言，导线14为多个，多个导线14连续地且彼此成角度地进行配线，导体21沿连续地配线的多个导线14的长度方向与导线14形成为一体。因此，得到与实施方式1的情况相同的效果，所以即使是根数少的导线14也能够将电流密度抑制得低。
<实施方式9>
接着，对实施方式9涉及的半导体装置进行说明。图14是用于说明实施方式9涉及的半导体装置的制造方法的俯视图。具体而言，图14(a)是表示将板状导电材料16连接于半导体芯片11和电路图案8之间之前的状态的俯视图。图14(b)是表示将板状导电材料16连接于半导体芯片11和电路图案8之间之后的状态的俯视图。此外，在实施方式9中，对与实施方式1～8中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图14(b)所示，在实施方式9中，不通过导线14将半导体芯片11和电路图案8之间连接，而通过板状导电材料16连接。
半导体装置具有：绝缘基板5，其具有电路图案8；多个半导体芯片10、11，它们搭载于电路图案8之上；以及板状导电材料16，其将半导体芯片11和电路图案8之间连接。
接着，对板状导电材料16的连接方法进行说明。如图14(a)所示，首先，在将多个导线14键合后，以与实施方式3的情况相同的方法在半导体芯片10、11之间形成导体21。接着，如图14(b)所示，在将导电性膏涂敷于半导体芯片11和电路图案8之间的连接部位后，经由导电性膏将板状导电材料16载置于连接部位。接着，例如通过进行加热处理而使导电性膏固化，从而将板状导电材料16连接于半导体芯片11和电路图案8之间。
此外，也可以替代与导线14一体化后的导体21，通过与导线14一体化后的导体20将半导体芯片10、11之间连接。另外，也可以不通过与导线14一体化后的导体21将半导体芯片10、11之间连接，而通过板状导电材料16连接。另外，也可以通过与导线14一体化后的导体20或导体21将半导体芯片11和电路图案8之间连接，通过板状导电材料16将半导体芯片10、11之间连接。
如上所述，实施方式9涉及的半导体装置具有：绝缘基板5，其具有电路图案8；多个半导体芯片10、11，它们搭载于电路图案8之上；以及板状导电材料16，其将多个半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接。
因此，能够得到与实施方式1的情况相同的效果。特别地，由于相对于难以进行使用了导线14的配线的布局也能够形成配线，因此能够进一步实现半导体装置的设计自由度的提高及小型化。
板状导电材料16是通过在将导电性膏涂敷于多个半导体芯片10、11之间的连接部位、及半导体芯片11和电路图案8之间的连接部位后，经由导电性膏将板状导电材料16载置于连接部位，使导电性膏固化而进行连接的。因此，能够将板状导电材料16容易地连接于多个半导体芯片10、11之间的连接部位、及半导体芯片11和电路图案8之间的连接部位。
还具有将多个半导体芯片10、11之间、及半导体芯片11和电路图案8之间分别进行连接的导线14、与导线14形成为一体的导体20或导体21。因此，通过使板状导电材料16和导体20或导体21并存，进一步提高了半导体装置的设计自由度。
<实施方式10>
接着，对实施方式10涉及的半导体装置进行说明。图15是实施方式10涉及的半导体装置所具有的半导体芯片10、11及其周边的俯视图。此外，在实施方式10中，对与实施方式1～9中说明过的结构要素相同的结构要素标注相同标号并省略说明。
如图15所示，在实施方式10中，1个板状导电材料16连接于被并联连接的多个半导体芯片10、11。具体而言，3组半导体芯片10、11并联连接，1个板状导电材料16连接于3组半导体芯片10、11和电路图案8。此外，由于板状导电材料16的连接方法与实施方式9的情况相同，因此省略说明。
另外，与实施方式9的情况相同地，例如，也可以通过1个板状导电材料16将配置于电路图案8侧的2组的多个半导体芯片10、11之间、及半导体芯片10、11和电路图案8之间连接，通过与导线14一体化后的导体20或导体21将剩余的1组的多个半导体芯片10、11之间连接。即，1个板状导电材料16和导体20或导体21也可以并存。
如上所述，就实施方式10涉及的半导体装置而言，由于多个半导体芯片10、11以多组并联连接，通过1个板状导电材料16将多组的多个半导体芯片10、11之间、及半导体芯片10、11和电路图案8之间连接。
并且，还具有将多个半导体芯片10、11之间、及半导体芯片10、11和电路图案8之间分别进行连接的导线14、与导线14形成为一体的导体20或导体21。由此，能够得到与实施方式9的情况相同的效果。
此外，本发明可以在其发明的范围内将各实施方式自由地组合，对各实施方式适当进行变形、省略。

Claims (17)

1.一种半导体装置，其具有：
绝缘基板，其具有电路图案；
多个半导体芯片，它们搭载于所述电路图案之上；
导线，其将多个所述半导体芯片之间、及所述半导体芯片和所述电路图案之间分别进行连接；以及
导体，其与所述导线形成为一体。
2.根据权利要求1所述的半导体装置，其中，
所述导体也形成于所述半导体芯片的与所述导线的连接部位的周边部。
3.根据权利要求1所述的半导体装置，其中，
所述导体的线膨胀系数比所述导线的线膨胀系数小。
4.根据权利要求1所述的半导体装置，其中，
所述导线具有由Al构成的基材和覆盖所述基材的由Ni或Cu构成的覆膜。
5.根据权利要求1所述的半导体装置，其中，
所述导体为导电材料。
6.根据权利要求1所述的半导体装置，其中，
所述导线为带状导线。
7.根据权利要求1所述的半导体装置，其中，
所述导体具有：导电材料，其形成于所述导线；以及板状导电材料，其经由所述导电材料固定于所述导线。
8.根据权利要求7所述的半导体装置，其中，
多个所述半导体芯片以多组并联连接，
通过1个所述导体将多组的多个所述半导体芯片之间连接。
9.根据权利要求1所述的半导体装置，其中，
所述导体在相邻的所述半导体芯片处，与一个所述半导体芯片处的位于另一个所述半导体芯片侧的所述导线、另一个所述半导体芯片处的位于一个所述半导体芯片侧的所述导线形成为一体，
所述导体具有：导电材料，其形成于所述导线；以及板状导电材料，其经由所述导电材料固定于所述导线。
10.根据权利要求1所述的半导体装置，其中，
所述导线为多个，
多个所述导线连续地且彼此成角度地进行配线，
所述导体沿连续地配线的多个所述导线的长度方向与所述导线形成为一体。
11.一种半导体装置，其具有：
绝缘基板，其具有电路图案；
多个半导体芯片，它们搭载于所述电路图案之上；以及
板状导电材料，其将多个所述半导体芯片之间、及所述半导体芯片和所述电路图案之间分别进行连接。
12.根据权利要求11所述的半导体装置，其中，
多个所述半导体芯片以多组并联连接，
通过1个所述板状导电材料将多组的多个所述半导体芯片之间、及所述半导体芯片和所述电路图案之间连接。
13.根据权利要求11或12所述的半导体装置，其中，
还具有：导线，其将多个所述半导体芯片之间、及所述半导体芯片和所述电路图案之间分别进行连接；以及
导体，其与所述导线形成为一体。
14.根据权利要求1至13中任一项所述的半导体装置，其中，
多个所述半导体芯片由宽带隙半导体形成。
15.一种半导体装置的制造方法，其为权利要求5所记载的半导体装置的制造方法，其中，
所述导体是通过将导电性膏涂敷于所述导线并固化而形成的。
16.一种半导体装置的制造方法，其为权利要求7所记载的半导体装置的制造方法，其中，
所述导体是通过在将导电性膏涂敷于所述导线后，经由所述导电性膏将所述板状导电材料载置于所述导线，使所述导电性膏固化而形成的。
17.一种半导体装置的制造方法，其为权利要求11所记载的半导体装置的制造方法，其中，
所述板状导电材料是通过在将导电性膏涂敷于多个所述半导体芯片之间的连接部位、及所述半导体芯片和所述电路图案之间的连接部位后，经由所述导电性膏将所述板状导电材料载置于所述连接部位，使所述导电性膏固化而进行连接的。
CN202010264074.1A 2019-04-12 2020-04-07 半导体装置及半导体装置的制造方法 Pending CN111816633A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019076289A JP7195208B2 (ja) 2019-04-12 2019-04-12 半導体装置および半導体装置の製造方法
JP2019-076289 2019-04-12

Publications (1)

Publication Number Publication Date
CN111816633A true CN111816633A (zh) 2020-10-23

Family

ID=72613709

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010264074.1A Pending CN111816633A (zh) 2019-04-12 2020-04-07 半导体装置及半导体装置的制造方法

Country Status (4)

Country Link
US (1) US11532590B2 (zh)
JP (1) JP7195208B2 (zh)
CN (1) CN111816633A (zh)
DE (1) DE102020204406A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6952824B2 (ja) * 2020-04-06 2021-10-27 三菱電機株式会社 パワーモジュール及びこれを用いた電力用半導体装置
JP7282147B1 (ja) * 2021-12-01 2023-05-26 三菱電機株式会社 半導体装置および電力変換装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243778A (ja) * 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US20020024134A1 (en) * 2000-08-28 2002-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2002203878A (ja) * 2000-11-02 2002-07-19 Nippon Steel Corp 半導体装置およびその製造方法
US20100308457A1 (en) * 2009-06-03 2010-12-09 Nec Electronics Corporation Semiconductor apparatus and manufacturing method of the same
CN104821282A (zh) * 2014-01-30 2015-08-05 株式会社日立功率半导体 功率半导体组件

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3877885A (en) * 1970-12-02 1975-04-15 Texas Instruments Inc Copper-clad aluminum wire and method of making
JPS5697655A (en) 1980-01-09 1981-08-06 Nippon Denso Co Ltd Power transmission
JPS6097655A (ja) * 1983-11-02 1985-05-31 Hitachi Ltd ボンデイング用ワイヤ
US7084656B1 (en) * 1993-11-16 2006-08-01 Formfactor, Inc. Probe for semiconductor devices
US6727579B1 (en) * 1994-11-16 2004-04-27 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US20020113322A1 (en) * 2000-06-12 2002-08-22 Shinichi Terashima Semiconductor device and method to produce the same
US20060189119A1 (en) * 2005-01-24 2006-08-24 Michael Jin Encapsulation of circuit components to reduce thermal cycling stress
DE102005028951B4 (de) 2005-06-22 2018-05-30 Infineon Technologies Ag Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung
JP5110996B2 (ja) 2007-07-20 2012-12-26 新光電気工業株式会社 積層型半導体装置の製造方法
US7956469B2 (en) * 2007-07-27 2011-06-07 Nichia Corporation Light emitting device and method of manufacturing the same
JP2009071156A (ja) * 2007-09-14 2009-04-02 Toshiba Corp 半導体装置及びその製造方法
US8815019B2 (en) * 2009-03-17 2014-08-26 Nippon Steel & Sumikin Materials., Ltd. Bonding wire for semiconductor
US9461023B2 (en) * 2011-10-28 2016-10-04 Bridgelux, Inc. Jetting a highly reflective layer onto an LED assembly
DE102012208251A1 (de) 2012-05-16 2013-11-21 Robert Bosch Gmbh Elektrische Kontaktierung für Halbleiter
JP6305302B2 (ja) 2014-10-02 2018-04-04 三菱電機株式会社 半導体装置およびその製造方法
SG10201509634UA (en) * 2015-11-23 2017-06-29 Heraeus Oriental Hitec Co Ltd Coated wire
JP6410998B1 (ja) 2017-04-12 2018-10-24 三菱電機株式会社 半導体モジュール、半導体モジュールの製造方法および電力変換装置
US11063025B2 (en) 2017-09-04 2021-07-13 Mitsubishi Electric Corporation Semiconductor module and power conversion device
US10629562B2 (en) * 2017-12-29 2020-04-21 Texas Instruments Incorporated Integrated circuit packaging
WO2019241737A1 (en) * 2018-06-14 2019-12-19 Caprice Gray Haley Coaxial wire
US20200203243A1 (en) * 2018-12-19 2020-06-25 Texas Instruments Incorporated Universal leaded/leadless chip scale package for microelecronic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243778A (ja) * 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US20020024134A1 (en) * 2000-08-28 2002-02-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2002203878A (ja) * 2000-11-02 2002-07-19 Nippon Steel Corp 半導体装置およびその製造方法
US20100308457A1 (en) * 2009-06-03 2010-12-09 Nec Electronics Corporation Semiconductor apparatus and manufacturing method of the same
CN104821282A (zh) * 2014-01-30 2015-08-05 株式会社日立功率半导体 功率半导体组件

Also Published As

Publication number Publication date
JP7195208B2 (ja) 2022-12-23
JP2020174156A (ja) 2020-10-22
US11532590B2 (en) 2022-12-20
US20200328178A1 (en) 2020-10-15
DE102020204406A1 (de) 2020-10-15

Similar Documents

Publication Publication Date Title
US8451621B2 (en) Semiconductor component and method of manufacture
US8324722B2 (en) Packaging device for matrix-arrayed semiconductor light-emitting elements of high power and high directivity
US7466012B2 (en) Power semiconductor package
US6972479B2 (en) Package with stacked substrates
CN107615464B (zh) 电力用半导体装置的制造方法以及电力用半导体装置
US9911680B2 (en) Bidirectional semiconductor package
US8546926B2 (en) Power converter
US9433075B2 (en) Electric power semiconductor device
US20080029875A1 (en) Hermetically sealed semiconductor device module
JP2006253516A (ja) パワー半導体装置
JP2010283053A (ja) 半導体装置及びその製造方法
KR20100064629A (ko) 외부 본딩 영역을 구비하는 반도체 파워 모듈 패키지
JP2005064479A (ja) 回路モジュール
JP6305176B2 (ja) 半導体装置及び製造方法
CN111816633A (zh) 半导体装置及半导体装置的制造方法
KR102199360B1 (ko) 반도체 패키지
JP2017034152A (ja) 電力用半導体装置
JP2015023226A (ja) ワイドギャップ半導体装置
JP4038173B2 (ja) 電力用半導体装置
CN116190339A (zh) 端子元件或汇流条以及包括端子元件或汇流条的功率半导体模块装置
US20020030276A1 (en) Dimple array interconnect technique for semiconductor device
CN111900135A (zh) 功率半导体模块装置
JP3297959B2 (ja) 半導体装置
US11462504B2 (en) Semiconductor apparatus
US11837571B2 (en) Semiconductor module comprising a first and second connecting element for connecting a semiconductor chip, and also production method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination