WO2018189948A1 - 半導体モジュール、半導体モジュールの製造方法および電力変換装置 - Google Patents

半導体モジュール、半導体モジュールの製造方法および電力変換装置 Download PDF

Info

Publication number
WO2018189948A1
WO2018189948A1 PCT/JP2017/043423 JP2017043423W WO2018189948A1 WO 2018189948 A1 WO2018189948 A1 WO 2018189948A1 JP 2017043423 W JP2017043423 W JP 2017043423W WO 2018189948 A1 WO2018189948 A1 WO 2018189948A1
Authority
WO
WIPO (PCT)
Prior art keywords
wire
conductor
semiconductor module
surface electrode
semiconductor element
Prior art date
Application number
PCT/JP2017/043423
Other languages
English (en)
French (fr)
Inventor
悠策 伊藤
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2018527816A priority Critical patent/JP6410998B1/ja
Priority to CN201780089024.0A priority patent/CN110462805A/zh
Priority to US16/486,924 priority patent/US10930616B2/en
Priority to DE112017007430.4T priority patent/DE112017007430T5/de
Publication of WO2018189948A1 publication Critical patent/WO2018189948A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/85801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/8584—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor module, a method for manufacturing a semiconductor module, and a power converter, and more particularly, to a power semiconductor module including a power semiconductor element, a method for manufacturing the power semiconductor module, and a power converter.
  • a semiconductor module usually includes a substrate having a conductor pattern, a semiconductor element having a back surface bonded to the conductor pattern and a surface provided with a surface electrode, and a bonding wire bonded to the surface electrode.
  • Some semiconductor modules have a semiconductor element and a wire electrically connected without bonding the wire.
  • An example of such a semiconductor module is described in Japanese Patent No. 3809379 (Patent Document 1).
  • Patent Document 1 a protective film having an opening covers the surface electrode disposed on the surface of the semiconductor element. The wire and the surface electrode are joined by solder at the opening of the protective film.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor capable of extending the life of a wire junction with a surface electrode of a semiconductor element and reducing the current density per wire.
  • a module, a method for manufacturing a semiconductor module, and a power conversion device are provided.
  • the semiconductor module of the present invention includes a substrate, a semiconductor element, and a wire.
  • the semiconductor element is bonded on the substrate and has a surface electrode.
  • Each end of the wire is bonded to the substrate across the surface electrode of the semiconductor element.
  • the wire is electrically connected to the surface electrode.
  • each end of the wire is bonded to the substrate across the surface electrode of the semiconductor element, and is electrically connected to the surface electrode. For this reason, since notch shape is not formed in the junction part of the wire with a surface electrode, it can suppress that stress concentrates on the edge of the junction part of a wire. Further, since bonding wires are used, the number of wires can be increased as compared with the case where the wires are joined by solder. Therefore, it is possible to extend the life of the joint between the surface electrode of the semiconductor element and the wire and to reduce the current density per wire.
  • FIG. 3 is an end view taken along line III-III in FIGS. 1 and 2. It is a front view which shows roughly the structure of the semiconductor module which concerns on Embodiment 2 of this invention. It is a top view which shows roughly the structure of the semiconductor module which concerns on Embodiment 2 of this invention.
  • FIG. 6 is an end view taken along line VI-VI in FIG. 5. It is a front view which shows roughly the structure of the semiconductor module which concerns on the modification 1 of Embodiment 2 of this invention.
  • FIG. 8 is an end view taken along line IX-IX in FIG. 7. It is an end view which shows roughly the structure of the semiconductor module which concerns on the modification 2 of Embodiment 2 of this invention. It is a top view which shows roughly the structure of the semiconductor module which concerns on the modification 3 of Embodiment 2 of this invention.
  • FIG. 12 is an end view taken along line XII-XII in FIG. 11. It is a front view which shows roughly the structure of the semiconductor module which concerns on Embodiment 3 of this invention. It is a top view which shows roughly the structure of the semiconductor module which concerns on Embodiment 3 of this invention.
  • FIG. 8 is an end view taken along line IX-IX in FIG. 7. It is an end view which shows roughly the structure of the semiconductor module which concerns on the modification 2 of Embodiment 2 of this invention. It is a top view which shows roughly the structure of the semiconductor module which concerns on the modification 3 of Embodiment 2 of this invention.
  • FIG. 12 is an end view taken along line X
  • FIG. 15 is an enlarged cross-sectional view taken along line XV-XV in FIG. 14 in the XV portion in FIG. 13. It is a block diagram which shows the structure of the power conversion system to which the power converter device which concerns on Embodiment 4 of this invention is applied.
  • FIG. 1 is a front view of the semiconductor module according to the present embodiment.
  • FIG. 2 is a top view of the semiconductor module according to the present embodiment.
  • FIG. 3 is an end view of the semiconductor module according to the present embodiment.
  • the semiconductor module according to the present embodiment mainly includes a substrate 1, a bonding material 2, a semiconductor element 3, a bonding material 5, a conductor 6, and a bonding It has a material 7 and a wire 8.
  • Conductor patterns 1a, 1b and 1c are provided on the surface of the substrate 1.
  • the bonding material 2 is for bonding the conductor pattern 1 b of the substrate 1 and the semiconductor element 3.
  • the bonding material 2 has conductivity.
  • the semiconductor element 3 is bonded on the substrate 1.
  • the semiconductor element 3 has a surface electrode 4.
  • the surface electrode 4 is provided on the surface of the semiconductor element 3.
  • a conductor 6 is bonded onto the surface electrode 4 of the semiconductor element 3 via a bonding material 5.
  • the surface electrode 4 and the conductor 6 of the semiconductor element 3 do not need to be joined only by the joining material 5, and another conductor and the joining material may be sandwiched between each other.
  • the bonding material 7 bonds the conductor 6 and the wire 8 together.
  • Each end 8 a of the wire 8 is bonded to the substrate 1 across the surface electrode 4 of the semiconductor element 3.
  • the wire 8 is electrically connected to the surface electrode 4.
  • the wire 8 is bonded at both ends 8 a to the conductor pattern 1 b and the conductor pattern 1 c and is bridged across the semiconductor element 3.
  • the wire 8 is electrically connected to the surface electrode 4 above the surface electrode 4.
  • the substrate 1 has conductor patterns 1a, 1b, 1c, and 1e and an insulating layer 1d. Conductive patterns 1a, 1b, 1c, and 1e are provided on insulating layer 1d. Specifically, the substrate 1 includes a conductor pattern 1a, 1b, and 1c provided on the front surface, and a conductor pattern provided on the back surface opposite to the surface on which the insulating layer 1d and the semiconductor element 3 are mounted. 1e. That is, the conductor patterns 1a, 1b, and 1c are disposed on the surface of the insulating layer 1d, and the conductor pattern 1e is disposed on the back surface of the insulating layer 1d.
  • the semiconductor element 3 is disposed between the conductor pattern (first conductor portion) 1a and the conductor pattern (second conductor portion) 1c.
  • the first end 8a1 of the both ends 8a of the wire 8 is bonded to the conductor pattern (first conductor) 1a, and the second end 8a2 of the both ends 8a of the wire 8 is the second conductor pattern ( Bonded to the second conductor portion 1c.
  • Al 2 O 3 aluminum oxide
  • AlN aluminum nitride
  • Cu copper
  • the semiconductor module according to the present embodiment has a base plate 10.
  • the base plate 10 is made of a material having high thermal conductivity.
  • the upper surface of the base plate 10 is bonded to a conductor pattern 1 e formed on the back surface of the substrate 1.
  • the conductor pattern 1 e and the base plate 10 are joined by a joining material 9.
  • As the bonding material 9 for example, solder and sinterable silver particles are used.
  • the semiconductor element 3 is, for example, a power semiconductor element having a vertical structure in which a current flows from the lower surface (back surface) to the upper surface (front surface).
  • the semiconductor element 3 is, for example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor), a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a rectifying element such as a Schottky barrier diode.
  • the semiconductor element 3 is formed using, for example, a single crystal of silicon (Si).
  • the semiconductor material constituting the semiconductor element 3 is not limited to a single crystal of silicon (Si), and may be a semiconductor material having a wide band gap such as silicon carbide (SiC) or silicon nitride (GaN). Good.
  • the lower surface of the semiconductor element 3 is electrically joined to the conductor pattern 1 b on the surface of the substrate 1.
  • the lower surface of the semiconductor element 3 and the conductor pattern 1b are bonded via a bonding material 2 having conductivity.
  • the bonding material 2 for example, solder, sinterable silver particles, or the like is used.
  • the semiconductor element 3 has a surface electrode 4.
  • the surface electrode 4 is formed on the surface (upper surface) of the semiconductor element 3.
  • an aluminum (Al) alloy containing silicon (Si) is used for the surface electrode 4.
  • the surface electrode 4 may have a coating layer.
  • nickel (Ni), gold (Au), or a structure in which these are laminated is used.
  • the conductor 6 is joined on the surface electrode 4.
  • the bonding material 5 is disposed on the conductor 6.
  • the surface electrode 4 and the conductor 6 are joined by a conductive joining material 5.
  • As the bonding material 5, for example, solder, sinterable silver particles, or the like is used.
  • the conductor 6 for example, copper (Cu) is used.
  • the conductor 6 may be a material different from the bonding material 5.
  • the wire 8 is bonded to the conductor 6 by a conductive bonding material 7.
  • the bonding material 7 for example, solder, sinterable silver particles, or the like is used.
  • the bonding material 7 is preferably a sintered body containing silver (Ag sintered body).
  • the conductor 6 may have a groove 6a into which the wire 8 and the bonding material 7 enter.
  • a groove 6 a is provided on the upper surface of the conductor 6.
  • the wire 8 and the bonding material 7 are arranged so as to enter the groove 6a. Since the conductor 6 has the groove 6 a, the wire 8 can be easily inserted into the groove 6 a and fixed by the bonding material 7.
  • the wire 8 may be a single wire or a plurality of wires.
  • the wire 8 is joined to the conductor patterns 1a and 1c. That is, one end of the wire 8 is joined to the conductor pattern 1a, and the other end of the wire 8 is joined to the conductor pattern 1c.
  • the conductor pattern 1a and the conductor pattern 1c may be separate patterns or may be a single connected pattern. When there are a plurality of wires 8, both ends of the wires 8 do not have to be bonded to the conductor patterns 1a and 1c, respectively, and some of the wires 8 are other conductors other than the conductor patterns 1a and 1c. It may be connected to the pattern.
  • gold (Au), aluminum (Al), copper (Cu), or the like is used for example.
  • the semiconductor element 3 is bonded to the conductive pattern 1 b provided on the surface of the substrate 1 by the bonding material 2.
  • the conductor 6 is bonded to the surface electrode 4 of the semiconductor element 3 by the bonding material 5.
  • both ends of the wire 8 are bonded to the conductor patterns 1a and 1c on the surface of the substrate 1 by ultrasonic bonding.
  • the wires 8 are bonded to the conductor patterns 1 a and 1 c of the substrate 1 at both ends 8 a of the wires 8 across the surface electrode 4 of the semiconductor element 3.
  • a wire 8 bonded to the conductor patterns 1 a and 1 c of the substrate 1 is electrically connected to the surface electrode 4 of the semiconductor element 3.
  • the wire 8 After the joining of the both ends of the wire 8 and the conductor patterns 1 a and 1 c, the wire 8 may be pushed and deformed so as to approach the conductor 6. At that time, as shown in FIG. 6, when the conductor 6 has a groove 6a for inserting the wire 8, the wire 8 is inserted into the groove 6a so that the wire 8 enters the groove 6a of the conductor 6. You may push it in. After the wire 8 is pushed into the groove 6a, the conductor 6 and the wire 8 are joined by the joining material 7 in the groove 6a. As a result, the semiconductor module shown in FIGS. 1 to 3 is manufactured.
  • the wire 8 is bonded to the conductor 6 by the conductive bonding material 7, for example, from the lower surface to the surface electrode 4 in the vertical direction with respect to the semiconductor element 3.
  • the flowing current can flow in the order of the conductive bonding material 5, the conductor 6, the conductive bonding material 7, the wire 8, and the conductor patterns 1a and 1c.
  • the wire 8 is bonded to the surface electrode 4 of the semiconductor element 3 by ultrasonic bonding as in the above-described normal semiconductor module, a notch shape is formed at the bonding portion of the wire 8 with the surface electrode 4. Is formed. For this reason, when the temperature changes due to repeated heat generation and cooling during operation of the semiconductor module, stress concentrates on the end of the notch shape at the joint portion of the wire 8, and breakage occurs from the end of the notch shape. In other words, in the semiconductor module, the change in temperature is greatest around the semiconductor element.
  • the normal conductor module has a wire bonding portion by ultrasonic bonding in which stress is concentrated around the semiconductor element having the largest temperature change. For this reason, there is a problem in terms of reliability. Moreover, it can be easily created using a conventional wire bonding apparatus.
  • both ends 8 a of the wire 8 straddle the surface electrode 4 of the semiconductor element 3 are bonded to the substrate 1 and are electrically connected to the surface electrode 4. .
  • notch shape is not formed in the junction part of the wire 8 with the surface electrode 4, it can suppress that stress concentrates on the edge of the junction part of the wire 8.
  • FIG. Therefore, the life of the joint portion of the wire 8 with the surface electrode 4 of the semiconductor element 3 can be extended.
  • the number of the wires 8 can be increased as compared with the case where the wire 8 is joined to the surface electrode 4 by solder. Therefore, the current density per wire can be reduced.
  • the wire 8 is bonded to the substrate 1 across the surface electrode 4, a current can flow toward both ends of the wire 8. Thereby, the current density per wire can be reduced.
  • the semiconductor element 3 is disposed between the conductor pattern (first conductor portion) 1a and the conductor pattern 1c (second conductor portion).
  • the wire 8 can be electrically connected to the surface electrode 4 across the surface electrode 4 of the semiconductor element 3.
  • the first end 8a1 is bonded to the conductor pattern 1a, and among the both ends 8a of the wire 8, the first end 8a1 is bonded to the conductor pattern 1c. For this reason, an electric current can be sent toward each of the both ends 8a of the wire 8.
  • the wire 8 is joined to the conductor 6 joined to the surface electrode 4 by the joining material 7.
  • the conductor 6 and the wire 8 electrically connected to the semiconductor element 3 can be joined by the joining material 7 instead of the ultrasonic joining. Therefore, since the joint portion between the conductor 6 and the wire 8 is not a notch shape, the life of the joint portion between the wire 8 and the conductor 6 can be extended.
  • the wire 8 When the wire 8 is bonded to the surface electrode 4 of the semiconductor element 3 and when the wire 8 is bonded to the surface electrode 4 of the semiconductor element 3 with a bonding material such as solder, generally, the wire 8
  • the linear expansion coefficient is larger than the linear expansion coefficient of the semiconductor element 3 by several times. Therefore, thermal stress due to the difference between the linear expansion coefficient of the semiconductor element 3 and the linear expansion coefficient of the wire 8 is generated when the temperature changes due to repeated heat generation and cooling during operation of the semiconductor module.
  • this thermal stress is generated in the vicinity of the bonding surface where the wire 8 is bonded to the surface electrode 4 and in the bonding material obtained by bonding the semiconductor element 3 and the wire 8, the bonding surface and the bonding material are likely to be broken.
  • the conductor 6 since the conductor 6 is interposed between the semiconductor element 3 and the wire 8, thermal stress due to the difference in linear expansion coefficient between the conductor 6 and the wire 8, and the semiconductor element 3 and the conductor 6 What is necessary is to consider the thermal stress due to the difference in linear expansion coefficient. Since the conductor 6 and the wire 8 generally have a small linear expansion coefficient difference, the generated thermal stress is small. Although the linear expansion coefficient difference between the semiconductor element 3 and the conductor 6 is large, the end of the joint portion between the semiconductor element 3 and the conductor 6 does not have a notch shape, so that the generated thermal stress can be suppressed low. Furthermore, since the bonding area between the semiconductor element 3 and the conductor 6 is several tens of times larger than the area of wire bonding, the life of the bonded portion can be extended.
  • the wire 8 and the bonding material 7 are arranged so as to enter the groove 6a, it is easy to insert the wire 8 into the groove 6a and fix it with the bonding material 7. Become.
  • the bonding material 7 is a sintered body containing silver. Therefore, the lifetime of the junction part of the wire 8 can be extended by using a highly heat-resistant and highly reliable joining material. Therefore, the reliability of the semiconductor module can be greatly improved.
  • the material of the wire 8 is copper. Therefore, the cost of the semiconductor module can be reduced.
  • the manufacturing method of the semiconductor module according to the present embodiment includes the following steps. Each of both end portions 8 a of the wire 8 is bonded to the substrate 1 across the surface electrode 4 of the semiconductor element 3 bonded to the substrate 1. A wire 8 bonded to the substrate 1 is electrically connected to the surface electrode 4 of the semiconductor element 3. Therefore, it is possible to manufacture a semiconductor module capable of extending the life of the joint between the surface electrode 4 of the semiconductor element 3 and the wire 8 and reducing the current density per wire.
  • the semiconductor module manufacturing method further includes the following configuration.
  • a conductor 6 having a groove 6 a on the upper surface is joined onto the surface electrode 4. After the wire 8 is pushed into the groove 6a, the conductor 6 and the wire 8 are joined with the conductive joining material 7 in the groove 6a. It becomes easy to insert the wire 8 into the groove 6 a and fix it with the bonding material 7.
  • the wiring structure on the chip can be wired using a conventional wire and a wire bonding apparatus without using a copper plate other than wires, there is an advantage that manufacture is easy.
  • FIG. 7 is a front view of the semiconductor module according to the present embodiment.
  • FIG. 5 is a top view of the semiconductor module according to the present embodiment.
  • FIG. 6 is an end view of the semiconductor module according to the present embodiment.
  • the semiconductor module according to the present embodiment mainly includes a substrate 1, a bonding material 2, a semiconductor element 3, and the semiconductor module according to the first embodiment. , A bonding material 5, a conductor 6, a bonding material 7, and a wire 8.
  • the wires 8 may be bonded to the conductor patterns 1a and 1c in two rows. Moreover, as FIG. 9 shows, when the wire 8 is joined in the groove
  • the manufacturing method of the semiconductor module according to the present embodiment is the same as the manufacturing method of the semiconductor module according to the first embodiment.
  • the wires 8 when they are bonded, they are arranged in two rows. The only difference is that it is bonded to the conductor patterns 1a and 1c.
  • the wires 8 may be bonded in three or more rows, and both end portions 8a of the wires 8 may be bonded to arbitrary positions of the conductor patterns 1a and 1c.
  • the number of the wires 8 that are electrically connected to one semiconductor element 3 is reduced by connecting the wires 8 to the conductor 6 in two or more stages. It can be arbitrarily increased without depending on the surface area. In the semiconductor module, not only the semiconductor element 3 but also heat generated by the loss in the wire 8 is a factor that shortens the life of the semiconductor module. In this embodiment, since the current density per wire can be reduced, the life of the semiconductor module can be extended.
  • the second-stage wire 8 is arranged between the first-stage wires 8, and the second-stage wires are connected to each other.
  • a first-stage wire is arranged between them. That is, the first-stage wires 8 and the second-stage wires 8 are arranged so as to close each other between the first-stage wires 8 and between the second-stage wires 8.
  • the distance in the stacking direction between the first-stage wire 8 and the second-stage wire 8 can be shortened. Therefore, the semiconductor module can be reduced in size.
  • a conductor 12 is further bonded onto the conductor 6 via a conductive bonding material 11.
  • the conductor 12 has a groove 12a.
  • the wire 14 is joined by the conductive joining material 13 in the groove 12a.
  • gold (Au), aluminum (Al), copper (Cu), or the like is used.
  • copper (Cu) is used as the conductor 12.
  • bonding material 13 for example, solder, sinterable silver particles, or the like is used.
  • the wire 8 and the wire 14 are disposed so as to straddle the surface electrode 4 of the semiconductor element 3 in a direction crossing each other.
  • the conductor 6 and the wire 8 are joined by the joining material 7 first, and then the wire 14 and the conductor 12 are joined by the joining material 13.
  • the bonding material 7 and the bonding material 13 may be cured at the same time.
  • the direction in which the wire 8 and the wire 14 straddle the surface electrode 4 of the semiconductor element 3 can be made different from each other. Thereby, the freedom degree of arrangement
  • positioning of a wire can be improved.
  • FIG. 13 is a front view of the semiconductor module according to the present embodiment.
  • FIG. 14 is a top view of the semiconductor module according to the present embodiment.
  • 15 is an enlarged cross-sectional view of the XV portion in FIG. 13 of the semiconductor module according to the present embodiment, taken along line XV-XV in FIG.
  • the semiconductor module according to the present embodiment mainly includes a substrate 1, a bonding material 2, a semiconductor element 3, and the semiconductor module according to the first embodiment. , A bonding material 5, a conductor 6, a bonding material 7, and a wire 8.
  • the area of the conductor 6 is smaller than the area of the semiconductor element 3.
  • the conductor 6 has a smaller area than the semiconductor element 3 when viewed from above. That is, the area of the upper surface of the conductor 6 is smaller than the area of the upper surface of the semiconductor element 3.
  • the vertical width of the conductor 6 is smaller than the vertical width of the semiconductor element 3
  • the horizontal width of the conductor 6 is smaller than the horizontal width of the semiconductor element 3.
  • the groove 6a has a depth at the center (inside) of the groove 6a along the direction in which the wire 8 straddles the surface electrode 4 in a cross-sectional view.
  • the shape may be deep and the end portion may be shallow. That is, the conductor 6 has a shape in which the depth of the end portion of the groove 6a is shallower than the depth of the central portion of the groove 6a along the direction in which the wire 8 straddles the surface electrode 4.
  • the depth of each end of the groove 6a may be shallower than the depth of the central part of the groove 6a.
  • the manufacturing process of the semiconductor module according to the present embodiment is the same as the manufacturing process of the semiconductor module according to the first embodiment.
  • the area of the conductor 6 is smaller than the area of the semiconductor element 3, so that a high voltage is applied and insulation is maintained. Therefore, it is possible to earn an insulation distance between the conductor pattern 1b and the wire 8 that require the above.
  • the depth of the end portion of the groove 6a is shallower than the depth of the central portion of the groove 6a along the direction in which the wire 8 straddles the surface electrode 4. It is possible to earn an insulation distance between the conductor pattern 1b and the wire 8 that require voltage and keep insulation.
  • Embodiment 4 FIG.
  • the semiconductor module according to Embodiments 1 to 3 described above is applied to a power conversion device.
  • the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a fourth embodiment.
  • FIG. 16 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 16 includes a power supply 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source and supplies DC power to the power conversion device 200.
  • the power source 100 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good.
  • the power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 16, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And.
  • the load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 201 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes.
  • Each switching element and each free-wheeling diode of the main conversion circuit 201 are configured by the semiconductor module 202 corresponding to any one of the first to third embodiments described above.
  • the six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.
  • the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element.
  • the drive circuit may be built in the semiconductor module 202, or a drive circuit may be provided separately from the semiconductor module 202. The structure provided may be sufficient.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element.
  • Signal (off signal) When the switching element is maintained in the ON state,
  • the control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.
  • the semiconductor module according to Embodiments 1 to 3 is applied as the switching element and the free wheel diode of main conversion circuit 201, the life of the power conversion device is increased, and the wire of the semiconductor module is used. It is possible to reduce the current density per line.
  • the present invention is not limited to this, and can be applied to various power conversion devices.
  • a two-level power converter is used.
  • a three-level or multi-level power converter may be used.
  • the present invention is applied to a single-phase inverter. You may apply.
  • the present invention can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor.
  • the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inverter Devices (AREA)
  • Wire Bonding (AREA)

Abstract

半導体モジュールは、基板（１）と、半導体素子（３）と、ワイヤ（８）とを備えている。半導体素子（３）は、基板（１）上に接合され、かつ表面電極（４）を有する。ワイヤ（８）は、半導体素子（３）の表面電極（４）をまたいで両端部（８ａ）の各々が基板（１）にボンディングされている。ワイヤ（８）は、表面電極（４）と電気的に接続されている。

Description

半導体モジュール、半導体モジュールの製造方法および電力変換装置
　本発明は、半導体モジュール、半導体モジュールの製造方法および電力変換装置に関し、特に、パワー半導体素子を含むパワー半導体モジュール、その製造方法および電力変換装置に関するものである。
　半導体モジュールは、通常、導体パターンを有する基板と、導体パターンに接合される裏面と表面電極が設けられている表面とを有する半導体素子と、表面電極に接合されたボンディングワイヤとを有している。
　また、半導体モジュールには、ワイヤがボンディングされずに半導体素子とワイヤとが電気的に接続されているものがある。このような半導体モジュールの一例が、特許第３８０９３７９号公報（特許文献１）に記載されている。この公報に記載された半導体モジュールにおいては、半導体素子の表面に配置された表面電極上を開口部を有する保護膜が覆っている。保護膜の開口部でワイヤと表面電極とが半田によって接合されている。
特許第３８０９３７９号公報
　上記の通常の半導体モジュールにおいては、表面電極にワイヤがボンディングされるため、表面電極とのワイヤの接合部において切欠き形状が形成される。このため、半導体モジュールの運用中の発熱、冷却の繰り返しによる温度変化時に、ワイヤの接合部において切欠き形状の端に応力が集中する。これにより、切欠き形状の端から破壊が発生する。したがって、半導体素子の表面電極にボンディングされたワイヤの接合部を長寿命化することは困難である。
　また、上記の公報に記載された半導体モジュールにおいては、超音波接合によるワイヤボンディングは行われないため、表面電極とのワイヤの接合部において切欠き形状は形成されない。しかしながら、ワイヤは表面電極に半田によって接合されているため、ワイヤボンディングに比べて、ワイヤの本数が制限される。したがって、ワイヤ一本あたりの電流密度を小さくすることは困難である。
　本発明は、上記課題に鑑みてなされたものであり、その目的は、半導体素子の表面電極とのワイヤの接合部を長寿命化し、かつワイヤ一本あたりの電流密度を小さくすることができる半導体モジュール、半導体モジュールの製造方法および電力変換装置を提供することである。
　本発明の半導体モジュールは、基板と、半導体素子と、ワイヤとを備えている。半導体素子は、基板上に接合され、かつ表面電極を有する。ワイヤは、半導体素子の表面電極をまたいで両端部の各々が基板にボンディングされている。ワイヤは、表面電極と電気的に接続されている。
　本発明の半導体モジュールによれば、ワイヤは、半導体素子の表面電極をまたいで両端部の各々が基板にボンディングされており、表面電極と電気的に接続されている。このため、表面電極とのワイヤの接合部において切欠き形状が形成されないので、ワイヤの接合部の端に応力が集中することを抑制することができる。また、ボンディングワイヤが用いられるため、ワイヤが半田によって接合される場合に比べて、ワイヤの本数を多くすることができる。したがって、半導体素子の表面電極とワイヤとの接合部を長寿命化し、かつワイヤ一本あたりの電流密度を小さくすることができる。
本発明の実施の形態１に係る半導体モジュールの構成を概略的に示す正面図である。 本発明の実施の形態１に係る半導体モジュールの構成を概略的に示す上面図である。 図１および図２のＩＩＩ－ＩＩＩ線に沿う端面図である。 本発明の実施の形態２に係る半導体モジュールの構成を概略的に示す正面図である。 本発明の実施の形態２に係る半導体モジュールの構成を概略的に示す上面図である。 図５のＶＩ－ＶＩ線に沿う端面図である。 本発明の実施の形態２の変形例１に係る半導体モジュールの構成を概略的に示す正面図である。 本発明の実施の形態２の変形例１に係る半導体モジュールの構成を概略的に示す上面図である。 図７のＩＸ－ＩＸ線に沿う端面図である。 本発明の実施の形態２の変形例２に係る半導体モジュールの構成を概略的に示す端面図である。 本発明の実施形態２の変形例３に係る半導体モジュールの構成を概略的に示す上面図である。 図１１のＸＩＩ－ＸＩＩ線に沿う端面図である。 本発明の実施の形態３に係る半導体モジュールの構成を概略的に示す正面図である。 本発明の実施の形態３に係る半導体モジュールの構成を概略的に示す上面図である。 図１３のＸＶ部分における図１４のＸＶ－ＸＶ線に沿う拡大断面図である。 本発明の実施の形態４に係る電力変換装置を適用した電力変換システムの構成を示すブロック図である。
　以下に、本発明の実施の形態について、図を参照して説明する。なお、各図中同一または相当部分には同一符号を付している。また、以下に記載する実施の形態の少なくとも一部を任意に組み合わせてもよい。
　実施の形態１．
　図１～図３を参照して、本発明の実施の形態１に係る半導体モジュールの構造について説明する。図１は、本実施の形態に係る半導体モジュールの正面図である。図２は、本実施の形態に係る半導体モジュールの上面図である。図３は、本実施の形態に係る半導体モジュールの端面図である。
　図１、図２および図３に示されるように、本実施の形態に係る半導体モジュールは、主として、基板１と、接合材２と、半導体素子３と、接合材５と、導体６と、接合材７と、ワイヤ８とを有している。
　基板１の表面には導体パターン１ａ、１ｂ、１ｃが設けられている。接合材２は基板１の導体パターン１ｂと半導体素子３とを接合するためのものである。接合材２は導電性を有している。半導体素子３は基板１上に接合されている。半導体素子３は表面電極４を有している。表面電極４は半導体素子３の表面に設けられている。半導体素子３の表面電極４上に接合材５を介して導体６が接合されている。なお、半導体素子３の表面電極４と導体６とは、接合材５のみで接合されていなくてもよく、互いの間に別の導体および接合材が挟まれていてもよい。
　接合材７は導体６とワイヤ８とを接合している。ワイヤ８は、半導体素子３の表面電極４をまたいで両端部８ａの各々が基板１にボンディングされている。ワイヤ８は、表面電極４と電気的に接続されている。具体的には、ワイヤ８は、導体パターン１ｂと導体パターン１ｃとに両端部８ａをボンディングされ、半導体素子３をまたぐように橋架けされている。ワイヤ８は表面電極４の上側において表面電極４と電気的に接続されている。
　基板１は、導体パターン１ａ、１ｂ、１ｃ、１ｅと、絶縁層１ｄとを有している。導体パターン１ａ、１ｂ、１ｃ、１ｅは絶縁層１ｄ上に設けられている。具体的には、基板１は、表面に設けられた導体パターン１ａ、１ｂ、１ｃに加えて、絶縁層１ｄと、半導体素子３が搭載された表面と反対の側の裏面に設けられた導体パターン１ｅとを有している。つまり、絶縁層１ｄの表面に導体パターン１ａ、１ｂ、１ｃが配置されており、絶縁層１ｄの裏面に導体パターン１ｅが配置されている。
　半導体素子３は、導体パターン（第１導体部）１ａと、導体パターン（第２導体部）１ｃとの間に配置されている。ワイヤ８の両端部８ａのうち第１の端部８ａ１は導体パターン（第１導体部）１ａにボンディングされており、ワイヤ８の両端部８ａのうち第２の端部８ａ２は第２導体パターン（第２導体部）１ｃにボンディングされている。
　絶縁層１ｄには、例えば、酸化アルミニウム（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）等が用いられる。導体パターン１ａ、１ｂ、１ｃ、１ｅは、絶縁層１ｄ上に形成されている。導体パターン１ａ、１ｂ、１ｃ、１ｅには、例えば銅（Ｃｕ）が用いられる。
　本実施の形態に係る半導体モジュールはベース板１０を有している。ベース板１０は、熱伝導性の高い材料により構成されている。ベース板１０には、例えば、銅（Ｃｕ）が用いられる。ベース板１０の上面は、基板１の裏面に形成された導体パターン１ｅに接合されている。導体パターン１ｅとベース板１０とは、接合材９により接合されている。接合材９としては、例えば、はんだ、焼結性銀粒子が用いられる。
　半導体素子３は、例えば、下面（裏面）から上面（表面）に向かって電流が流れる縦型構造を有するパワー半導体素子である。半導体素子３は、例えば、ＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）、縦型ＭＯＳＦＥＴ（Metal　Oxide　Semiconductor　Field　Effect　Transistor）のようなスイッチング素子、又はショットキーバリアダイオードのような整流素子である。
　半導体素子３は、例えば、シリコン（Ｓｉ）の単結晶を用いて形成されている。半導体素子３を構成する半導体材料は、シリコン（Ｓｉ）の単結晶に限られるものではなく、例えば、炭化珪素（ＳｉＣ）、窒化珪素（ＧａＮ）等のワイドバンドギャップを有する半導体材料であってもよい。
　半導体素子３の下面は、基板１の表面の導体パターン１ｂに電気的に接合されている。半導体素子３の下面と導体パターン１ｂとは、導電性を有する接合材２を介して接合されている。接合材２としては、例えば、はんだ、焼結性銀粒子等が用いられる。
　半導体素子３は、表面電極４を有している。表面電極４は、半導体素子３の表面（上面）に形成されている。表面電極４には、例えば、シリコン（Ｓｉ）を含有するアルミニウム（Ａｌ）合金等が用いられる。表面電極４は、被覆層を有していてもよい。被覆層には、例えば、ニッケル（Ｎｉ）、金（Ａｕ）又はこれらを積層した構造が用いられる。導体６は表面電極４上に接合されている。接合材５は導体６上に配置されている。表面電極４と導体６とは、導電性の接合材５によって接合されている。接合材５としては、例えば、はんだ、焼結性銀粒子等が用いられる。
　導体６としては、例えば、銅（Ｃｕ）が用いられる。導体６は、接合材５とは異なる材料であってもよい。ワイヤ８は、導体６と導電性を有する接合材７によって接合されている。接合材７としては、例えば、はんだ、焼結性銀粒子等が用いられる。接合材７は、例えば、銀を含む焼結体（Ａｇ焼結体）が好ましい。
　図３に示されるように、導体６は、ワイヤ８と接合材７とが入り込む溝６ａを有していてもよい。導体６の上面に溝６ａが設けられている。ワイヤ８および接合材７は溝６ａに入り込むように配置されている。導体６が溝６ａを有することで、ワイヤ８を溝６ａに入れ込んで、接合材７によって固定することが容易となる。
　ワイヤ８は、一本でも良いし、複数本でもよい。ワイヤ８は、導体パターン１ａ、１ｃと接合されている。つまり、ワイヤ８の一方端が導体パターン１ａに接合されており、ワイヤ８の他方端が導体パターン１ｃに接合されている。導体パターン１ａと導体パターン１ｃは別々のパターンであってもよく、つながった一つのパターンであってもよい。ワイヤ８が複数本の場合に、ワイヤ８の両端はそれぞれ導体パターン１ａと導体パターン１ｃにすべてボンディングされている必要はなく、一部のワイヤ８が導体パターン１ａと導体パターン１ｃ以外の別の導体パターンとに接続されていてもよい。ワイヤ８には、例えば、金（Ａｕ）、アルミニウム（Ａｌ）、銅（Ｃｕ）等が用いられる。
　次に、図４～図６を参照して、本発明の実施の形態１に係る半導体モジュールの製造方法について説明する。
　図４に示されるように、本実施の形態に係る半導体モジュールの製造方法では、基板１の表面に設けられた導体パターン１ｂ上に、半導体素子３が接合材２によって接合される。導体６は半導体素子３の表面電極４上に接合材５によって接合される。
　続いて、図５に示されるように、基板１の表面の導体パターン１ａ、１ｃにワイヤ８の両端が超音波接合によって接合される。ワイヤ８は半導体素子３の表面電極４をまたいでワイヤ８の両端部８ａの各々を基板１の導体パターン１ａ、１ｃにボンディングされる。基板１の導体パターン１ａ、１ｃにボンディングされたワイヤ８が半導体素子３の表面電極４と電気的に接続される。
　ワイヤ８の両端と導体パターン１ａ、１ｃとの接合後に、ワイヤ８を導体６に近づくように押して変形させてもよい。そのとき、図６に示されるように、導体６がワイヤ８を入れるための溝６ａを有している場合には、導体６の溝６ａにワイヤ８が入り込むように、ワイヤ８を溝６ａに押し入れてもよい。溝６ａ内にワイヤ８が押し入れられた後に溝６ａ内で導体６とワイヤ８とが接合材７で接合される。これにより、図１～図３に示された半導体モジュールが製造される。
　次に、本実施の形態に係る半導体モジュールの効果について説明する。
　図１、図２および図３に示されように、ワイヤ８を導電性を有する接合材７によって導体６と接合することで、例えば、半導体素子３に対して縦方向に下面から表面電極４に流れた電流が導電性を有する接合材５、導体６、導電性を有する接合材７、ワイヤ８、導体パターン１ａ、１ｃの順に流れることができる。
　このとき、仮に、上記の通常の半導体モジュールのように、ワイヤ８が半導体素子３の表面電極４に超音波接合によってボンディングされていると、表面電極４とのワイヤ８の接合部に切欠き形状が形成される。そのため、半導体モジュールの運用中の発熱、冷却の繰り返しによる温度変化時に、ワイヤ８の接合部のおいて切欠き形状の端に応力が集中して、切欠き形状の端から破壊が発生する。言いかえれば、半導体モジュールにおいて、最も温度の変化が大きくなるのは半導体素子周辺である。そして、上記の通常の導体モジュールでは、最も温度変化の大きい半導体素子周辺に、応力が集中する超音波接合によるワイヤボンディング部を有している。このため、信頼性の点で問題がある。また、従来のワイヤボンディング装置を使用して容易に作成できる。
　一方、本実施の形態に係る半導体モジュールでは、ワイヤ８は半導体素子３の表面電極４をまたいで両端部８ａの各々が基板１にボンディングされており、表面電極４と電気的に接続されている。このため、表面電極４とのワイヤ８の接合部において切欠き形状が形成されないので、ワイヤ８の接合部の端に応力が集中することを抑制することができる。したがって、半導体素子３の表面電極４とのワイヤ８の接合部を長寿命化することができる。また、ワイヤ８としてボンディングワイヤが用いられるため、ワイヤ８が表面電極４に半田によって接合されている場合と比べて、ワイヤ８の本数を多くすることができる。したがって、ワイヤ一本あたりの電流密度を小さくすることができる。さらに、ワイヤ８は表面電極４をまたいで基板１にボンディングされているため、ワイヤ８の両端に向かって電流を流すことができる。これにより、ワイヤ一本あたりの電流密度を小さくすることができる。
　また、本実施の形態に係る半導体モジュールでは、半導体素子３は、導体パターン（第１導体部）１ａと、導体パターン１ｃ（第２導体部）との間に配置されている。このため、ワイヤ８は、半導体素子３の表面電極４をまたいで表面電極４と電気的に接続することができる。ワイヤ８の両端部８ａのうち第１の端部８ａ１は導体パターン１ａにボンディングされており、ワイヤ８の両端部８ａのうち第１の端部８ａ１は導体パターン１ｃにボンディングされている。このため、ワイヤ８の両端部８ａの各々に向かって電流を流すことができる。
　また、本実施の形態に係る半導体モジュールでは、ワイヤ８は、表面電極４上に接合された導体６と接合材７によって接合されている。このため、半導体素子３と電気的に繋がった導体６とワイヤ８とを、超音波接合ではなく、接合材７によって接合することができる。したがって、導体６とワイヤ８との接合部は切欠き形状ではないため、導体６とのワイヤ８の接合部を長寿命化することができる。
　また、ワイヤ８が半導体素子３の表面電極４にボンディングされる場合、および、ワイヤ８がはんだ等の接合材によって半導体素子３の表面電極４に接合される場合には、一般的に、ワイヤ８の線膨張係数は、半導体素子３の線膨張係数と比べて数倍以上に大きい。そのため、半導体モジュールの運用中の発熱、冷却の繰り返しによる温度変化時に、半導体素子３の線膨張係数とワイヤ８の線膨張係数との差異による熱応力が発生する。この熱応力がワイヤ８が表面電極４にボンディングされた接合面付近および半導体素子３とワイヤ８とを接合した接合材に生じることにより、当該接合面および当該接合材に破壊が発生しやすい。
　一方、本実施の形態では、半導体素子３とワイヤ８との間に導体６を介しているため、導体６とワイヤ８との線膨張係数差による熱応力、および、半導体素子３と導体６との線膨張係数差による熱応力を考えればよい。導体６とワイヤ８とは一般的に線膨張係数差が小さいため、発生する熱応力は小さい。半導体素子３と導体６とは線膨張係数差が大きいが、半導体素子３と導体６との接合部の端が切欠き形状にならないため、発生する熱応力を低く抑えることができる。さらに、半導体素子３と導体６の接合面積はワイヤボンディングの面積と比較して数十倍以上に大きいため、接合部を長寿命化することができる。
　また、本実施の形態に係る半導体モジュールでは、ワイヤ８および接合材７は溝６ａに入り込むように配置されているため、ワイヤ８を溝６ａに入れ込んで接合材７によって固定することが容易となる。
　また、本実施の形態に係る半導体モジュールでは、接合材７は、銀を含む焼結体である。これにより、高耐熱、高信頼性の接合材を使うことで、ワイヤ８の接合部を長寿命化することができる。したがって、半導体モジュールの信頼性が大きく向上することが可能となる。
　また、本実施の形態に係る半導体モジュールでは、ワイヤ８の材質は銅である。これにより、半導体モジュールのコストを低減することができる。
　本実施の形態に係る半導体モジュールの製造方法は次の工程を備えている。基板１に接合された半導体素子３の表面電極４をまたいでワイヤ８の両端部８ａの各々が基板１にボンディングされる。基板１にボンディングされたワイヤ８が半導体素子３の表面電極４と電気的に接続される。したがって、半導体素子３の表面電極４とワイヤ８との接合部を長寿命化し、かつワイヤ一本あたりの電流密度を小さくすることができる半導体モジュールを製造することが可能となる。
　また、本実施の形態に係る半導体モジュールの製造方法は次の構成をさらに備えている。上面に溝６ａが設けられた導体６が表面電極４上に接合される。溝６ａ内にワイヤ８が押し入れられた後に溝６ａ内で導体６とワイヤ８とが導電性を有する接合材７で接合される。ワイヤ８を溝６ａに入れ込んで接合材７によって固定することが容易となる。また、チップ上の配線構造として、ワイヤ以外の銅板などを使用せず、従来のワイヤとワイヤボンディング装置を用いて配線できるため、製造が容易であるという利点がある。
　実施の形態２．
　図７～図９を参照して、本発明の実施の形態２に係る半導体モジュールの構造について説明する。なお、ここでは、実施の形態１と異なる点について主に説明する。図７は、本実施の形態に係る半導体モジュールの正面図である。図５は、本実施の形態に係る半導体モジュールの上面図である。図６は、本実施の形態に係る半導体モジュールの端面図である。
　図７、図８および図９に示すように、本実施の形態に係る半導体モジュールは、実施の形態１に係る半導体モジュールと同様に、主として、基板１と、接合材２と、半導体素子３と、接合材５と、導体６と、接合材７と、ワイヤ８とを有している。
　図８に示されるように、ワイヤ８は２列に並んで導体パターン１ａ、１ｃにボンディングされていてもよい。また、図９に示されるように、ワイヤ８が導体６の溝６ａにおいて接合されるときに、２段以上に並んで接合されていてもよい。
　次に、本実施の形態に係る半導体モジュールの製造方法について説明する。
　本実施の形態に係る半導体モジュールの製造方法は、実施の形態１に係る半導体モジュールの製造方法と同様であり、図８に示されるように、ワイヤ８がボンディングされる際に２列に並んで導体パターン１ａ、１ｃにボンディングされる点だけが異なる。なお、ワイヤ８は３列以上に並んでボンディングされていてもよく、ワイヤ８の両端部８ａの各々は導体パターン１ａ、１ｃの任意の位置にボンディングされていてもよい。
　次に、本実施の形態に係る半導体モジュールの効果について説明する。ここでは、実施の形態１に係る半導体モジュールの効果に記載していなかった効果について説明する。
　本実施の形態に係る半導体モジュールでは、導体６とのワイヤ８の接合部が２段以上になることで、一つの半導体素子３と電気的に接続されたワイヤ８の本数を、半導体素子３の表面積に依存せず、任意に増加することができる。半導体モジュールでは、半導体素子３だけでなく、ワイヤ８における損失による発熱も半導体モジュールの寿命を短くする要因である。本実施の形態では、ワイヤ一本当たりの電流密度を減らすことができるため、半導体モジュールを長寿命化することができる。
　次に、図１０～図１２を参照して、本実施の形態の変形例に係る半導体モジュールについて説明する。なお、本実施の形態の変形例は、特に説明しない限り、上記の本実施の形態と同様の構成を備えているため、同一の要素については同一の符号を付し、その説明を繰り返さない。
　図１０に示されるように、本実施の形態の変形例１に係る半導体モジュールにおいては、１段目のワイヤ８同士の間に２段目のワイヤ８が配置され、２段目のワイヤ同士の間に１段目のワイヤが配置されている。つまり、１段目のワイヤ８と２段目のワイヤ８とは互いに１段目のワイヤ８同士の間と２段目のワイヤ８同士の間を詰めるように並んでいる。
　本実施の形態の変形例１に係る半導体モジュールによれば、１段目のワイヤ８と２段目のワイヤ８との積層方向の距離を短くすることができる。したがって、半導体モジュールを小型化することができる。
　図１１および図１２に示されるように、本実施の形態の変形例２における半導体モジュールにおいては、導体６の上にさらに導電性の接合材１１を介して導体１２が接合されている。導体１２は溝１２ａを有している。ワイヤ１４が溝１２ａ内において導電性の接合材１３によって接合されている。ワイヤ１４には、例えば、金（Ａｕ）、アルミニウム（Ａｌ）、銅（Ｃｕ）等が用いられる。導体１２としては、例えば、銅（Ｃｕ）が用いられる。接合材１３としては、例えば、はんだ、焼結性銀粒子等が用いられる。ワイヤ８とワイヤ１４とは互いに交差する方向に半導体素子３の表面電極４をまたぐように配置されている。
　半導体素子３上に導体が２つ以上、接合材によって接合される場合には、導体６とワイヤ８とが先に接合材７によって接合されてから、ワイヤ１４と導体１２とが接合材１３によって接合されてもよいし、接合材７と接合材１３を同時に硬化させてもよい。
　本実施の形態の変形例２に係る半導体モジュールによれば、ワイヤ８とワイヤ１４とが半導体素子３の表面電極４をまたぐ方向を互いに異ならせることができる。これにより、ワイヤの配置の自由度を向上させることができる。
　実施の形態３．
　図１３～１５を参照して、本発明の実施の形態３に係る半導体モジュールの構造について説明する。なお、ここでは、実施の形態１と異なる点について主に説明する。図１３は、本実施の形態に係る半導体モジュールの正面図である。図１４は、本実施の形態に係る半導体モジュールの上面図である。図１５は、本実施の形態に係る半導体モジュールの図１３におけるＸＶ部分の図１４におけるＸＶ－ＸＶ線に沿う断面を拡大して示す断面図である。
　図１３、図１４および図１５に示すように、本実施の形態に係る半導体モジュールは、実施の形態１に係る半導体モジュールと同様に、主として、基板１と、接合材２と、半導体素子３と、接合材５と、導体６と、接合材７と、ワイヤ８とを有している。
　図１３および図１４に示されるように、導体６および半導体素子３を上から見たときに、導体６の面積は半導体素子３の面積よりも小さい。すなわち、上面視において、導体６は半導体素子３よりも面積が小さい。つまり、導体６の上面の面積は、半導体素子３の上面の面積よりも小さい。具体的には、導体６の縦幅は半導体素子３の縦幅よりも小さく、導体６の横幅は半導体素子３の横幅よりも小さい。
　図１５に示されるように、導体６が溝６ａを有する場合に、断面視において、溝６ａは、ワイヤ８が表面電極４をまたぐ方向に沿って、溝６ａの中央部（内部）の深さが深く、端部の深さが浅い形状であってもよい。つまり、導体６は、ワイヤ８が表面電極４をまたぐ方向に沿って、溝６ａの中央部の深さよりも溝６ａの端部の深さが浅くなる形状を有している。溝６ａの中央部の深さよりも溝６ａの両端部の各々の深さが浅くなっていてもよい。
　なお、本実施の形態に係る半導体モジュールの製造工程は、実施の形態１に係る半導体モジュールの製造工程と同様である。
　次に、本実施の形態に係る半導体モジュールの効果について説明する。ここでは、実施の形態１および実施の形態２に係る半導体モジュールの効果に記載していなかった効果について説明する。
　本実施の形態に係る半導体モジュールによれば、導体６および半導体素子３を上から見たときに、導体６の面積は半導体素子３の面積よりも小さいため、高電圧がかかりかつ絶縁を保つことが必要となる導体パターン１ｂとワイヤ８との間の絶縁距離を稼ぐことができる。
　また、本実施の形態に係る半導体モジュールによれば、ワイヤ８が表面電極４をまたぐ方向に沿って、溝６ａの中央部の深さよりも溝６ａの端部の深さが浅くなるため、高電圧がかかりかつ絶縁を保つことが必要となる導体パターン１ｂとワイヤ８との間の絶縁距離を稼ぐことができる。
　実施の形態４．
　本実施の形態は、上述した実施の形態１～３に係る半導体モジュールを電力変換装置に適用したものである。本発明は特定の電力変換装置に限定されるものではないが、以下、実施の形態４として、三相のインバータに本発明を適用した場合について説明する。
　図１６は、本実施の形態にかかる電力変換装置を適用した電力変換システムの構成を示すブロック図である。
　図１６に示す電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成することとしてもよい。また、電源１００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。
　電力変換装置２００は、電源１００と負荷３００の間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図１６に示すように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１を制御する制御信号を主変換回路２０１に出力する制御回路２０３とを備えている。
　負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。
　以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子と還流ダイオードを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１００から供給される直流電力を交流電力に変換し、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードから構成することができる。主変換回路２０１の各スイッチング素子や各還流ダイオードは、上述した実施の形態１～３のいずれかに相当する半導体モジュール２０２によって構成する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。
　また、主変換回路２０１は、各スイッチング素子を駆動する駆動回路（図示なし）を備えているが、駆動回路は半導体モジュール２０２に内蔵されていてもよいし、半導体モジュール２０２とは別に駆動回路を備える構成であってもよい。駆動回路は、主変換回路２０１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２０１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。
　制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２０１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、主変換回路２０１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。
　本実施の形態に係る電力変換装置では、主変換回路２０１のスイッチング素子と還流ダイオードとして実施の形態１～３に係る半導体モジュールを適用するため、電力変換装置を長寿命化し、かつ半導体モジュールのワイヤ一本あたりの電流密度を小さくすることを実現することができる。
　本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、本発明は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本発明を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに本発明を適用することも可能である。
　また、本発明を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触器給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
　１　基板、１ａ，１ｂ，１ｃ，１ｅ　導体パターン、２　接合材、３　半導体素子、４　表面電極、５　接合材、６　導体、７　接合材、８　ワイヤ、８ａ　両端部、９　接合材、１０　ベース板、１１　接合材、１２　導体、１３　接合材、１４　ワイヤ、　１００　電源、２００　電力変換装置、２０１　主変換回路、２０２　半導体モジュール、２０３　制御回路、３００　負荷。

Claims (11)

  1. 　基板と、
    　前記基板上に接合され、かつ表面電極を有する半導体素子と、
    　前記半導体素子の前記表面電極をまたいで両端部の各々が前記基板にボンディングされたワイヤとを備え、
    　前記ワイヤは、前記表面電極と電気的に接続されている、半導体モジュール。
  2. 　前記基板は、絶縁層と、前記絶縁層上に設けられた導体パターンとを含み、
    　前記導体パターンは、第１導体部と、第２導体部とを含み、
    　前記半導体素子は、前記第１導体部と前記第２導体部との間に配置されており、
    　前記ワイヤの前記両端部のうち第１の端部は前記第１導体部にボンディングされており、前記ワイヤの前記両端部のうち第２の端部は前記第２導体部にボンディングされている、請求項１に記載の半導体モジュール。
  3. 　前記表面電極上に接合された導体と、
    　前記導体上に配置され、かつ導電性を有する接合材とをさらに備え、
    　前記ワイヤは、前記導体と前記接合材によって接合されている、請求項１または２に記載の半導体モジュール。
  4. 　前記導体は上面に設けられた溝を含み、
    　前記ワイヤおよび前記接合材は前記溝に入り込むように配置されている、請求項３に記載の半導体モジュール。
  5. 　前記溝は、前記ワイヤが前記表面電極をまたぐ方向に沿って、前記溝の中央部の深さよりも前記溝の端部の深さが浅くなる形状を有している、請求項４に記載の半導体モジュール。
  6. 　前記接合材は、銀を含む焼結体である、請求項３～５のいずれか１項に記載の半導体モジュール。
  7. 　前記導体および前記半導体素子を上から見たときに、前記導体の面積は前記半導体素子の面積よりも小さい、請求項３～６のいずれか１項に記載の半導体モジュール。
  8. 　前記ワイヤの材質は銅である、請求項１～７のいずれか１項に記載の半導体モジュール。
  9. 　基板に接合された半導体素子の表面電極をまたいでワイヤの両端部の各々を前記基板にボンディングする工程と、
    　前記基板にボンディングされた前記ワイヤを前記半導体素子の前記表面電極と電気的に接続する工程とを備えた、半導体モジュールの製造方法。
  10. 　上面に溝が設けられた導体を前記表面電極上に接合する工程と、
    　前記溝内に前記ワイヤが押し入れられた後に前記溝内で前記導体と前記ワイヤとを導電性を有する接合材で接合する工程とをさらに備えた、請求項９に記載の半導体モジュールの製造方法。
  11. 　請求項１～８のいずれか１項に記載の半導体モジュールを有し、入力される電力を変換して出力する主変換回路と、
    　前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路とを備えた、
    電力変換装置。
PCT/JP2017/043423 2017-04-12 2017-12-04 半導体モジュール、半導体モジュールの製造方法および電力変換装置 WO2018189948A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018527816A JP6410998B1 (ja) 2017-04-12 2017-12-04 半導体モジュール、半導体モジュールの製造方法および電力変換装置
CN201780089024.0A CN110462805A (zh) 2017-04-12 2017-12-04 半导体模块、半导体模块的制造方法以及电力变换装置
US16/486,924 US10930616B2 (en) 2017-04-12 2017-12-04 Semiconductor module, method for manufacturing semiconductor module, and power conversion apparatus
DE112017007430.4T DE112017007430T5 (de) 2017-04-12 2017-12-04 Halbleitermodul, Verfahren zur Herstellung eines Halbleitermoduls und Leistungswandlergerät

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017078948 2017-04-12
JP2017-078948 2017-04-12

Publications (1)

Publication Number Publication Date
WO2018189948A1 true WO2018189948A1 (ja) 2018-10-18

Family

ID=63793171

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/043423 WO2018189948A1 (ja) 2017-04-12 2017-12-04 半導体モジュール、半導体モジュールの製造方法および電力変換装置

Country Status (5)

Country Link
US (1) US10930616B2 (ja)
JP (1) JP6410998B1 (ja)
CN (1) CN110462805A (ja)
DE (1) DE112017007430T5 (ja)
WO (1) WO2018189948A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7195208B2 (ja) 2019-04-12 2022-12-23 三菱電機株式会社 半導体装置および半導体装置の製造方法
DE112020007196T5 (de) * 2020-05-14 2023-04-20 Mitsubishi Electric Corporation Halbleitereinheit und verfahren zur herstellung einer halbleitereinheit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022821B2 (ja) * 1977-07-22 1985-06-04 株式会社日立製作所 半導体装置
JPH03245769A (ja) * 1990-02-23 1991-11-01 Fuji Electric Co Ltd 高集積型パワー半導体モジュール
JP2009206140A (ja) * 2008-02-26 2009-09-10 Sumitomo Electric Ind Ltd パワーモジュール
JP2015142059A (ja) * 2014-01-30 2015-08-03 株式会社日立製作所 パワー半導体モジュール

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053864A (en) * 1976-12-20 1977-10-11 Sprague Electric Company Thermistor with leads and method of making
JP3455685B2 (ja) * 1998-11-05 2003-10-14 新光電気工業株式会社 半導体装置の製造方法
JP4544724B2 (ja) * 2000-10-30 2010-09-15 京セラ株式会社 半導体装置
JP3809379B2 (ja) 2002-01-24 2006-08-16 三洋電機株式会社 半導体装置およびその製造方法
US7531893B2 (en) * 2006-07-19 2009-05-12 Texas Instruments Incorporated Power semiconductor devices having integrated inductor
JP5054359B2 (ja) * 2006-12-01 2012-10-24 パナソニック株式会社 半導体集積回路及びその製造方法
DE102008003971A1 (de) * 2008-01-11 2009-07-16 Ledon Lighting Jennersdorf Gmbh Leuchtdiodenanordnung mit Schutzrahmen
JP5125530B2 (ja) 2008-01-16 2013-01-23 日産自動車株式会社 電力変換装置
WO2010001597A1 (ja) * 2008-06-30 2010-01-07 三洋電機株式会社 素子搭載用基板、半導体モジュール、半導体装置、素子搭載用基板の製造方法および半導体装置の製造方法、ならびに携帯機器
EP2159834A1 (en) * 2009-09-01 2010-03-03 ABB Technology AG Conductive bond wire coating
JP5185956B2 (ja) 2010-01-06 2013-04-17 三菱電機株式会社 電力用半導体装置
TWI502723B (zh) * 2010-06-18 2015-10-01 Chipmos Technologies Inc 多晶粒堆疊封裝結構
JP5572454B2 (ja) * 2010-06-29 2014-08-13 日立アプライアンス株式会社 Ｌｅｄ点灯装置
JP5975911B2 (ja) * 2013-03-15 2016-08-23 ルネサスエレクトロニクス株式会社 半導体装置
US20150249940A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Method and apparatus for performing call recovery after call drop
CN105762130B (zh) * 2014-12-15 2019-04-05 财团法人工业技术研究院 功率模块
JP2016163024A (ja) * 2015-03-05 2016-09-05 三菱電機株式会社 パワーモジュール

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022821B2 (ja) * 1977-07-22 1985-06-04 株式会社日立製作所 半導体装置
JPH03245769A (ja) * 1990-02-23 1991-11-01 Fuji Electric Co Ltd 高集積型パワー半導体モジュール
JP2009206140A (ja) * 2008-02-26 2009-09-10 Sumitomo Electric Ind Ltd パワーモジュール
JP2015142059A (ja) * 2014-01-30 2015-08-03 株式会社日立製作所 パワー半導体モジュール

Also Published As

Publication number Publication date
JP6410998B1 (ja) 2018-10-24
US10930616B2 (en) 2021-02-23
JPWO2018189948A1 (ja) 2019-04-18
CN110462805A (zh) 2019-11-15
US20200035639A1 (en) 2020-01-30
DE112017007430T5 (de) 2020-01-16

Similar Documents

Publication Publication Date Title
US11271352B2 (en) Power semiconductor device and manufacturing method thereof, and power conversion device
US10229869B2 (en) Semiconductor device and power conversion device including a bent control side frame
CN112701093A (zh) 半导体模块及电力转换装置
JP6965706B2 (ja) 半導体モジュール、その製造方法及び電力変換装置
JP6743728B2 (ja) 半導体パワーモジュール及び電力変換装置
JP6410998B1 (ja) 半導体モジュール、半導体モジュールの製造方法および電力変換装置
JP6826665B2 (ja) 半導体装置、半導体装置の製造方法及び電力変換装置
CN111052325B (zh) 半导体模块以及电力转换装置
JP7126609B2 (ja) パワー半導体モジュール及び電力変換装置
JP2020043154A (ja) 半導体装置及びその製造方法、並びに、電力変換装置
JP7438466B1 (ja) 半導体装置及びその製造方法並びに電力変換装置
CN111788694B (zh) 半导体元件、半导体装置、电力变换装置以及半导体元件的制造方法
US11257768B2 (en) Semiconductor device and power conversion device
WO2021100199A1 (ja) 半導体装置およびその製造方法ならびに電力変換装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2018527816

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17905124

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17905124

Country of ref document: EP

Kind code of ref document: A1