CN110462805A - 半导体模块、半导体模块的制造方法以及电力变换装置 - Google Patents

半导体模块、半导体模块的制造方法以及电力变换装置 Download PDF

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Publication number
CN110462805A
CN110462805A CN201780089024.0A CN201780089024A CN110462805A CN 110462805 A CN110462805 A CN 110462805A CN 201780089024 A CN201780089024 A CN 201780089024A CN 110462805 A CN110462805 A CN 110462805A
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semiconductor module
conductor
surface electrode
semiconductor element
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CN201780089024.0A
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伊藤悠策
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Mitsubishi Corp
Mitsubishi Electric Corp
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Mitsubishi Corp
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Abstract

半导体模块具备基板(1)、半导体元件(3)以及线(8)。半导体元件(3)被接合到基板(1)上，并且具有表面电极(4)。关于线(8)，跨越半导体元件(3)的表面电极(4)而两端部(8a)的各个端部被键合到基板(1)。线(8)与表面电极(4)电连接。

Description

半导体模块、半导体模块的制造方法以及电力变换装置
技术领域
本发明涉及半导体模块、半导体模块的制造方法以及电力变换装置，特别涉及包括功率半导体元件的功率半导体模块、其制造方法以及电力变换装置。
背景技术
半导体模块通常具备：基板，具有导体图案；半导体元件，具有与导体图案接合的背面和设置有表面电极的表面；以及键合线，与表面电极接合。
另外，在半导体模块中，有线未被键合而半导体元件和线被电连接的例子。这样的半导体模块的一个例子记载于日本专利第3809379号公报(专利文献1)。在该公报记载的半导体模块中，具有开口部的保护膜覆盖配置于半导体元件的表面的表面电极上。在保护膜的开口部利用焊料接合线和表面电极。
现有技术文献
专利文献
专利文献1：日本专利第3809379号公报
发明内容
在上述通常的半导体模块中，对表面电极键合线，所以在与表面电极的线的接合部中形成切口形状。因此，在半导体模块的运用中的发热、冷却的反复所致的温度变化时，在线的接合部中应力集中到切口形状的端。由此，从切口形状的端发生破坏。因此，难以使对半导体元件的表面电极键合的线的接合部长寿命化。
另外，在上述公报记载的半导体模块中，未进行利用超声波接合的线键合，所以在与表面电极的线的接合部中不形成切口形状。然而，线通过焊料被接合到表面电极，所以相比于线键合，线的根数受到限制。因此，难以减小每一根线的电流密度。
本发明是鉴于上述课题而完成的，其目的在于提供能够使与半导体元件的表面电极的线的接合部长寿命化并且减小每一根线的电流密度的半导体模块、半导体模块的制造方法以及电力变换装置。
本发明的半导体模块具备基板、半导体元件以及线。半导体元件被接合到基板上，并且具有表面电极。线跨越半导体元件的表面电极而两端部的各个端部被键合到基板。线与表面电极电连接。
根据本发明的半导体模块，线跨越半导体元件的表面电极而两端部的各个端部被键合到基板，并与表面电极电连接。因此，在与表面电极的线的接合部中未形成切口形状，所以能够抑制应力集中到线的接合部的端。另外，使用键合线，所以相比于通过焊料接合线的情况，能够增加线的根数。因此，能够使半导体元件的表面电极和线的接合部长寿命化并且减小每一根线的电流密度。
附图说明
图1是概略地示出本发明的实施方式1所涉及的半导体模块的结构的正面图。
图2是概略地示出本发明的实施方式1所涉及的半导体模块的结构的俯视图。
图3是沿着图1以及图2的III-III线的端面图。
图4是概略地示出本发明的实施方式2所涉及的半导体模块的结构的正面图。
图5是概略地示出本发明的实施方式2所涉及的半导体模块的结构的俯视图。
图6是沿着图5的VI-VI线的端面图。
图7是概略地示出本发明的实施方式2的变形例1所涉及的半导体模块的结构的正面图。
图8是概略地示出本发明的实施方式2的变形例1所涉及的半导体模块的结构的俯视图。
图9是沿着图7的IX-IX射线的端面图。
图10是概略地示出本发明的实施方式2的变形例2所涉及的半导体模块的结构的端面图。
图11是概略地示出本发明的实施方式2的变形例3所涉及的半导体模块的结构的俯视图。
图12是沿着图11的XII-XII线的端面图。
图13是概略地示出本发明的实施方式3所涉及的半导体模块的结构的正面图。
图14是概略地示出本发明的实施方式3所涉及的半导体模块的结构的俯视图。
图15是图13的XV部分中的沿着图14的XV-XV线的放大剖面图。
图16是示出应用本发明的实施方式4所涉及的电力变换装置的电力变换系统的结构的框图。
(符号说明)
1：基板；1a、1b、1c、1e：导体图案；2：接合件；3：半导体元件；4：表面电极；5：接合件；6：导体；7：接合件；8：线；8a：两端部；9：接合件；10：基体板；11：接合件；12：导体；13：接合件；14：线；：100：电源；200：电力变换装置；201：主变换电路；202：半导体模块；203：控制电路；300：负载。
具体实施方式
以下，参照附图，说明本发明的实施方式。此外，在各图中对相同或者相当部分附加相同符号。另外，也可以任意地组合以下记载的实施方式的至少一部分。
实施方式1.
参照图1～图3，说明本发明的实施方式1所涉及的半导体模块的构造。图1是本实施方式所涉及的半导体模块的正面图。图2是本实施方式所涉及的半导体模块的俯视图。图3是本实施方式所涉及的半导体模块的端面图。
如图1、图2以及图3所示，本实施方式所涉及的半导体模块主要具有基板1、接合件2、半导体元件3、接合件5、导体6、接合件7以及线8。
在基板1的表面设置有导体图案1a、1b、1c。接合件2用于接合基板1的导体图案1b和半导体元件3。接合件2具有导电性。半导体元件3被接合到基板1上。半导体元件3具有表面电极4。表面电极4设置于半导体元件3的表面。在半导体元件3的表面电极4上经由接合件5接合有导体6。此外，半导体元件3的表面电极4和导体6也可以并非仅通过接合件5接合，也可以在相互之间夹着其他导体以及接合件。
接合件7接合导体6和线8。线8跨越半导体元件3的表面电极4而两端部8a的各个端部被键合到基板1。线8与表面电极4电连接。具体而言，关于线8，对导体图案1b和导体图案1c键合两端部8a，以跨越半导体元件3的方式桥接。线8在表面电极4的上侧与表面电极4电连接。
基板1具有导体图案1a、1b、1c、1e和绝缘层1d。导体图案1a、1b、1c、1e设置于绝缘层1d上。具体而言，基板1除了设置于表面的导体图案1a、1b、1c以外，还具有绝缘层1d和设置于与搭载有半导体元件3的表面相反的一侧的背面的导体图案1e。即，在绝缘层1d的表面配置有导体图案1a、1b、1c，在绝缘层1d的背面配置有导体图案1e。
半导体元件3配置于导体图案(第1导体部)1a与导体图案(第2导体部)1c之间。线8的两端部8a中的第1端部8a1被键合到导体图案(第1导体部)1a，线8的两端部8a中的第2端部8a2被键合到第2导体图案(第2导体部)1c。
在绝缘层1d中，例如使用氧化铝(Al2O3)、氮化铝(AlN)等。导体图案1a、1b、1c、1e形成于绝缘层1d上。在导体图案1a、1b、1c、1e中，例如使用铜(Cu)。
本实施方式所涉及的半导体模块具有基体板10。基体板10由热传导性高的材料构成。在基体板10中，例如使用铜(Cu)。基体板10的上表面被接合到形成于基板1的背面的导体图案1e。导体图案1e和基体板10通过接合件9接合。作为接合件9，例如使用焊料、烧结性银粒子。
半导体元件3例如是电流从下表面(背面)流向上表面(表面)的具有纵型构造的功率半导体元件。半导体元件3例如是如IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极晶体管)、纵型MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)那样的开关元件或者如肖特基势垒二极管那样的整流元件。
半导体元件3例如使用硅(Si)的单结晶来形成。构成半导体元件3的半导体材料不限于硅(Si)的单结晶，例如也可以是碳化硅(SiC)、氮化硅(GaN)等具有宽能带隙的半导体材料。
半导体元件3的下表面被电接合到基板1的表面的导体图案1b。半导体元件3的下表面和导体图案1b经由具有导电性的接合件2接合。作为接合件2，例如使用焊料、烧结性银粒子等。
半导体元件3具有表面电极4。表面电极4形成于半导体元件3的表面(上表面)。在表面电极4中，例如使用含有硅(Si)的铝(Al)合金等。表面电极4也可以具有包覆层。在包覆层中，例如使用镍(Ni)、金(Au)或者将它们层叠的构造。导体6被接合到表面电极4上。接合件5配置于导体6上。表面电极4和导体6通过导电性的接合件5接合。作为接合件5，例如使用焊料、烧结性银粒子等。
作为导体6，例如使用铜(Cu)。导体6也可以是与接合件5不同的材料。线8与导体6通过具有导电性的接合件7接合。作为接合件7，例如使用焊料、烧结性银粒子等。接合件7例如优选为包含银的烧结体(Ag烧结体)。
如图3所示，导体6也可以具有线8和接合件7进入的槽6a。在导体6的上表面设置有槽6a。线8以及接合件7以进入到槽6a的方式配置。通过导体6具有槽6a，易于将线8放入到槽6a，利用接合件7固定。
线8既可以是一根，也可以是多根。线8与导体图案1a、1c接合。即，线8的一方端被接合到导体图案1a，线8的另一方端被接合到导体图案1c。导体图案1a和导体图案1c既可以是不同的图案，也可以是连接的一个图案。在线8是多根的情况下，线8的两端无需全部被分别键合到导体图案1a和导体图案1c，而也可以一部分的线8与导体图案1a和导体图案1c以外的其他导体图案连接。在线8中，例如使用金(Au)、铝(Al)、铜(Cu)等。
接下来，参照图4～图6，说明本发明的实施方式1所涉及的半导体模块的制造方法。
如图4所示，在本实施方式所涉及的半导体模块的制造方法中，在设置于基板1的表面的导体图案1b上，通过接合件2接合半导体元件3。导体6通过接合件5被接合到半导体元件3的表面电极4上。
接下来，如图5所示，线8的两端通过超声波接合被接合到基板1的表面的导体图案1a、1c。线8跨越半导体元件3的表面电极4而将线8的两端部8a的各个端部键合到基板1的导体图案1a、1c。被键合到基板1的导体图案1a、1c的线8与半导体元件3的表面电极4电连接。
也可以在线8的两端和导体图案1a、1c接合之后，以接近导体6的方式按压线8而使其变形。此时，如图6所示，在导体6具有用于放入线8的槽6a的情况下，也可以以使线8进入到导体6的槽6a的方式将线8推入到槽6a。线8被推入到槽6a内之后在槽6a内用接合件7接合导体6和线8。由此，制造图1～图3所示的半导体模块。
接下来，说明本实施方式所涉及的半导体模块的效果。
如图1、图2以及图3所示，通过利用具有导电性的接合件7将线8与导体6接合，例如相对半导体元件3在纵向从下表面流到表面电极4的电流能够按照具有导电性的接合件5、导体6、具有导电性的接合件7、线8、导体图案1a、1c的顺序流过。
此时，如果假设如上述通常的半导体模块，将线8通过超声波接合键合到半导体元件3的表面电极4，则在与表面电极4的线8的接合部中形成切口形状。因此，在半导体模块的运用中的发热、冷却的反复所致的温度变化时，在线8的接合部中应力集中到切口形状的端，而从切口形状的端发生破坏。换言之，在半导体模块中，温度的变化变得最大的是半导体元件周边。而且，在上述通常的导体模块中，在温度变化最大的半导体元件周边，具有应力集中的利用超声波接合的线键合部。因此，在可靠性的点存在问题。另外，能够使用以往的线键合装置容易地制作。
另一方面，在本实施方式所涉及的半导体模块中，线8跨越半导体元件3的表面电极4而两端部8a的各个端部被键合到基板1，并与表面电极4电连接。因此，在与表面电极4的线8的接合部中未形成切口形状，所以能够抑制应力集中到线8的接合部的端。因此，能够使与半导体元件3的表面电极4的线8的接合部长寿命化。另外，作为线8使用键合线，所以相比于线8通过焊料被接合到表面电极4的情况，能够增加线8的根数。因此，能够减小每一根线的电流密度。进而，线8跨越表面电极4而被键合到基板1，所以能够使电流流向线8的两端。由此，能够减小每一根线的电流密度。
另外，在本实施方式所涉及的半导体模块中，半导体元件3配置于导体图案(第1导体部)1a与导体图案1c(第2导体部)之间。因此，线8能够跨越半导体元件3的表面电极4而与表面电极4电连接。线8的两端部8a中的第1端部8a1被键合到导体图案1a，线8的两端部8a中的第1端部8a1被键合到导体图案1c。因此，能够使电流流向线8的两端部8a的各个端部。
另外，在本实施方式所涉及的半导体模块中，线8通过接合件7与接合于表面电极4上的导体6接合。因此，并非通过超声波接合，而能够通过接合件7接合与半导体元件3电连接的导体6和线8。因此，导体6和线8的接合部并非切口形状，所以能够使与导体6的线8的接合部长寿命化。
另外，在线8被键合到半导体元件3的表面电极4的情况以及线8通过焊料等接合件被接合到半导体元件3的表面电极4的情况下，一般而言，线8的线膨胀系数比半导体元件3的线膨胀系数大到几倍以上。因此，在半导体模块的运用中的发热、冷却的反复所致的温度变化时，发生由半导体元件3的线膨胀系数和线8的线膨胀系数的差异所致的热应力。由于在线8被键合到表面电极4的接合面附近以及将半导体元件3和线8接合的接合件中产生该热应力，在该接合面以及该接合件易于发生破坏。
另一方面，在本实施方式中，在半导体元件3与线8之间介有导体6，所以考虑导体6和线8的线膨胀系数差所致的热应力以及半导体元件3和导体6的线膨胀系数差所致的热应力即可。导体6和线8由于一般而言线膨胀系数差小，所以发生的热应力小。半导体元件3和导体6虽然线膨胀系数差大，但由于半导体元件3和导体6的接合部的端未成为切口形状，所以能够将发生的热应力抑制得较低。进而，半导体元件3和导体6的接合面积相比于线键合的面积大到几十倍以上，所以能够使接合部长寿命化。
另外，在本实施方式所涉及的半导体模块中，线8以及接合件7以进入到槽6a的方式配置，所以易于将线8放入到槽6a而利用接合件7固定。
另外，在本实施方式所涉及的半导体模块中，接合件7是包含银的烧结体。由此，通过使用高耐热、高可靠性的接合件，能够使线8的接合部长寿命化。因此，能够大幅提高半导体模块的可靠性。
另外，在本实施方式所涉及的半导体模块中，线8的材质是铜。由此，能够降低半导体模块的成本。
本实施方式所涉及的半导体模块的制造方法具备以下的工序。跨越接合于基板1的半导体元件3的表面电极4而线8的两端部8a的各个端部被键合到基板1。被键合到基板1的线8与半导体元件3的表面电极4电连接。因此，能够制造能够使半导体元件3的表面电极4和线8的接合部长寿命化，并且减小每一根线的电流密度的半导体模块。
另外，本实施方式所涉及的半导体模块的制造方法还具备以下的结构。在上表面设置有槽6a的导体6被接合到表面电极4上。线8被推入到槽6a内之后在槽6a内用具有导电性的接合件7接合导体6和线8。易于将线8放入到槽6a而通过接合件7固定。另外，作为芯片上的布线构造，不使用线以外的铜板等，而能够使用以往的线和线键合装置来布线，所以具有制造容易这样的优点。
实施方式2.
参照图7～图9，说明本发明的实施方式2所涉及的半导体模块的构造。此外，在此主要说明与实施方式1不同的点。图7是本实施方式所涉及的半导体模块的正面图。图5是本实施方式所涉及的半导体模块的俯视图。图6是本实施方式所涉及的半导体模块的端面图。
如图7、图8以及图9所示，本实施方式所涉及的半导体模块与实施方式1所涉及的半导体模块同样地，主要具有基板1、接合件2、半导体元件3、接合件5、导体6、接合件7以及线8。
也可以如图8所示，线8排成2列而被键合到导体图案1a、1c。另外，也可以如图9所示，在线8在导体6的槽6a中被接合时，排成2层以上而接合。
接下来，说明本实施方式所涉及的半导体模块的制造方法。
本实施方式所涉及的半导体模块的制造方法与实施方式1所涉及的半导体模块的制造方法相同，如图8所示，仅在线8被键合时排成2列而被键合到导体图案1a、1c的点不同。此外，线8也可以排成3列以上而键合，线8的两端部8a的各个端部也可以被键合到导体图案1a、1c的任意的位置。
接下来，说明本实施方式所涉及的半导体模块的效果。在此，说明在实施方式1所涉及的半导体模块的效果中未记载的效果。
在本实施方式所涉及的半导体模块中，通过与导体6的线8的接合部成为2层以上，不依赖于半导体元件3的表面积，而能够任意地增加与一个半导体元件3电连接的线8的根数。在半导体模块中，不仅是半导体元件3，而且线8中的损失所致的发热也是缩短半导体模块的寿命的主要原因。在本实施方式中，能够减少每一根线的电流密度，所以能够使半导体模块长寿命化。
接下来，参照图10～图12，说明本实施方式的变形例所涉及的半导体模块。此外，本实施方式的变形例只要未特别说明，则具备与上述本实施方式同样的结构，所以对相同要素附加相同符号，不反复其说明。
如图10所示，在本实施方式的变形例1所涉及的半导体模块中，在第1层的线8彼此之间配置有第2层的线8，在第2层的线彼此之间配置有第1层的线。即，第1层的线8和第2层的线8以相互填充第1层的线8彼此之间和第2层的线8彼此之间的方式排列。
根据本实施方式的变形例1所涉及的半导体模块，能够缩短第1层的线8和第2层的线8的层叠方向的距离。因此，能够使半导体模块小型化。
如图11以及图12所示，在本实施方式的变形例2中的半导体模块中，在导体6之上进而经由导电性的接合件11接合导体12。导体12具有槽12a。线14在槽12a内通过导电性的接合件13接合。在线14中，例如使用金(Au)、铝(Al)、铜(Cu)等。作为导体12，例如使用铜(Cu)。作为接合件13，例如使用焊料、烧结性银粒子等。线8和线14以在相互交叉的方向跨越半导体元件3的表面电极4的方式配置。
在半导体元件3上将导体通过接合件接合2个以上的情况下，既可以首先利用接合件7接合导体6和线8之后，利用接合件13接合线14和导体12，也可以使接合件7和接合件13同时硬化。
根据本实施方式的变形例2所涉及的半导体模块，能够使线8和线14跨越半导体元件3的表面电极4的方向相互不同。由此，能够提高线的配置的自由度。
实施方式3.
参照图13～15，说明本发明的实施方式3所涉及的半导体模块的构造。此外，在此，主要说明与实施方式1不同的点。图13是本实施方式所涉及的半导体模块的正面图。图14是本实施方式所涉及的半导体模块的俯视图。图15是将本实施方式所涉及的半导体模块的图13中的XV部分的沿着图14中的XV-XV线的剖面放大而示出的剖面图。
如图13、图14以及图15所示，本实施方式所涉及的半导体模块与实施方式1所涉及的半导体模块同样地，主要具有基板1、接合件2、半导体元件3、接合件5、导体6、接合件7以及线8。
如图13以及图14所示，在从上观察导体6以及半导体元件3时，导体6的面积小于半导体元件3的面积。即，在俯视时，导体6的面积小于半导体元件3。即，导体6的上表面的面积小于半导体元件3的上表面的面积。具体而言，导体6的纵宽小于半导体元件3的纵宽，导体6的横宽小于半导体元件3的横宽。
如图15所示，在导体6具有槽6a的情况下，在剖视时，槽6a也可以是沿着线8跨越表面电极4的方向，槽6a的中央部(内部)的深度深、且端部的深度浅的形状。即，导体6具有沿着线8跨越表面电极4的方向而槽6a的端部的深度比槽6a的中央部的深度浅的形状。也可以是槽6a的两端部的各个端部的深度比槽6a的中央部的深度浅。
此外，本实施方式所涉及的半导体模块的制造工序与实施方式1所涉及的半导体模块的制造工序相同。
接下来，说明本实施方式所涉及的半导体模块的效果。在此，说明在实施方式1以及实施方式2所涉及的半导体模块的效果中未记载的效果。
根据本实施方式所涉及的半导体模块，在从上观察导体6以及半导体元件3时，导体6的面积小于半导体元件3的面积，所以能够确保施加高电压并且需要保持绝缘的导体图案1b与线8之间的绝缘距离。
另外，根据本实施方式所涉及的半导体模块，沿着线8跨越表面电极4的方向，相比于槽6a的中央部的深度，槽6a的端部的深度更浅，所以能够确保施加高电压并且需要保持绝缘的导体图案1b与线8之间的绝缘距离。
实施方式4.
本实施方式是将上述实施方式1～3所涉及的半导体模块应用于电力变换装置的例子。本发明不限定于特定的电力变换装置，但以下作为实施方式4，说明对三相的逆变器应用本发明的情况。
图16是示出应用本实施方式的电力变换装置的电力变换系统的结构的框图。
图16所示的电力变换系统包括电源100、电力变换装置200、负载300。电源100是直流电源，对电力变换装置200供给直流电力。电源100能够由各种结构构成，例如，既能够由直流系统、太阳能电池、蓄电池构成，也可以由与交流系统连接的整流电路、AC/DC转换器构成。另外，也可以由将从直流系统输出的直流电力变换为预定的电力的DC/DC转换器构成电源100。
电力变换装置200是在电源100与负载300之间连接的三相的逆变器，将从电源100供给的直流电力变换为交流电力，对负载300供给交流电力。电力变换装置200如图16所示，具备：主变换电路201，将直流电力变换为交流电力而输出；以及控制电路203，将控制主变换电路201的控制信号输出到主变换电路201。
负载300是通过从电力变换装置200供给的交流电力驱动的三相的电动机。此外，负载300不限于特定的用途，而是搭载于各种电气设备的电动机，被用作例如面向混合动力汽车、电动汽车、铁路车辆、电梯或者空调设备的电动机。
以下，详细说明电力变换装置200。主变换电路201具备开关元件和续流二极管(未图示)，通过开关元件进行开关，将从电源100供给的直流电力变换为交流电力，供给给负载300。主变换电路201的具体的电路结构有各种例子，但本实施方式的主变换电路201是2电平的三相全桥电路，能够包括6个开关元件和与各个开关元件反并联的6个续流二极管。主变换电路201的各开关元件、各续流二极管由与上述实施方式1～3中的任意实施方式相当的半导体模块202构成。6个开关元件针对每2个开关元件串联连接而构成上下臂，各上下臂构成全桥电路的各相(U相、V相、W相)。而且，各上下臂的输出端子、即主变换电路201的3个输出端子与负载300连接。
另外，主变换电路201具备驱动各开关元件的驱动电路(未图示)，但驱动电路也可以内置于半导体模块202，还可以是与半导体模块202独立地具备驱动电路的结构。驱动电路生成驱动主变换电路201的开关元件的驱动信号，供给给主变换电路201的开关元件的控制电极。具体而言，依照来自后述控制电路203的控制信号，将使开关元件成为导通状态的驱动信号和使开关元件成为截止状态的驱动信号输出到各开关元件的控制电极。在将开关元件维持为导通状态的情况下，驱动信号是开关元件的阈值电压以上的电压信号(导通信号)，在将开关元件维持为截止状态的情况下，驱动信号成为开关元件的阈值电压以下的电压信号(截止信号)。
控制电路203以对负载300供给期望的电力的方式控制主变换电路201的开关元件。具体而言，根据应供给给负载300的电力，计算主变换电路201的各开关元件应成为导通状态的时间(导通时间)。例如，能够通过根据应输出的电压调制开关元件的导通时间的PWM控制，控制主变换电路201。而且，以在各时间点向应成为导通状态的开关元件输出导通信号、并向应成为截止状态的开关元件输出截止信号的方式，向主变换电路201具备的驱动电路输出控制指令(控制信号)。驱动电路依照该控制信号，向各开关元件的控制电极输出导通信号或者截止信号作为驱动信号。
在本实施方式所涉及的电力变换装置中，作为主变换电路201的开关元件和续流二极管，应用实施方式1～3所涉及的半导体模块，所以能够实现使电力变换装置长寿命化，并且减小半导体模块的每一根线的电流密度。
在本实施方式中，说明了对2电平的三相逆变器应用本发明的例子，但本发明不限于此，能够应用于各种电力变换装置。在本实施方式中，设为2电平的电力变换装置，但也可以是3电平、多电平的电力变换装置，在对单相负载供给电力的情况下，也可以对单相的逆变器应用本发明。另外，在对直流负载等供给电力的情况下，还能够对DC/DC转换器、AC/DC转换器应用本发明。
另外，应用本发明的电力变换装置不限定于上述负载是电动机的情况，例如，也能够用作放电加工机、激光加工机或者感应加热烹调器、非接触器供电系统的电源装置，进而还能够用作太阳能发电系统、蓄电系统等的功率调节器。
应认为本次公开的实施方式在所有点为例示而不限定于此。本发明的范围并非由上述说明而由权利要求书表示，意图包括与权利要求书均等的意义以及范围内的所有变更。

Claims (11)

1.一种半导体模块，具备：
基板；
半导体元件，被接合到所述基板上，并且具有表面电极；以及
线，跨越所述半导体元件的所述表面电极而两端部的各个端部被键合到所述基板，
所述线与所述表面电极电连接。
2.根据权利要求1所述的半导体模块，其中，
所述基板包括绝缘层和设置于所述绝缘层上的导体图案，
所述导体图案包括第1导体部和第2导体部，
所述半导体元件配置于所述第1导体部与所述第2导体部之间，
所述线的所述两端部中的第1端部被键合到所述第1导体部，所述线的所述两端部中的第2端部被键合到所述第2导体部。
3.根据权利要求1或者2所述的半导体模块，其中，还具备：
导体，被接合到所述表面电极上；以及
接合件，配置于所述导体上，并且具有导电性，
所述线与所述导体通过所述接合件接合。
4.根据权利要求3所述的半导体模块，其中，
所述导体包括设置于上表面的槽，
所述线以及所述接合件以进入到所述槽的方式配置。
5.根据权利要求4所述的半导体模块，其中，
所述槽具有沿着所述线跨越所述表面电极的方向而所述槽的端部的深度比所述槽的中央部的深度浅的形状。
6.根据权利要求3～5中的任意一项所述的半导体模块，其中，
所述接合件是包含银的烧结体。
7.根据权利要求3～6中的任意一项所述的半导体模块，其中，
在从上观察所述导体以及所述半导体元件时，所述导体的面积小于所述半导体元件的面积。
8.根据权利要求1～7中的任意一项所述的半导体模块，其中，
所述线的材质是铜。
9.一种半导体模块的制造方法，具备：
跨越被接合到基板的半导体元件的表面电极而将线的两端部的各个端部键合到所述基板的工序；以及
将被键合到所述基板的所述线与所述半导体元件的所述表面电极电连接的工序。
10.根据权利要求9所述的半导体模块的制造方法，其中，还具备：
将在上表面设置有槽的导体接合到所述表面电极上的工序；以及
在所述槽内推入所述线之后在所述槽内将所述导体和所述线用具有导电性的接合件接合的工序。
11.一种电力变换装置，具备：
主变换电路，具有权利要求1～8中的任意一项所述的半导体模块，该主变换电路将输入的电力变换而输出；以及
控制电路，将控制所述主变换电路的控制信号输出到所述主变换电路。
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245769A (ja) * 1990-02-23 1991-11-01 Fuji Electric Co Ltd 高集積型パワー半導体モジュール
US6204162B1 (en) * 1998-11-05 2001-03-20 Shinko Electric Industries Co., Ltd. Production of semiconductor device
JP2002141433A (ja) * 2000-10-30 2002-05-17 Kyocera Corp 半導体装置
US20080128755A1 (en) * 2006-12-01 2008-06-05 Shingo Fukamizu Semiconductor integrated circuit and manufacturing method thereof
EP2159834A1 (en) * 2009-09-01 2010-03-03 ABB Technology AG Conductive bond wire coating
CN102124563A (zh) * 2008-06-30 2011-07-13 三洋电机株式会社 元件搭载用基板、半导体模块、半导体装置、元件搭载用基板的制造方法、半导体装置的制造方法及便携式设备
US20110309497A1 (en) * 2010-06-18 2011-12-22 David Wei Wang Multi-chip stack package structure
CN102316627A (zh) * 2010-06-29 2012-01-11 日立空调·家用电器株式会社 Led点灯装置
US20140264383A1 (en) * 2013-03-15 2014-09-18 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US20150221626A1 (en) * 2014-01-30 2015-08-06 Hitachi Power Semiconductor Device, Ltd. Power Semiconductor Module
CN105762130A (zh) * 2014-12-15 2016-07-13 财团法人工业技术研究院 功率模块

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053864A (en) * 1976-12-20 1977-10-11 Sprague Electric Company Thermistor with leads and method of making
JPS6022821B2 (ja) * 1977-07-22 1985-06-04 株式会社日立製作所 半導体装置
JP3809379B2 (ja) 2002-01-24 2006-08-16 三洋電機株式会社 半導体装置およびその製造方法
US7531893B2 (en) * 2006-07-19 2009-05-12 Texas Instruments Incorporated Power semiconductor devices having integrated inductor
DE102008003971A1 (de) * 2008-01-11 2009-07-16 Ledon Lighting Jennersdorf Gmbh Leuchtdiodenanordnung mit Schutzrahmen
JP5125530B2 (ja) 2008-01-16 2013-01-23 日産自動車株式会社 電力変換装置
JP2009206140A (ja) * 2008-02-26 2009-09-10 Sumitomo Electric Ind Ltd パワーモジュール
JP5185956B2 (ja) 2010-01-06 2013-04-17 三菱電機株式会社 電力用半導体装置
US20150249940A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Method and apparatus for performing call recovery after call drop
JP2016163024A (ja) * 2015-03-05 2016-09-05 三菱電機株式会社 パワーモジュール

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245769A (ja) * 1990-02-23 1991-11-01 Fuji Electric Co Ltd 高集積型パワー半導体モジュール
US6204162B1 (en) * 1998-11-05 2001-03-20 Shinko Electric Industries Co., Ltd. Production of semiconductor device
JP2002141433A (ja) * 2000-10-30 2002-05-17 Kyocera Corp 半導体装置
US20080128755A1 (en) * 2006-12-01 2008-06-05 Shingo Fukamizu Semiconductor integrated circuit and manufacturing method thereof
CN102124563A (zh) * 2008-06-30 2011-07-13 三洋电机株式会社 元件搭载用基板、半导体模块、半导体装置、元件搭载用基板的制造方法、半导体装置的制造方法及便携式设备
EP2159834A1 (en) * 2009-09-01 2010-03-03 ABB Technology AG Conductive bond wire coating
US20110309497A1 (en) * 2010-06-18 2011-12-22 David Wei Wang Multi-chip stack package structure
CN102316627A (zh) * 2010-06-29 2012-01-11 日立空调·家用电器株式会社 Led点灯装置
US20140264383A1 (en) * 2013-03-15 2014-09-18 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US20150221626A1 (en) * 2014-01-30 2015-08-06 Hitachi Power Semiconductor Device, Ltd. Power Semiconductor Module
CN105762130A (zh) * 2014-12-15 2016-07-13 财团法人工业技术研究院 功率模块

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