JP6846117B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6846117B2 JP6846117B2 JP2016079856A JP2016079856A JP6846117B2 JP 6846117 B2 JP6846117 B2 JP 6846117B2 JP 2016079856 A JP2016079856 A JP 2016079856A JP 2016079856 A JP2016079856 A JP 2016079856A JP 6846117 B2 JP6846117 B2 JP 6846117B2
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Description
図1は、本発明の一実施形態に係る半導体装置1の模式的な斜視図(上面側)である。図2は、本発明の一実施形態に係る半導体装置1の模式的な斜視図(下面側)である。図3は、図1のIII−III切断線における断面図である。
半導体装置1は、QFN(Quad Flat Non-leaded Package)が適用された半導体装置である。半導体装置1は、半導体チップ2をアイランド3、リード4およびワイヤ5とともに樹脂パッケージ6で封止した構造を有している。半導体装置1(樹脂パッケージ6)の外形は、扁平な直方体形状である。
アイランド3は、平面視四角形状に形成されており、各側面が半導体装置1の側面と平行をなすように半導体装置1の中央部に配置されている。
リード4は、アイランド3の各側面と対向する位置に、同数(この実施形態では4本)ずつ設けられている。各リード4は、アイランド3の側面に対して交差する方向(この実施形態では直交方向)に延びる長尺な平面視長方形状に形成されている。むろん、各リード4は、上記交差方向に長手な長方形状である必要はなく、上記交差方向が幅方向である長方形状であってもよいし、正方形状であってもよい。複数のリード4は、アイランド3の側面と平行な方向に等しい間隔を空けて配列されている。
なお、半導体チップ2とアイランド3との電気的な接続が不要な場合には、裏メタル8が省略されて、半導体チップ2がアイランド3に絶縁性ペーストからなる接合材を介して接合されてもよい。この場合、アイランド3の表面上のめっき層9が省略されてもよい。
図4〜図9は、半導体チップ2のパッド7付近の拡大図である。図4〜図9を参照して、半導体チップ2のパッド構造をより具体的に説明する。この実施形態で説明するパッド構造は、主にAlパッド上のめっき層の構造に係るものである。当該めっき層は、たとえば、Alパッド−Cuワイヤ接合が適用される半導体装置において生じ得る下記の課題(1)〜(3)の解決に貢献する。
(1)パッドクラックによるショート不良
(2)高温放置試験時の合金成長によるオープン不良
(3)不飽和加圧蒸気試験(HAST)、飽和加圧蒸気試験(PCT)の試験時の接合部腐食によるオープン不良
図4を参照して、半導体チップ2(図示せず)は、半導体基板14、多層配線構造15、絶縁膜16および表面保護膜17を含む。
多層配線構造15は、半導体素子18と電気的に接続された配線層であり、複数の絶縁膜および配線層を含む。この実施形態では、多層配線構造15は、第1絶縁層19、第2絶縁層20および第3絶縁層21を有し、配線層として、第1配線層22および本発明の配線層の一例としての第2配線層23を有している。
第1配線層22および第2配線層23は、この実施形態ではAl配線層であるが、他の金属材料からなる配線層であってもよい。また、第1配線層22および第2配線層23は、同じ材料で形成されていなくてもよい。たとえば、最上層の第2配線層23をAl配線層で形成し、それよりも下方の第1配線層22を含む配線層をCuダマシン配線としてもよい。複数のビア24は、たとえばタングステン等の金属材料からなっていてもよい。
絶縁膜16は、第2配線層23を含む第3絶縁層21の上面領域を覆うように配置されている。絶縁膜16には、第2配線層23の一部をパッド7として露出させるパッド開口25が形成されている。絶縁膜16は、パッド開口25の外縁26が第2配線層23の外縁27よりも内側に配置されるように、その一部が第2配線層23にオーバーラップ部28として乗り上がっていてもよい。絶縁膜16のオーバーラップ部28以外の残りの部分は、本体部35として第3絶縁層21と密着して設けられていてもよい。絶縁膜16のオーバーラップ部28と本体部35とは、第2配線層23の厚さからなる高低差に基づく段部36を介して連なっている。
表面保護膜17は、絶縁膜16上に積層されている。表面保護膜17には、少なくともパッド7の露出を確保する第2パッド開口32が形成されている。表面保護膜17は、図4では、第2パッド開口32の外縁33とパッド開口25の外縁26とが一致するように、その一部が第2配線層23の上面領域にオーバーラップ部34として乗り上がっていてもよい。この実施形態では、表面保護膜17のオーバーラップ部34は、第2パッド開口32の周縁部43と称してもよい。表面保護膜17のオーバーラップ部34以外の残りの部分は、本体部37として絶縁膜16と密着して設けられていてもよい。また、表面保護膜17は、絶縁膜16の段部36上の領域において、第2配線層23に近づく方向に向かって厚さが減少するように形成されている。これにより、表面保護膜17は、段部36の高低差を吸収し、絶縁膜16の本体部35、段部36およびオーバーラップ部28上の領域に跨って一定の高さの平坦面を有している。
そして、パッド7上には、シード層38を介してめっき層39が形成されている。この実施形態では、シード層38は、めっき層39の下面全域にわたって設けられている。つまり、シード層38およびめっき層39は、互いに面一なめっき端面42を有している。めっき端面42は、半導体基板14の表面に沿う方向において、たとえば、第2配線層23の外縁27と一致する位置に配置されていてもよい。
めっき層39は、シード層38からのめっき成長によって構成された金属層であり、半導体チップ2において、図3に示したワイヤ5が接合される部分である。めっき層39は、シード層38と同様に、パッド開口25から外側へ向かって絶縁膜16の周縁部41の上面領域まで延びている。この実施形態では、第2パッド開口32の外縁33とパッド開口25の外縁26とが一致していて、絶縁膜16が表面保護膜17で完全に覆われていることから、めっき層39およびシード層38は、表面保護膜17の上面に接するように形成されている。
図5では、表面保護膜17の第2パッド開口32の外縁33が、絶縁膜16のパッド開口25の外縁26よりも外側に配置されている。これにより、パッド開口25の外縁26と第2パッド開口32の外縁33との間に、絶縁膜16の上面の一部が露出している。
この実施形態では、めっき層39は、パッド開口25の周縁部41および第2パッド開口32の周縁部43(オーバーラップ部34)上に連なって形成されている。
また、めっき層39は、第2パッド開口32の内方領域において第2パッド開口32の外縁33から間隔を空けて配置されている。
この実施形態では、めっき層39は、表面保護膜17の周縁部43および絶縁膜16の周縁部41の上面領域を覆うように形成されている。
図10および図11は、半導体チップ2の製造工程の一部を工程順に示す図である。図11では、図4〜図9に示した構成のうち半導体チップ2の製造方法の説明に必要な構成のみを示している。また、図11では、図4〜図9のうち代表例として図4の構造の製造工程を示すが、図5〜図9の構造については、絶縁膜16、表面保護膜17およびめっき層39を形成するためのマスクパターンを変更することで、図4の構造と同様に製造することができる。
次に、図11Cに示すように、たとえばスピンコート法によって、絶縁膜16上に表面保護膜17が形成される(ステップS3)。
次に、図11Fに示すように、シード層38上に、めっき層39を形成すべき領域に開口46を有するマスク47が形成される(ステップS6)。
この後は、シード層38の不要部分が除去される工程、複数のチップ形成領域44が各半導体チップ2の個片に切り分けられる工程等が行われ、半導体チップ2が得られる。
以上、上記の実施形態によれば、めっき層39を電解めっきによって形成するので、めっき層39の形成に要するコストを低減することができる。また、めっき前に、めっき対象物であるパッド7を前処理する必要がないので、パッド7に不具合が発生することを防止することもできる。
無電解めっきでは、めっき前に、めっき対象物の表面を前処理しなければならない。たとえば、Niめっきの場合には、事前にパッド7にジンケート処理が行われる。この処理が行われると、図12に示すように、Alパッド7におけるビア24の直上位置にスパイク48(微孔)が形成される。その結果、図13に示すように、めっき成長の際、スパイク48がめっき金属で埋め戻される前に、スパイク48の開口端部でめっき金属同士が繋がり、スパイク48内に空洞の巣49が発生する場合がある。
また、図14は、無電解めっきによって形成されためっき層を有する半導体チップのSEM画像である。この半導体チップでは、絶縁膜16および表面保護膜17の開口25,32を、同じエッチング工程(等方性エッチング)で形成している。そのため、図14に示すように、エッチング時の横方向侵食によって、表面保護膜17の下方に空隙50が形成されている。
また、図7〜図9の構造のように、めっき層39が第2配線層23の上面領域に収まる大きさで形成されていれば、比較的硬いめっき層39(特にNi)を起点に絶縁膜16や表面保護膜17にクラックが生じても、そのクラックを第2配線層23で阻止することができる。その結果、当該クラックが半導体素子18にまで達して短絡することを防止することができる。
以上、本発明の一実施形態を説明したが、本発明は、他の形態で実施することもできる。
本発明の半導体装置は、パワーモジュール等のパワーデバイスの製造全般に利用可能であり、特に、小型・軽量化が求められている分野、車載、太陽電池、産業機器向けの装置等、温度変化が激しい環境下で使用される装置に良好に適用できる。
2 半導体チップ
5 ワイヤ
7 パッド
14 半導体基板
16 絶縁膜
17 表面保護膜
23 第2配線層
25 パッド開口
26 (パッド開口の)外縁
27 (パッドの)外縁
32 第2パッド開口
33 (第2パッド開口の)外縁
38 シード層
39 めっき層
40 (パッド開口の)側面
41(パッド開口の)周縁部
43 (第2パッド開口の)周縁部
44 チップ形成領域
45 半導体ウエハ
47 マスク
Claims (15)
- 第1配線層が形成された半導体基板と、
前記第1配線層を覆うように前記半導体基板上に形成された絶縁層と、
前記絶縁層上に形成された第2配線層と、
前記第2配線層を覆うように前記絶縁層上に形成され、前記第2配線層の一部をパッドとして露出させるパッド開口を有する絶縁膜と、
前記パッドの直下の領域において前記絶縁層を貫通し、前記第1配線層および前記第2配線層を接続するビアと、
前記絶縁膜上に形成され、前記絶縁膜とは異なる絶縁材料からなり、少なくとも前記パッドの一部の露出を確保する第2パッド開口を有する表面保護膜と、
前記パッド上に形成されたシード層と、
前記シード層上に形成されためっき層とを含み、
前記絶縁膜は、前記絶縁層の上面および前記第2配線層の一部を覆う下層のライナー窒化シリコン膜と、前記ライナー窒化シリコン膜上に形成された中間のHDP酸化シリコン膜と、前記HDP酸化シリコン膜上に形成された表面窒化シリコン膜とを含み、
前記ライナー窒化シリコン膜、前記HDP酸化シリコン膜および前記表面窒化シリコン膜のうち、前記ライナー窒化シリコン膜が最も薄く、次いで、前記表面窒化シリコン膜が薄く、前記HDP酸化シリコン膜が最も厚い、半導体装置。 - 前記パッド開口の外縁と、前記第2パッド開口の外縁とが一致している、請求項1に記載の半導体装置。
- 前記第2パッド開口の外縁が、前記パッド開口の外縁よりも外側に配置されており、
前記パッド開口の外縁と前記第2パッド開口の外縁との間に、前記絶縁膜の上面の一部からなるパッド周縁部が露出しており、
前記めっき層は、前記パッド周縁部上に配置されている、請求項1に記載の半導体装置。 - 前記めっき層は、前記第2パッド開口の内方領域において前記第2パッド開口の外縁から間隔を空けて配置されている、請求項3に記載の半導体装置。
- 前記めっき層は、前記パッド周縁部、および前記表面保護膜の上面の一部からなる第2パッド周縁部上に連なって配置されている、請求項3に記載の半導体装置。
- 前記パッド開口の側面が前記表面保護膜で覆われるように、前記第2パッド開口の外縁が、前記パッド開口の外縁よりも内側に配置されている、請求項1に記載の半導体装置。
- 前記めっき層は、前記表面保護膜の上面の一部からなる第2パッド周縁部上に配置されている、請求項6に記載の半導体装置。
- 前記めっき層は、前記第2パッド開口の内方領域において前記第2パッド開口の外縁から間隔を空けて配置されている、請求項3に記載の半導体装置。
- 前記めっき層は、前記第2配線層の上面領域に収まる大きさで形成されている、請求項1〜8のいずれか一項に記載の半導体装置。
- 前記第2配線層は、Al配線層を含む、請求項1〜9のいずれか一項に記載の半導体装置。
- 前記表面保護膜がポリイミド膜を含む、請求項1〜10のいずれか一項に記載の半導体装置。
- 前記めっき層は、Niおよび前記Ni上のPdからなる積層構造を含む、請求項1〜11のいずれか一項に記載の半導体装置。
- 前記パッドに接続されたCuを主成分とする金属材料からなるワイヤをさらに含む、請求項1〜12のいずれか一項に記載の半導体装置。
- 第1配線層、前記第1配線層を覆う絶縁層、前記絶縁層上の第2配線層、ならびに前記絶縁層を貫通し、前記第1配線層および前記第2配線層を接続するビアが形成された半導体基板上に、前記第2配線層を覆うように絶縁膜を形成する工程と、
前記絶縁膜の前記ビアの直上の部分を選択的に除去することによって、前記第2配線層の一部を前記ビアに対向するパッドとして露出させるパッド開口を形成する工程と、
前記絶縁膜上に、前記絶縁膜とは異なる絶縁材料からなる表面保護膜を形成する工程と、
前記表面保護膜を選択的に除去することによって、少なくとも前記パッドの一部の露出を確保する第2パッド開口を形成する工程と、
前記パッド上にシード層を形成する工程と、
電解めっきによって、前記シード層からめっき層を成長させる工程とを含み、
前記絶縁膜を形成する工程は、前記絶縁層の上面および前記第2配線層の一部を覆うように下層のライナー窒化シリコン膜を形成し、前記ライナー窒化シリコン膜上に中間のHDP酸化シリコン膜を形成し、前記HDP酸化シリコン膜上に表面窒化シリコン膜を形成する工程を含み、
前記ライナー窒化シリコン膜、前記HDP酸化シリコン膜および前記表面窒化シリコン膜のうち、前記ライナー窒化シリコン膜が最も薄く、次いで、前記表面窒化シリコン膜が薄く、前記HDP酸化シリコン膜が最も厚い、半導体装置の製造方法。 - 前記半導体基板は、それぞれが前記第2配線層を有する複数のチップ形成領域を有する半導体ウエハを含み、
前記シード層を形成する工程は、前記複数のチップ形成領域を覆うように前記半導体ウエハ全体に前記シード層を形成する工程を含み、
前記めっき層を成長させる工程は、前記シード層を選択的に覆うマスクを形成し、前記マスクから露出する前記シード層の一部から前記めっき層を成長させる工程を含む、請求項14に記載の半導体装置の製造方法。
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