JP5432543B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5432543B2 JP5432543B2 JP2009038716A JP2009038716A JP5432543B2 JP 5432543 B2 JP5432543 B2 JP 5432543B2 JP 2009038716 A JP2009038716 A JP 2009038716A JP 2009038716 A JP2009038716 A JP 2009038716A JP 5432543 B2 JP5432543 B2 JP 5432543B2
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- Japan
- Prior art keywords
- metal layer
- barrier metal
- insulating film
- opening
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000002184 metal Substances 0.000 claims description 103
- 230000004888 barrier function Effects 0.000 claims description 82
- 238000000034 method Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 description 33
- 229910045601 alloy Inorganic materials 0.000 description 12
- 239000000956 alloy Substances 0.000 description 12
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000006722 reduction reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000013585 weight reducing agent Substances 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
- H01L2224/03472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
- H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
Description
2 電極端子
3 第1絶縁膜
3a 第1開口部
4 第2絶縁膜
4a 第2開口部
5 バリアメタル層
6 バンプ
7 バリアメタル層
7a 第1バリアメタル層
7b 第2バリアメタル層
Claims (1)
- 半導体基板に電子回路を形成し、該電子回路の端子を外部回路と電気的接続するために形成された電極端子が露出するように、前記半導体基板の表面に開口部を有する絶縁膜を形成する工程と、
前記開口部から露出する前記電極端子の表面全面に、および前記開口部周囲の前記絶縁膜上にバリアメタル層を形成する工程と、
該バリアメタル層上に、印刷、ボールドロップまたは吐出の方法によりバンプを形成する工程とを有し、
前記電極端子上の前記バリアメタル層と前記絶縁膜上の前記バリアメタル層とが、該絶縁膜による段差部において不連続になるように前記絶縁膜および前記バリアメタル層を形成することを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009038716A JP5432543B2 (ja) | 2009-02-21 | 2009-02-21 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009038716A JP5432543B2 (ja) | 2009-02-21 | 2009-02-21 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010199103A JP2010199103A (ja) | 2010-09-09 |
JP5432543B2 true JP5432543B2 (ja) | 2014-03-05 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009038716A Active JP5432543B2 (ja) | 2009-02-21 | 2009-02-21 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5432543B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102500170B1 (ko) * | 2018-01-03 | 2023-02-16 | 삼성전자주식회사 | 금속 범프를 갖는 반도체 소자 및 그 제조방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06112209A (ja) * | 1992-09-29 | 1994-04-22 | Matsushita Electron Corp | 半導体装置の製造方法 |
US6959856B2 (en) * | 2003-01-10 | 2005-11-01 | Samsung Electronics Co., Ltd. | Solder bump structure and method for forming a solder bump |
JP2006165595A (ja) * | 2006-02-03 | 2006-06-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP5162851B2 (ja) * | 2006-07-14 | 2013-03-13 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
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2009
- 2009-02-21 JP JP2009038716A patent/JP5432543B2/ja active Active
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JP2010199103A (ja) | 2010-09-09 |
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