WO2023019516A1 - 芯片封装结构及电子设备 - Google Patents

芯片封装结构及电子设备 Download PDF

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Publication number
WO2023019516A1
WO2023019516A1 PCT/CN2021/113573 CN2021113573W WO2023019516A1 WO 2023019516 A1 WO2023019516 A1 WO 2023019516A1 CN 2021113573 W CN2021113573 W CN 2021113573W WO 2023019516 A1 WO2023019516 A1 WO 2023019516A1
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WO
WIPO (PCT)
Prior art keywords
chip
contact
circuit path
contacts
redistribution layer
Prior art date
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PCT/CN2021/113573
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English (en)
French (fr)
Inventor
赵南
谢文旭
李品辉
蒋尚轩
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21953760.2A priority Critical patent/EP4362086A1/en
Priority to PCT/CN2021/113573 priority patent/WO2023019516A1/zh
Priority to CN202180097957.0A priority patent/CN117296147A/zh
Publication of WO2023019516A1 publication Critical patent/WO2023019516A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a chip packaging structure and electronic equipment.
  • SBAFOP Silicon bridge across fan out package
  • FOP 2.5D fan out package
  • the SBAFOP structure in the prior art transmits the power signal on the packaging substrate to the connected chip through conductive pillars and through silicon vias (TSV), which requires complex processes to form TSV, resulting in product failure. Increased cost and increased complexity.
  • TSV through silicon vias
  • the embodiment of the present application provides a chip packaging structure and electronic equipment, which are used to solve the problem of how to reduce the cost and complexity of the SBAFOP structure without affecting the internal power supply of the SBAFOP.
  • a chip packaging structure including: a first chip, a second chip, a first connection chip, a redistribution layer, a plurality of conductive pillars, and a packaging substrate.
  • the redistribution layer includes opposite first surfaces and second surfaces; the first chip and the second chip are arranged side by side on the first surface of the redistribution layer, and there is a gap between the first chip and the second chip; the first connection chip is arranged On the second surface of the redistribution layer; the bottoms of the first chip and the second chip are provided with a plurality of first contacts and a plurality of second contacts, and the first contacts are distributed on the first chip and the second chip The area where the bottom is covered by the projection of the first connecting chip, and the second contacts are distributed in the area of the bottom of the first chip and the second chip that is not covered by the projection of the first connecting chip; the redistribution layer is supported by a plurality of conductive columns above the package substrate , a plurality of conductive pillars are arranged on the periphery of the first connection chip; a first circuit path and a second circuit path are arranged in the redistribution layer, and the first circuit path is used to connect part of the conductive pillars among
  • the package substrate is soldered to the conductive pillars through C4 bumps or solder balls, and the signals on the package substrate are transmitted to the conductive pillars.
  • the conductive column is arranged on the periphery of the first connection chip, and is electrically connected with the redistribution layer. The signal on the conductive column is transmitted to the first chip and the second chip through the circuit path on the redistribution layer, so as to supply power to the first chip and the second chip.
  • the power supply method adopted in the embodiment of the present application can reduce the cost on the basis of ensuring the power supply requirements of the internal circuits of the chip packaging structure.
  • the power supply method adopted in the embodiment of the present application can reduce the number of metal layers in the redistribution layer, and reduce the The thickness of the thin heavy wiring layer.
  • the area of the first connection chip can be reduced, which helps to achieve short-distance and high-density interconnection between the first chip and the second chip, In order to meet the needs of large bandwidth, high speed, high performance and low cost chips.
  • the side of the first connection chip facing the redistribution layer is further provided with a plurality of first auxiliary contacts, and the first auxiliary contacts are arranged correspondingly to the first contacts; the redistribution layer further includes a third circuit path , the third circuit path is used to electrically connect some of the plurality of conductive pillars with the first auxiliary contact.
  • the signal on the conductive column is transmitted to the first connection chip through the circuit path on the redistribution layer, so as to supply power to the first connection chip.
  • the power supply method adopted in the embodiment of the present application can reduce the cost and reduce the area of the first connection chip on the basis of ensuring the power supply demand of the internal circuit of the chip packaging structure.
  • the redistribution layer further includes a fourth circuit path, and the fourth circuit path is used to connect the first contact at the bottom of the second chip, It is electrically connected with the first auxiliary contact at the corresponding position of the first connection chip.
  • a new power supply path that can be included in the chip packaging structure can enrich the power supply network of the chip packaging structure and improve the application range of the chip packaging structure.
  • the side of the first connection chip facing the redistribution layer is further provided with a plurality of second auxiliary contacts, and the second auxiliary contacts are distributed on the first connection chip which is not covered by the projection of the first chip and the second chip. Area.
  • At least part of the second auxiliary contact is electrically connected to part of the first auxiliary contact inside the first connecting chip; Part of the conductive columns in the columns are electrically connected to the second auxiliary contact.
  • a new power supply path that can be included in the chip packaging structure can enrich the power supply network of the chip packaging structure and improve the application range of the chip packaging structure.
  • the redistribution layer further includes a sixth circuit path; the sixth circuit path is used to electrically connect the first contact at the bottom of the first chip with the first auxiliary contact at the corresponding position of the first connection chip.
  • a new power supply path that can be included in the chip packaging structure can enrich the power supply network of the chip packaging structure and improve the application range of the chip packaging structure.
  • the redistribution layer further includes a seventh circuit path; the seventh circuit path is used to electrically connect at least part of the second auxiliary contacts.
  • a new power supply path that can be included in the chip packaging structure can enrich the power supply network of the chip packaging structure and improve the application range of the chip packaging structure.
  • the first chip and the second chip further include a plurality of third contacts, and the third contacts are distributed in the area where the bottom of the first chip and the second chip are covered by the projection of the first connecting chip; the first connection The chip also includes a plurality of third auxiliary contacts, and the third auxiliary contacts are distributed correspondingly to the third contacts; the redistribution layer also includes an eighth circuit path; the eighth circuit path is used to connect the third contact to the third auxiliary contact Point electrical connection. A manner in which the first chip and the second chip are interconnected through the first connecting chip is realized.
  • the first line path is used to transmit the intellectual property power signal and the ground signal; the second line path is used to transmit the intellectual property power signal, the core power signal and the ground signal.
  • the chip packaging structure further includes a second connection chip; the second connection chip is arranged side by side with the first connection chip on the second surface of the redistribution layer; the projection of the second connection chip covers the first chip and the second connection chip. part of the chip.
  • the chip packaging structure further includes a third chip; the third chip is disposed on the first surface of the redistribution layer, and there is a space between the first chip and the second chip; a part of the third chip is covered by the first Projection overlay of connected chips.
  • the chip packaging structure is flexible in design and strong in applicability.
  • a second aspect of the embodiments of the present application provides an electronic device, including the chip package structure according to any one of the first aspect and a printed circuit board, where the chip package structure is arranged on the printed circuit board.
  • the electronic device provided by the embodiment of the present application includes the chip packaging structure of the first aspect, and its beneficial effect is the same as that of the chip packaging structure, so it will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application.
  • FIG. 3A is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 3B is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 4A is a schematic diagram of a partial power supply path of a chip packaging structure provided by an embodiment of the present application.
  • FIG. 4B is a top view of a chip packaging structure provided by an embodiment of the present application.
  • FIG. 4C is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • Fig. 5A is a cross-sectional view along the A1-A2 direction in Fig. 4B provided by the embodiment of the present application;
  • Fig. 5B is a cross-sectional view along the B1-B2 direction in Fig. 4B provided by the embodiment of the present application;
  • FIG. 6A is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 6B is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 6C is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9A is a top view of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 9B is a top view of another chip packaging structure provided by the embodiment of the present application.
  • Fig. 9C is a cross-sectional view along the C1-C2 direction in Fig. 9A provided by the embodiment of the present application;
  • Fig. 9D is a cross-sectional view along the D1-D2 direction in Fig. 9A provided by the embodiment of the present application;
  • Fig. 9E is a cross-sectional view along the E1-E2 direction in Fig. 9A provided by the embodiment of the present application;
  • FIG. 10A is a top view of another chip packaging structure provided by the embodiment of the present application.
  • Fig. 10B is a cross-sectional view along the F1-F2 direction in Fig. 10A provided by the embodiment of the present application;
  • FIG. 10C is a cross-sectional view along the G1-G2 direction in FIG. 10A provided by the embodiment of the present application;
  • FIG. 11A is a top view of another chip packaging structure provided by the embodiment of the present application.
  • Figure 11B is a cross-sectional view along the H1-H2 direction in Figure 11A provided by the embodiment of the present application;
  • Fig. 11C is a cross-sectional view along the I1-I2 direction in Fig. 11A provided by the embodiment of the present application;
  • FIG. 12A is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 12B is a schematic diagram of a partial power supply path of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 13A is a top view of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 13B is a top view of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 14A is a top view of another chip packaging structure provided by the embodiment of the present application.
  • FIG. 14B is a top view of another chip packaging structure provided by the embodiment of the present application.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • An embodiment of the present application provides an electronic device, which can be a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, and a vehicle-mounted computer, or a smart display wearable device such as a smart watch or a smart bracelet, or a Servers, storage, base stations and other communication equipment, or smart cars, etc.
  • a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, and a vehicle-mounted computer
  • a smart display wearable device such as a smart watch or a smart bracelet, or a Servers, storage, base stations and other communication equipment, or smart cars, etc.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • the following embodiments all take the electronic device as a mobile phone as an example for illustration.
  • the electronic device 1 mainly includes a display module 2 , a middle frame 3 , a case (or called a battery cover, a rear case) 4 and a cover plate 5 .
  • the display module 2 has a light-emitting side where the display screen can be seen and a back side opposite to the light-emitting side.
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3.
  • the cover plate 5 may be, for example, cover glass (CG), and the cover glass may have certain toughness.
  • the middle frame 3 is located between the display module 2 and the housing 4, and the surface of the middle frame 3 away from the display module 2 is used for installing internal components such as a battery, a printed circuit board (PCB), a camera (camera), and an antenna. . After the casing 4 and the middle frame 3 are closed, the above-mentioned internal components are located between the casing 4 and the middle frame 3 .
  • the above-mentioned electronic device 1 also includes a processor (center processing unit, CPU) chip, a radio frequency chip, a radio frequency power amplifier (power amplifier, PA) chip, a system on a chip (system on a chip, SOC), and a power supply arranged on the PCB.
  • Management chips power management integrated circuits, PMIC), storage chips (such as high bandwidth memory (HBM)), audio processor chips, touch screen control chips, NAND flash (flash memory), image sensor chips and other electronic devices, PCB It is used to carry the above-mentioned electronic devices and complete signal interaction with the above-mentioned electronic devices.
  • the embodiment of the present application provides a chip packaging structure, as shown in FIG. , the first connection chip 21 has a plurality of through silicon vias (through silicon via, TSV).
  • the conductive pillars 30 are disposed on the packaging substrate 10 and located on the periphery of the first connection chip 21 .
  • the first chip 41 is disposed on the conductive pillar 30 and the first connecting chip 21 , and is electrically connected with the conductive pillar 30 and the first connecting chip 21 .
  • the second chip 42 is disposed on the conductive pillar 30 and the first connecting chip 21 , and is electrically connected with the conductive pillar 30 and the first connecting chip 21 .
  • the first chip 41 and the second chip 42 cannot directly transmit signals through the conductive pillars 30, but pass through
  • the TSV in the first connection chip 21 is used to transmit the power signal on the packaging substrate 10 to the first chip 41 and the second chip 42 .
  • the embodiment of the present application also provides a chip packaging structure.
  • the chip packaging structure includes: a packaging substrate 10, a first connecting chip 21, a plurality of conductive pillars 30, a first chip 41, a second chip 42 and redistribution layer 50.
  • the redistribution layer (also called redistribution layer or redistribution layer, RDL) 50 includes a first surface and a second surface opposite to each other.
  • the redistribution layer 50 includes alternately arranged metal layers and insulating layers.
  • the material of the metal layer may include, for example, one or more conductive materials selected from copper, aluminum, nickel, gold, silver, and titanium.
  • the material of the insulating layer may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silica gel, and polyimide.
  • the first chip 41 and the second chip 42 are arranged side by side on the first surface of the redistribution layer 50 , and are bonded to the redistribution layer 50 , with a gap between the first chip 41 and the second chip 42 .
  • each chip includes a substrate and a functional layer disposed on the substrate.
  • the functional layer can enable the chip to realize its own functions, such as logic computing functions or storage functions, etc. during operation.
  • the functional layer mainly includes functional devices, circuit structures, interconnection metal lines, and dielectric layers.
  • first chip 41 and the second chip 42 in the chip packaging structure of the embodiment of the present application may be bare chips cut from a wafer (or called bare die, grains or particles). It may also be a packaged chip obtained by packaging a bare chip. Of course, it is not limited that the first chip 41 and the second chip 42 must both be bare chips or packaged chips. It is also possible that the first chip 41 is a bare chip (such as the aforementioned SOC), and the second chip 42 is a packaged chip (such as the aforementioned HBM).
  • first chip 41 and the second chip 42 in the chip package structure are electrically connected to the redistribution layer 16
  • one chip may be electrically connected to the redistribution layer 16 at a time, or multiple chips at a time may be used. Electrically connected to the redistribution layer 16 .
  • the thicknesses of the first chip 41 and the second chip 42 along a direction perpendicular to the packaging substrate 10 may be the same.
  • the thicknesses of the first chip 41 and the second chip 42 along a direction perpendicular to the package substrate 10 may also be different, which is not limited in this embodiment of the present application.
  • the active surface of each first chip 41 and the active surface of each second chip 42 face the substrate 10 .
  • what is exposed on the active surfaces of the first chip 41 and the second chip 42 may be a pad, or a bump structure may be formed on the pad, and the bump structure may be, for example, a solder ball bump. point (ball bump), or copper pillar bump (Cu bump), etc.
  • the first connection chip 21 is disposed on the second surface of the redistribution layer 50 and is electrically connected to the redistribution layer 50 .
  • the first connection chip 21 is located between the redistribution layer 50 and the packaging substrate 10 .
  • the projection of the first connecting chip 21 covers partial areas of the first chip 41 and the second chip 42 .
  • a partial area of the first chip 41 is located directly above the first connecting chip 21
  • a partial area of the second chip 42 is located directly above the first connecting chip 21 .
  • a partial area of the first chip 41 overlaps with the first connecting chip 21
  • a partial area of the second chip 42 overlaps with the first connecting chip 21 .
  • the first chip 41 and the second chip 42 are interconnected through the first connection chip 21 .
  • the required circuit can be directly made on the wafer according to the need, and then the first connection chip 21 can be obtained after dicing, which can be used in the chip packaging structure.
  • the first connection chip 21 can be understood as a bridge silicon chip (silicon bridge die, SBD).
  • the material of the substrate of the first connection chip 21 may include one or more of silicon (Si), germanium (Ge), gallium nitride (GaN), gallium arsenide (GaAs) or other semiconductor materials, for example.
  • the material of the substrate may be, for example, glass, organic material, and the like.
  • the bridge silicon chip is only an illustration.
  • the active surface of the first connection chip 21 faces the redistribution layer 50 and is electrically connected to the redistribution layer 50 .
  • the back surface of the first connection chip 21 is disposed on the packaging substrate 10 and fixedly connected to the packaging substrate 10 .
  • no TSV is provided inside the first connection chip 21 .
  • the back surface of the first connection chip 21 is bonded to the packaging substrate 10 .
  • the back surface of the first connecting chip 21 is bonded to the packaging substrate 10 through a die attach film (DAF).
  • DAF die attach film
  • the back surface of the first connection chip 21 is bonded to the packaging substrate 10 by double-sided adhesive.
  • TSVs are disposed inside the first connection chip 21 .
  • the TSVs in the first connection chip 21 are electrically connected to the packaging substrate 10 on the backside of the first connection chip 21 .
  • the TSVs in the first connection chip 21 are coupled to the substrate 10 through fusion bonding or adhesive bonding.
  • the TSV inside the first connection chip 21 is not used for transmitting the power signal on the packaging substrate 10 to the first chip 41 and the second chip 42 , but for other functions.
  • Other functions may be to transmit the power signal on the package substrate 10 to the first connection chip 21 to improve the utilization rate of the pins on the package substrate 10 under the first connection chip 21 .
  • the redistribution layer 50 is supported above the packaging substrate 10 by a plurality of conductive pillars 30, the plurality of conductive pillars 30 are arranged on the periphery of the first connection chip 21, and the plurality of conductive pillars 30 are electrically connected to the packaging substrate 10 and the redistribution layer 50 respectively. , so as to transmit the signal on the package substrate 10 to the redistribution layer 50 .
  • the material of the conductive pillar 30 may include one or more of titanium (Ti), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W) or related alloys, for example.
  • a second redistribution layer 90 is further disposed between the conductive pillar 30 and the package substrate 10 , and the second redistribution layer 90 and the package substrate 10 are soldered by C4 bumps or solder balls.
  • the second redistribution layer 90 may only include a single metal layer, or may include multiple metal layers, which is not limited in this embodiment of the present application.
  • the chip packaging structure further includes a first plastic encapsulation layer 60, the first plastic encapsulation layer 60 wraps the sides of the first connecting chip 21 and the conductive pillars 30, exposing the active surface of the first connecting chip 21 and the sides of the conductive pillars 30.
  • the top surface protects the first connection chip 21 and the conductive pillar 30 .
  • the material of the first plastic sealing layer 60 may be, for example, molding compound (molding), epoxy resin adhesive (epoxy molding compound, EMC) or insulating material.
  • the chip packaging structure further includes a second plastic encapsulation layer 70, the second plastic encapsulation layer wraps at least the side surfaces of the first chip 41 and the second chip 42 to protect the first chip 41 and the second chip 42 effect.
  • the chip package structure further includes an underfill layer 80 filling the periphery of the C4 bump or solder ball.
  • the underfill layer 80 is located between the first molding layer 60 and the packaging substrate 10 .
  • the underfill layer 80 is located between the second redistribution layer 90 and the package substrate 10 .
  • CCF capillary underfill
  • MCF mold underfill
  • NCF non-conductive film
  • NCF non-conductive paste
  • Any one of the NCP processes forms the underfill layer 80 .
  • the chip package structure further includes at least one of a pressure ring, a heat dissipation cover, or a third plastic packaging layer.
  • the pressure ring is disposed on the surface of the packaging substrate 10 and located at the periphery of the first plastic sealing layer 60 .
  • the heat dissipation cover is mated and connected with the packaging substrate 10, and the first connection chip 21, the conductive pillar 30, the first chip 41, the second chip 42, the first plastic packaging layer 60, the second plastic packaging layer 70 and the underfill layer 80 are all located on the heat dissipation cover. In the accommodation cavity formed by matching with the packaging substrate 10 .
  • the third plastic encapsulation layer wraps at least the sides of the first plastic encapsulation layer 60 , the second plastic encapsulation layer 70 and the underfill layer 80 .
  • the third plastic encapsulation layer can also cover the top surfaces of the second plastic encapsulation layer 70 , the first chip 41 and the second chip 42 .
  • FIG. 3A illustrates the chip packaging structure including the third plastic packaging layer as an example
  • FIG. 3B illustrates the chip packaging structure including the heat dissipation cover as an example.
  • first chips 41 and second chips 42 in the chip packaging structure are interconnected through the first connecting chip 21, and there may be multiple chips including the first chip 41, the second chip 42 in the chip packaging structure.
  • the unit group of the chip 42 and the first connection chip 21 are interconnected through the first connecting chip 21, and there may be multiple chips including the first chip 41, the second chip 42 in the chip packaging structure.
  • the first chip 41 and the second chip 42 are interconnected through the first connecting chip 21.
  • the higher integration level makes the obtained chip package structure have higher integration level, which is suitable for ultra-high integration high performance computing (high performance computing, HPC) packaging.
  • a plurality of first contacts 43 and a plurality of second contacts 44 are provided on the bottoms of the first chip 41 and the second chip 42 .
  • the first contacts 43 are distributed in the areas where the bottoms of the first chip 41 and the second chip 42 are projected and covered by the first connecting chip 21 . That is to say, the first contacts 43 are distributed in the areas of the first chip 41 and the second chip 42 that are located directly above the first connecting chip 21 and overlap with the first connecting chip 21 .
  • the second contacts 44 are distributed in areas of the bottoms of the first chip 41 and the second chip 42 that are not covered by the projection of the first connecting chip 21 . That is to say, the second contacts 44 are distributed in areas where the first chip 41 and the second chip 42 do not overlap with the first connection chip 21 .
  • first contact 43 and the second contact 44 may be conductive structures such as solder pads, solder balls, and conductive columns.
  • a first circuit path 1 is disposed in the redistribution layer 60 , and the first circuit path 1 is used to electrically connect a part of the plurality of conductive pillars 30 with the first contact 43 .
  • the first circuit path 1 is used to electrically connect a part of the plurality of conductive pillars 30 with the first contact 43 .
  • a second circuit path 2 is also provided in the redistribution layer 60 , and the second circuit path 2 is used to electrically connect a part of the plurality of conductive pillars 30 with the second contact 44 .
  • the second circuit path 2 is used to electrically connect a part of the plurality of conductive pillars 30 with the second contact 44 .
  • the type of the signal transmitted by the first line path 1 is not limited.
  • part of the first circuit path 1 may be used to transmit an intellectual property (intellectual property, IP) power signal to supply power to IP units inside the first chip 41 and the second chip 42 .
  • Part of the first circuit path 1 can be used to transmit ground signals, so as to realize the return flow of power and signals of the first chip 41 and the second chip 42 .
  • IP intellectual property
  • the type of the signal transmitted by the second line path 2 is not limited.
  • part of the second line path 2 may be used to transmit IP power signals, and part of the second line path 2 may be used to transmit ground signals.
  • Part of the second circuit path 2 can also be used to transmit core power signals to supply power to the core units of the first chip 41 and the second chip 42 .
  • first circuit path 1 and the second circuit path 2 can be realized by adjusting the number of metal layers in the redistribution layer 50 and the pattern of each metal layer.
  • the specific paths are not limited, and the first circuit path can be realized. 1 and the power supply effect of the second line path 2.
  • the plurality of conductive pillars 30 in the chip package structure may include a plurality of IP power conductive pillars 31 , a plurality of core power conductive pillars 33 and a plurality of ground conductive pillars 32 .
  • a plurality of IP power supply conductive columns 31, a plurality of core power supply conductive columns 33 and a plurality of ground conductive columns 32 are distributed in the area defined by the redistribution layer 60, and some conductive columns 30 are located under the first chip 41 and the second chip 42 , part of the conductive pillars 30 are located on the periphery of the first chip 41 and the second chip 42 .
  • the plurality of first contacts 43 in the chip package structure includes a first IP power contact 431 and a first ground contact 432 .
  • the area M1 of the first chip 41 projected and covered by the first connection chip 21 (referred to as the first coverage area in the embodiment of the application) is distributed with a first IP power contact 431 and a first ground contact 432.
  • the area N1 of the second chip 42 projected and covered by the first connecting chip 21 (referred to as the second coverage area in the embodiment of the present application) is also distributed with a first IP power contact 431 and a first ground contact 432 .
  • the plurality of second contacts 44 in the chip package structure includes a second IP power contact 441 , a second ground contact 442 and a core power contact 443 .
  • the area M2 of the first chip 41 that is not covered by the projection of the first connecting chip 21 (referred to as the first uncovered area in the embodiment of the application) is distributed with a second IP power contact 441 and a second ground contact 442 And the core power contact 443, the area of the second chip 42 that is not covered by the projection of the first connection chip 21 (referred to as the second uncovered area in the embodiment of the application) N2 is also distributed with the second IP power contact 441, The second ground contact 442 and the core power contact 443 .
  • the conductive column 30 shown in FIG. 4A as the IP power conductive column 31
  • the first contact 43 as the first IP power contact 431
  • the second contact 44 as the second IP power contact 441 as an example for illustration.
  • part of the IP power conductive columns 31 among the plurality of IP power conductive columns 31 are electrically connected to the first circuit path 1, and the IP power signal on the package substrate 10 is transmitted through the IP power conductive columns 31 To the first line path 1.
  • the first circuit path 1 is electrically connected to the first IP power contact 431, and the first circuit path 1 on the left transmits the IP power signal to the first IP power contact 431 of the first chip 41, and then to the first IP power contact 431.
  • the first circuit path 1 on the right transmits the IP power signal to the first IP power contact 431 of the second chip 42 , and then to the second coverage area N1 of the second chip 42 .
  • IP power conductive columns 31 are electrically connected to the second circuit path 2 , and transmit the IP power signal on the packaging substrate 10 to the second circuit path 2 through the IP power conductive columns 31 .
  • the second circuit path 2 is electrically connected to the second IP power contact 441, and the second circuit path 2 on the left transmits the IP power signal to the second IP power contact 441 of the first chip 41, and then to the first IP power contact 441.
  • the second circuit path 2 on the right transmits the IP power signal to the second IP power contact 441 of the second chip 42 , and then to the second uncovered area N2 of the second chip 42 .
  • the conductive column 30 shown in FIG. 4A is the ground conductive column 32
  • the first contact 43 is the first ground contact 432
  • the second contact 44 is the second ground contact 442 as an example for illustration.
  • some of the ground conductive pillars 32 are electrically connected to the first circuit path 1, and the part of the ground conductive pillars 32 are connected to the first ground contact through the first circuit path 1.
  • 432 is electrically connected.
  • the first circuit path 1 on the left transmits the ground signal to the first ground contact 432 of the first chip 41 , and then to the first coverage area M1 of the first chip 41 .
  • the ground signal on the package substrate 10 is transmitted to the first circuit path 1 on the right through the right ground conductive pillar 32 .
  • the first circuit path 1 on the right transmits the ground signal to the first ground contact 432 of the second chip 42 , and then to the second coverage area N1 of the second chip 42 .
  • Part of the ground conductive pillars 32 in the plurality of ground conductive pillars 32 is electrically connected to the second circuit path 2 , and the part of the ground conductive pillars 32 is electrically connected to the second ground contact 442 through the second circuit path 2 .
  • the second circuit path 2 on the left transmits the ground signal to the second ground contact 442 of the first chip 41 , and then to the first uncovered area M2 of the first chip 41 .
  • the ground signal on the packaging substrate 10 is transmitted to the second circuit path 2 on the right through the right ground conductive pillar 32 .
  • the second circuit path 2 on the right transmits the ground signal to the second ground contact 442 of the second chip 42 , and then to the second uncovered area N2 of the second chip 42 .
  • the conductive post 30 is the core power conductive post 33
  • the second contact 44 is the core power contact 443 as an example for illustration.
  • a plurality of core power conductive columns 33 are electrically connected to the second circuit path 2 , and the core power conductive columns 33 are electrically connected to the core power contact 443 through the second circuit path 2 .
  • the second circuit path 2 on the left transmits the core power signal to the core power contact 443 of the first chip 41 , and then to the first uncovered area M2 of the first chip 41 .
  • the core power signal on the packaging substrate 10 is transmitted to the second line path 2 on the right through the right core power conductive column 33 .
  • the second line path 2 on the right transmits the core power signal to the core power contact 443 of the second chip 42 , and then to the second uncovered area N2 of the second chip 42 .
  • the first connection chip 21 has a first circuit path 1 and a second circuit path 2 on the left and right sides.
  • the first circuit path 1 and the second circuit path 2 may be provided on the upper, lower, left and right sides of the first connecting chip 21 . That is to say, the conductive pillars 30 around the first connection chip 21 can transmit signals to the first chip 41 and the second chip 42 through the first circuit path 1 and/or the second circuit path 2 .
  • the IP power conductive column 31 located under the first connection chip 21 can transmit the IP power signal to the first chip 41 and the second chip 42 through the first circuit path 1 .
  • the conductive column 30 on the left can only transmit the power signal to the first chip 41 on the left through the first circuit path 1 .
  • the conductive pillar 30 on the left can also transmit the power signal to the first chip 41 on the right through the first circuit path 1 .
  • the conductive pillar 30 on the right can also transmit the power signal to the first chip 41 on the left through the first circuit path 1 .
  • the principle of proximity may be adopted when selecting the conductive pillar 30 connected to the first line path 1 and the second line path 2 .
  • the side of the first connection chip 21 facing the redistribution layer 50 is further provided with a plurality of first auxiliary contacts 210, and the first auxiliary contacts 210 and The first contacts 43 are correspondingly arranged.
  • the first auxiliary contact 210 is arranged corresponding to the first contact 43 , it can be understood that the projection of the first contact 43 overlaps with the first auxiliary contact 210 . That is to say, the first contact 43 is located above the first auxiliary contact 210 .
  • first auxiliary contact 210 is disposed on the first overlapping region L1 of the first connecting chip 21 overlapping with the first overlapping region M1 of the first chip 41 .
  • a first auxiliary contact 210 is also disposed in a second overlapping area L2 of the first connecting chip 21 overlapping with the first overlapping area N1 of the second chip 42 .
  • the first contacts 43 include a first IP power contact 431 and a first ground contact 432 .
  • the first auxiliary contact 210 includes a first auxiliary IP power contact 211 and a first auxiliary ground contact 212 .
  • the first auxiliary IP power contact 211 is set corresponding to the first IP power contact 431 .
  • the first auxiliary ground contact 212 is arranged correspondingly to the first ground contact 432 .
  • the redistribution layer 50 further includes a third circuit path 3 , and the third circuit path 3 is used to connect some conductive columns 30 among the plurality of conductive columns 30 to the first auxiliary contact 210 electrical connection.
  • the type of the signal transmitted by the third line path 3 is not limited.
  • part of the third line path 3 may be used to transmit IP power signals, and part of the third line path 3 may be used to transmit ground signals.
  • the first wire path 1 and the third wire path 3 do not coincide.
  • the first circuit path 1 and the third circuit path 3 are partially overlapped.
  • the first line path 1 and the third line path 3 are substantially completely overlapped, and are transmitted separately at positions close to the first contact 43 and the first auxiliary contact 210, respectively. transmitted to the first contact 43 above the redistribution layer 50 and the first auxiliary contact 210 below the redistribution layer 50 .
  • the first circuit path 1 in FIG. 4B can also be regarded as the third circuit path 3 .
  • some of the IP power conductive columns 31 among the plurality of IP power conductive columns 31 are electrically connected to the third circuit path 3, and the IP power signal on the packaging substrate 10 is electrically conductive through the IP power supply.
  • the column 31 is transferred to the third line path 3 .
  • the third circuit path 3 is electrically connected to the first auxiliary IP power contact 211 , and the third circuit path 3 on the left transmits the IP power signal to the first auxiliary IP power contact 211 in the first overlapping area L1 .
  • the third line path 3 on the right transmits the IP power signal to the first auxiliary IP power contact 211 in the second overlapping area L2.
  • the plurality of first power contacts 211 may be electrically connected inside the first connecting chip 21 or may not be electrically connected as required.
  • the electrical connection can be realized through the metal layer P1 inside the first connection chip 21 . That is to say, the metal layer P1 serves as a network plane for interconnecting the first power contacts 211 .
  • the metal layer P1 may be, for example, a pad layer of the first connection chip 21 .
  • the first auxiliary contact 210 may be disposed on the metal layer P1, and the metal layer P1 is connected to the metal layer through a via (via) between the metal layers.
  • some of the multiple ground conductive pillars 32 are electrically connected to the third line path 3, and the ground signal on the package substrate 10 is transmitted to the third line through the ground conductive pillars 32.
  • Path 3 The third circuit path 3 is electrically connected to the first auxiliary ground contact 212 , and the third circuit path 3 on the left transmits the ground signal to the first auxiliary ground contact 212 in the first overlapping area L1 .
  • the third line path 3 on the right transmits the ground signal to the first auxiliary ground contact 212 in the second overlapping area L2.
  • the plurality of first auxiliary ground contacts 212 can be electrically connected, for example, through the metal layer P2 inside the first connection chip 21 .
  • third circuit paths 3 on the left and right sides of the first connecting chip 21 .
  • the third circuit path 3 can be provided on the upper, lower, left and right sides of the first connecting chip 21 , which can be reasonably set as required.
  • the first chip 41 and the second chip 42 further include a third contact 45, and the third contact 45 is distributed on the bottom of the first chip 41 and is projected and covered by the first connection chip 21. area (the first coverage area M1 ) and the area where the bottom of the second chip 42 is projected and covered by the first connection chip 21 (the second coverage area N1 ).
  • the first connection chip 21 further includes third auxiliary contacts 213 , and the third auxiliary contacts 213 are distributed correspondingly to the third contacts 45 . That is, the projection of the third contact 45 overlaps with the third auxiliary contact 213 . That is to say, the third auxiliary contact 213 corresponding to the third contact 45 in the first coverage area M1 is distributed in the first overlapping area L1 of the first connecting chip 21 , and the second overlapping area of the first connecting chip 21 A third auxiliary contact 213 corresponding to the third contact 45 in the second coverage area N1 is distributed in L2.
  • the third auxiliary contact 213 in the first overlapping area L1 and the third auxiliary contact 213 in the second overlapping area L2 are electrically connected inside the first connection chip 21 .
  • the third auxiliary contact 213 in the first overlapping area L1 is electrically connected to the third auxiliary contact 213 in the second overlapping area L2 through the metal layer P3 inside the first connection chip 21 .
  • the number of the metal layer P3 can be one layer or multiple layers, which can be reasonably set as required.
  • a metal layer P2 may be disposed between adjacent metal layers P3 .
  • third auxiliary contacts 213 are not electrically connected in FIG. 5A , it does not mean that they are not electrically connected. This part of the third auxiliary contact 213 can be electrically connected at other sections.
  • the redistribution layer 50 further includes an eighth circuit path 8 ; the eighth circuit path 8 is used to electrically connect the third contact 45 and the third auxiliary contact 213 .
  • the eighth circuit path 8 is used to electrically connect the third contact 45 and the third auxiliary contact 213 .
  • the power supply path of the chip package structure shown in Figure 7 includes:
  • the first path part of the conductive column 30 transmits the power signal in the package substrate 10 to the first coverage area M1 of the first chip 21 through the first circuit path 1, and part of the conductive column 30 transmits the power signal in the package substrate 10 through the first circuit path 1.
  • the second circuit path 2 is transmitted to the first uncovered area M2 of the first chip 41 . Power supply from the package substrate 10 to the first chip 41 via the conductive pillar 30 and the first circuit path 1 and the second circuit path 2 on the redistribution layer 50 is realized.
  • the second path part of the conductive column 30 transmits the power signal in the package substrate 10 to the second coverage area N1 of the second chip 22 through the first line path 1, and part of the conductive column 30 transmits the power signal in the package substrate 10 through the second path.
  • the second wire path 2 transmits to the second uncovered area N2 of the second chip 42 . Power supply from the packaging substrate 10 to the second chip 42 via the first circuit path 1 and the second circuit path 2 on the conductive pillar 30 and the redistribution layer 50 is realized.
  • the third path part of the conductive pillars 30 transmits the power signal in the package substrate 10 to the first overlapping area L1 of the first connection chip 21 through the third line path 3, and part of the conductive pillars 30 transmits the power signal in the package substrate 10 through the third line path 3.
  • the third circuit path 3 is transmitted to the second overlapping area L2 of the first connecting chip 21 , so as to realize power supply from the packaging substrate 10 to the first connecting chip 21 through the third circuit path 3 on the conductive pillar 30 and the redistribution layer 50 .
  • the path for realizing the interconnection between the first chip 41 and the second chip 42 the interconnection signal in the first chip 41 is transmitted to the first overlapping area L1 of the first connection chip 21 through the eighth power supply path 8, and the interconnection signal is in the first
  • the interior of the connection chip 21 is transmitted from the first overlapping area L1 to the second overlapping area L2, and the interconnection signal is then transmitted from the second overlapping area L2 to the second chip 42 through the eighth power supply path 8, thereby realizing the connection between the first chip 41 and the second chip 42 interconnects.
  • At least part of the first auxiliary contacts 210 are electrically connected inside the first connection chip 21 .
  • the first auxiliary contact 210 electrically connected inside the first connecting chip 21 may include a first auxiliary ground contact 212 for transmitting ground signals, and may also include a first power auxiliary contact for transmitting IP power signals. Point 211.
  • the redistribution layer 50 also includes a fourth circuit path 4, and the fourth circuit path 4 is used to connect the first contact 43 at the bottom of the second chip 42 to the position corresponding to the first connection chip 21 (the first connection chip 21).
  • the first auxiliary contacts 210 of the two overlapping regions L2) are electrically connected.
  • the power signal received by the first auxiliary contact 210 is transmitted to the first contact 43 on the second chip 42 through the fourth circuit path 4 , and then transmitted to the inside of the second chip 42 .
  • the first auxiliary contact 210 electrically connected through the fourth circuit path 4 is the first power auxiliary contact 211
  • the first contact 43 is the first IP power contact 431 .
  • the power supply path of the chip package structure also includes:
  • the fourth power supply path part of the conductive pillar 30 transmits the power signal in the package substrate 10 to the first overlapping area L1 of the first connection chip 21 through the third line path 3, and the power signal passes through the first connection chip 21 inside the first connection chip 21.
  • the first overlapping area L1 is transmitted to the second overlapping area L2
  • the power signal is transmitted to the second coverage area N1 of the second chip 42 through the fourth circuit path 4 in the second overlapping area L2 , and then transmitted to the second chip 42 .
  • the power supply of the line path 4 to the second chip 42 .
  • the difference between the fourth circuit path 4 and the eighth circuit path 8 on the redistribution layer 50 is that the fourth circuit path 4 is used to transmit power signals to the second chip 42, and the eighth circuit path 8 It is used to transmit interconnection signals between the first chip 41 and the second chip 42 .
  • the power signal in the conductive column 30 close to the first chip 41 can be transmitted to the second chip 42 through the first connecting chip 21 .
  • the second chip 42 is connected to the second chip 42 through the conductive column 30 on the side where the first chip 41 is located.
  • the power supply can meet the power supply requirement of the second chip 42 .
  • FIG. 4B shows a top view of the chip package structure, and the top view shows the arrangement and arrangement of a plurality of conductive pillars 30 (including IP power conductive pillars 31, ground conductive pillars 32, and core power conductive pillars 33).
  • the first contact 43 (the first IP power contact 431 and the first ground contact 432) and the second contact 44 (the second IP power contact 441, the second ground contact 442 and the core power contact 443) Arrangement method, but the figure is only an illustration, without any limitation, and the arrangement order of each row can also be changed.
  • the arrangement of the conductive pillars 30 , the first contacts 43 and the second contacts 44 may also be as shown in FIG. 9A and FIG. 9B , which is not limited in this embodiment of the present application.
  • a plurality of conductive columns 30 are arranged in multiple rows and columns along the first direction X and the second direction Y.
  • the conductive pillars 30 above and below the edges of the first chip 41 and the second chip 42 are arranged in multiple rows, and the left and right sides of the edges of the first chip 41 and the second chip 42 are arranged.
  • the conductive pillars 30 on the side are arranged in multiple rows. Wherein, the conductive pillars 30 in adjacent rows are arranged in dislocation, and the conductive pillars 30 in adjacent columns are arranged in dislocation.
  • the IP power supply conductive column 31 is disposed closer to the first connection chip 21 relative to the core power supply conductive column 33 .
  • a row of power supply conductive columns is disposed between adjacent rows of ground conductive columns 32 .
  • a row of power conductive columns may include IP power conductive columns 31; a row of power conductive columns may also include core power conductive columns 33; a row of power conductive columns may include both IP power conductive columns 31 and core power conductive columns 33.
  • the row of conductive pillars 30 closest to the first connection chip 21 is a row of IP power conductive pillars 31 or a row of ground conductive pillars 32 .
  • the row of conductive pillars 30 closest to the first connection chip 21 is a row of IP power conductive pillars 31 or a row of ground conductive pillars 32 .
  • the second contacts 44 are arranged corresponding to the conductive pillars 30 located under the first chip 41 and the second chip 42 .
  • the second contact 44 is located on the periphery of the corresponding conductive column 30 .
  • the second contact 44 corresponding to the IP power supply conductive post 31 is the second IP power contact 441, and one IP power supply conductive post 31 may be provided with at least one second IP power contact 441 correspondingly.
  • one IP power supply conductive column 31 can be provided with multiple second IP power supply contacts 441 correspondingly, as shown in FIG. 31 to enhance the conductive path.
  • the second contact 44 corresponding to the core power supply conductive column 33 is a core power supply contact 443 .
  • At least one core power contact 443 can be provided corresponding to one core power conductive column 33 .
  • one core power supply conductive column 33 can be provided with multiple core power supply contacts 443 correspondingly, as shown in FIG. 9A , the projections of the multiple core power supply contacts 443 are located at the periphery of the correspondingly provided core power supply conductive column 33 .
  • the second contact 44 corresponding to the ground conductive column 32 is the second ground contact 442 .
  • At least one second ground contact 442 can be provided corresponding to one ground conductive column 32 .
  • one ground conductive column 32 can be provided with a plurality of second ground contacts 442 correspondingly, as shown in FIG. 9A , the projections of the plurality of second ground contacts 442 are located at the periphery of the corresponding core power supply conductive column 33 .
  • a plurality of first contacts 43 are arranged in multiple rows along the second direction Y, A plurality of first contacts 43 in each row are arranged in sequence along the first direction X.
  • the plurality of third contacts 45 are arranged in multiple rows along the second direction Y, and the plurality of third contacts 45 in each row are arranged in sequence along the first direction X.
  • At least one row of first IP power contacts 431 , at least one row of third contacts 45 , at least one row of first ground contacts 432 , and at least one row of third contacts 45 are arranged circularly along the second direction Y as a cycle unit.
  • the contacts in adjacent rows are arranged in dislocations.
  • the conductive column 30 adjacent to the first IP power contact 431 in each row is the IP power conductive column 31, and the conductive column 30 adjacent to the first ground contact 432 in each row is the ground.
  • Conductive column 32 is the conductive column 30 adjacent to the first IP power contact 431 in each row.
  • a plurality of first contacts 43 are arranged in multiple rows along the first direction X, and a plurality of first contacts 43 in each row are arranged in sequence along the second direction Y. cloth.
  • the multiple third contacts 45 are arranged in multiple columns along the first direction X, and the multiple third contacts 45 in each column are arranged sequentially along the second direction Y.
  • At least one row of first IP power contacts 431 , at least one row of third contacts 45 , at least one row of first ground contacts 432 , and at least one row of third contacts 45 are arranged circularly along the first direction X.
  • the contacts in adjacent columns are arranged in dislocations.
  • the row of first contacts 43 closest to the conductive pillar 30 is the first IP power contact 431 .
  • a plurality of first contacts 43 are arranged in multiple rows along the first direction X, and a plurality of first contacts 43 in each row are arranged in sequence along the second direction Y. cloth.
  • the multiple third contacts 45 are arranged in multiple columns along the first direction X, and the multiple third contacts 45 in each column are arranged sequentially along the second direction Y.
  • each row of first contacts 43 is composed of first IP power contacts 431 and first ground contacts 432 alternately arranged.
  • the conductive columns 30 adjacent to the first IP power contact 431 are IP power conductive columns 31, and the conductive columns adjacent to the first ground contact 432 are The post 30 is a ground conductive post 32 .
  • the first auxiliary ground contact 212 of the first auxiliary contact 210 is disposed corresponding to the first ground contact one 432 of the first chip 41 and the second chip 42 .
  • the third auxiliary contact 213 is disposed corresponding to the third contact 45 in the first chip 41 and the second chip 42 .
  • the arrangement rule of the contacts in the first overlapping region L1 of the first connecting chip 21 is the same as the arrangement rule of the contacts in the first overlapping region M1 of the first chip 41 .
  • the arrangement law of the contacts in the second overlapping area L2 of the first connecting chip 21 is the same as the arrangement law of the contacts in the second overlapping area N1 of the second chip 42 .
  • the package substrate 10 is soldered to the conductive pillar 30 through C4 bumps or solder balls, and the signal on the package substrate 10 is transmitted to the conductive pillar 30 .
  • the conductive pillars 30 are arranged on the periphery of the first connection chip 21 and are electrically connected to the redistribution layer 50 .
  • the signal on the conductive column 30 is transmitted to the first connection chip 21, the first chip 41 and the second chip 42 through the circuit path on the redistribution layer 50, and supplies power to the first connection chip 21, the first chip 41 and the second chip 42 .
  • the power supply method adopted in the embodiment of the present application can reduce the cost on the basis of ensuring the power supply requirements of the internal circuits of the chip packaging structure.
  • the power supply method adopted in the embodiment of the present application can reduce the number of metal layers in the redistribution layer 50. The thickness of the redistribution layer 50 is reduced.
  • the area of the first connection chip 21 can be reduced, which helps to realize short-distance high-density interconnection between the first chip and the second chip. In order to meet the needs of large bandwidth, high speed, high performance and low cost chips.
  • the difference between the second example and the first example is that the first connecting chip 21 is further provided with a second auxiliary contact between the first overlapping area L1 and the second overlapping area L2.
  • the first connecting chip 21 is further provided with a plurality of second auxiliary contacts 214 on the side facing the redistribution layer 50 , and the second auxiliary contacts 214 are distributed on the first connecting chip 21 that is not covered by the first chip 41 . and the area covered by the projection of the second chip 42 .
  • the second auxiliary contacts 214 are distributed in the first overlapping Between the area L1 and the second overlapping area L2. That is, the second auxiliary contacts 214 are distributed below the gap between the first chip 41 and the second chip 42 .
  • all the second auxiliary contacts 214 can be the second auxiliary IP power contacts 215; or, all the second auxiliary contacts 214 are the second auxiliary ground contacts 216; or, as shown in FIG. 10A, the first Part of the second auxiliary contact 214 is the second auxiliary IP power contact 215 , and part is the second auxiliary ground contact 216 .
  • the arrangement of the second auxiliary contact 214 can also be Adjust accordingly.
  • the first auxiliary IP power contact 211 and the second auxiliary IP power contact 215 are arranged in parallel.
  • the first auxiliary ground contact 212 and the second auxiliary ground contact 216 are arranged in parallel.
  • the second auxiliary contact 214 is connected to the redistribution layer 50, which is equivalent to passing through the second auxiliary contact 214 to increase the supporting point to improve the supporting strength of the gap between the first chip 41 and the second chip 42, and prevent the chip packaging structure from breaking at the gap between the first chip 41 and the second chip 42.
  • At least part of the second auxiliary contact 214 is electrically connected to part of the first auxiliary contact 210 .
  • the electrical connection between the first auxiliary contact 210 and the second auxiliary contact 214 can be realized through the metal layer inside the first connection chip 21.
  • they may be electrically connected through a circuit path on the redistribution layer 50 .
  • the second auxiliary contact 214 is electrically connected to the first auxiliary contact 210 . That is to say, the first auxiliary IP power contact 211 of the first auxiliary contact 210 is electrically connected with the second auxiliary IP power contact 215 of the second auxiliary contact 214 for transmitting the first power signal.
  • the first auxiliary ground contact 212 of the first auxiliary contacts 210 is electrically connected to the second auxiliary ground contact 216 of the second auxiliary contacts 214 for transmitting ground signals.
  • the redistribution layer 50 further includes a fifth wiring path 5 .
  • the fifth circuit path 5 is used to electrically connect some of the plurality of conductive pillars 30 with the second auxiliary contact 214 .
  • the IP power conductive post 31 is electrically connected to the second auxiliary IP power contact 215 through the fifth circuit path 5 .
  • the ground conductive post 32 is electrically connected to the second auxiliary ground contact 216 through the fifth circuit path 5 .
  • the chip package structure can add two power supply paths:
  • the fifth path part of the conductive pillars 30 transmits the power signal in the package substrate 10 to the second auxiliary contact 214 through the fifth line path 5, and the power signal is transmitted to the first connecting chip 21 through the first connecting chip 21.
  • the sixth path part of the conductive column 30 transmits the power signal in the packaging substrate 10 to the second auxiliary contact 214 through the fifth line path 5, and then after the first connection chip 21 is transmitted, part of the power signal can also be transmitted in the second overlapping
  • the area L2 is transmitted to the second chip 42 via the fourth circuit path 4 . Power is supplied from the package substrate 10 to the first connecting chip 21 through the conductive pillar 30 and the fifth circuit path 5 on the redistribution layer 50 , and then to the second chip 42 through the fourth circuit path 4 on the redistribution layer 50 .
  • the redistribution layer 50 further includes a sixth circuit path 6 .
  • the sixth circuit path 6 is used to electrically connect the first contact 43 on the bottom of the first chip 41 with the first auxiliary contact 210 at the corresponding position (the first overlapping area L1 ) of the first connecting chip 21 .
  • the chip package structure can add a power supply path:
  • the seventh path part of the conductive pillar 30 transmits the power signal in the package substrate 10 to the second auxiliary contact 214 through the fifth line path 5, and then after transmitting the first connecting chip 21, part of the power signal can also be transmitted in the first overlapping
  • the area L1 is transmitted to the first chip 41 via the sixth circuit path 6 .
  • Power is supplied from the package substrate 10 to the first connecting chip 21 via the conductive pillar 30 and the fifth circuit path 5 on the redistribution layer 50 , and then to the first chip 41 via the sixth circuit path 6 on the redistribution layer 50 .
  • the difference between the sixth line path 6 and the eighth line path 8 on the redistribution layer 50 is that the sixth line path 6 is used to transmit power signals to the first chip 41, and the eighth line path 8 It is used to transmit interconnection signals between the first chip 41 and the second chip 42 .
  • the redistribution layer 50 further includes a seventh circuit path 7 .
  • the seventh circuit path 7 is used to electrically connect at least part of the second auxiliary contacts 214 .
  • At least part of the second auxiliary contacts 214 are electrically connected inside the first connection chip 21 .
  • the second auxiliary contact 214 By disposing the second auxiliary contact 214 between the first overlapping area L1 and the second overlapping area L2 , on the one hand, it can support the redistribution layer 50 and balance the stress on the redistribution layer 50 .
  • a circuit path can be added on the redistribution layer 50 to realize that the signal on the package substrate 10 is from the peripheral conductive pillar 30 to between the first overlapping area L1 and the second overlapping area L2, and then to the first connection chip 21 or Inside the first chip 41 or the second chip 42, the power supply network and the ground network of the first connection chip 21 can be enriched, and the power supply and return flow to the inside of the chip packaging structure can be strengthened.
  • Example 3 The difference between Example 3 and Example 1 and Example 2 is that the chip package structure further includes a second connection chip.
  • the chip package structure further includes a second connection chip 22 , and the second connection chip 22 is arranged side by side with the first connection chip 21 on the second surface of the redistribution layer 50 .
  • the projection of the second connection chip 22 covers a partial area of the first chip 41 and the second chip 42 . That is to say, a partial area of the first chip 41 is located directly above the second connecting chip 22 , and a partial area of the second chip 42 is located directly above the second connecting chip 22 .
  • a partial area of the first chip 41 is overlapped with the second connection chip 22
  • a partial area of the second chip 42 is overlapped with the second connection chip 22 .
  • the first chip 41 and the second chip 42 are interconnected through the second connecting chip 22 .
  • part of the functional areas of the first chip 41 and the second chip 42 are interconnected through the first connecting chip 21, and part of the functional areas of the first chip 41 and the second chip 42 are connected through the second connecting chip. 22 interconnections.
  • first chip 41 and the second chip 42 may be interconnected through multiple connecting chips, and the chip package structure provided in the embodiment of the present application does not limit the number of connecting chips, which can be reasonably set as required.
  • conductive pillars 30 may be provided between the first connection chip 21 and the second connection chip 22 .
  • no conductive pillar 30 may be provided between the first connection chip 21 and the second connection chip 22 .
  • the structure of the second connection chip 22 may be the same as that of the first connection chip 21 , and it only needs to be arranged corresponding to the first chip 41 and the second chip 42 .
  • Example 4 is different from Example 1 to Example 3 in that: the chip package structure further includes a third chip.
  • the chip package structure further includes a third chip 43 .
  • the third chip 43 is disposed on the first surface of the redistribution layer 50 , and is spaced from the first chip 41 and the second chip 42 ; part of the third chip 43 is covered by the projection of the first connection chip 21 .
  • the third chip 43 can be interconnected with the first chip 41 through the first connection chip 21, the third chip 43 can also be interconnected with the second chip 42 through the first connection chip 21, and the third chip 43 can also be connected through the first connection chip. 21 is interconnected with both the first chip 41 and the second chip 42.
  • the embodiment of the present application does not limit the number of chips interconnected through the first connection chip 21, it may be two, it may be three as shown in FIG. 14A, or it may be four as shown in FIG. 14B (also Including the fourth chip 44), there may be more chips, which can be reasonably set as required.
  • the chip packaging structure provided by the embodiment of the present application has flexible design and strong applicability.

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Abstract

本申请实施例提供一种芯片封装结构及电子设备，涉及半导体技术领域，用于解决如何降低SBAFOP结构的成本和复杂度的问题。芯片封装结构中第一芯片和第二芯片并排设置在重布线层的第一表面上；第一连接芯片被设置在重布线层的第二表面上；第一芯片和第二芯片的底部上设有多个第一触点和多个第二触点，第一触点分布于第一芯片和第二芯片的底部被第一连接芯片投影覆盖的区域，第二触点分布于第一芯片和第二芯片的底部未被第一连接芯片投影覆盖的区域，多个导电柱设置在第一连接芯片的外围，重布线层中第一线路路径用于将多个导电柱中的部分导电柱与第一触点电性连接，重布线层中第二线路路径用于将多个导电柱中的部分导电柱与第二触点电性连接。

Description

芯片封装结构及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片封装结构及电子设备。
背景技术
随着电子技术的发展，电子设备的功能不断的区域丰富化、全面化，使得高阶芯片演进迭代需求与日俱增，芯片的集成度持续的增加，多芯片、高密度集成合封成为趋势。
硅桥式扇出型封装(silicon bridge across fan out package，SBAFOP)是一种实现低成本多芯片集成的封装技术，是通过连接芯片将多个被连芯片进行互连。采用SBAFOP封装技术的结构，相比采用2.5D扇出型封装(fan out package，FOP)封装技术的结构，因连接芯片互连相比重布线层互连，可以缩短被连芯片之间的互连路径，而有较大幅度的性能提升。
而现有技术中的SBAFOP结构，是通过导电柱和硅通孔(through silicon vias，TSV)将封装基板上的电源信号传输至被连芯片，这就需要采用复杂的工艺形成TSV，导致产品的成本提升、复杂度增加。
发明内容
本申请实施例提供一种芯片封装结构及电子设备，用于解决如何在不影响SBAFOP内部供电的前提下，降低SBAFOP结构的成本和复杂度的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种芯片封装结构，包括：第一芯片、第二芯片、第一连接芯片、重布线层、多个导电柱以及封装基板。重布线层包括相对的第一表面和第二表面；第一芯片和第二芯片并排设置在重布线层的第一表面上，第一芯片和第二芯片间存在间隔；第一连接芯片被设置在重布线层的第二表面上；第一芯片和第二芯片的底部上设有多个第一触点和多个第二触点，第一触点分布于第一芯片和第二芯片的底部被第一连接芯片投影覆盖的区域，第二触点分布于第一芯片和第二芯片的底部未被第一连接芯片投影覆盖的区域；重布线层被多个导电柱支撑于封装基板上方，多个导电柱设置在第一连接芯片的外围；重布线层中设置有第一线路路径和第二线路路径，第一线路路径用于将多个导电柱中的部分导电柱与第一触点电性连接；第二线路路径用于将多个导电柱中的部分导电柱与第二触点电性连接。
本申请实施例提供的芯片封装结构，封装基板通过C4 bump或者焊球与导电柱焊接，将封装基板上的信号传输至导电柱上。导电柱排布在第一连接芯片的外围，与重布线层电性连接。导电柱上的信号经重布线层上的线路路径传输至第一芯片以及第二芯片，为第一芯片以及第二芯片供电。相比采用在第一连接芯片中形成TSV和多层重布线层的供电方式，本申请实施例采用的供电方式，在保证芯片封装结构内部电路的供电需求的基础上，可降低成本。相比采用没有连接芯片，而是采用重布线层实现第 一芯片和第二芯片的互连和供电的方式，本申请实施例采用的供电方式可减少重布线层中金属层的层数，减薄重布线层的厚度。另外，由于第一连接芯片中无需为了传输封装基板上的电源信号而形成TSV，可缩小第一连接芯片的面积，有助于实现第一芯片和第二芯片间短距离高密度的互连，从而满足大带宽、高速率、高性能且低成本芯片的需求。
在一些实施例中，第一连接芯片朝向重布线层的一侧还设有多个第一辅助触点，第一辅助触点与第一触点对应设置；重布线层还包括第三线路路径，第三线路路径用于将多个导电柱中的部分导电柱与第一辅助触点电性连接。导电柱上的信号经重布线层上的线路路径传输至第一连接芯片，为第一连接芯片供电。相比采用在第一连接芯片中形成TSV的供电方式，本申请实施例采用的供电方式，在保证芯片封装结构内部电路的供电需求的基础上，可降低成本，缩小第一连接芯片的面积。
在一些实施例中，至少部分第一辅助触点在第一连接芯片内部电性连接；重布线层还包括第四线路路径，第四线路路径用于将第二芯片底部的第一触点，与，第一连接芯片对应位置处的第一辅助触点电性连接。通过在重布线层中设置第四线路路径，可将靠近第一芯片的导电柱中的电源信号经第一连接芯片传输至第二芯片中。这样一来，在第二芯片的供电需求较大，而第二芯片所在侧用于设置导电柱的空间又不够时，通过第一芯片所在侧的导电柱向第二芯片供电，可满足第二芯片的供电需求。
芯片封装结构中可包含的一条新的供电路径，可丰富芯片封装结构的供电网络，提高芯片封装结构的适用范围。
在一些实施例中，第一连接芯片朝向重布线层的一侧还设有多个第二辅助触点，第二辅助触点分布于第一连接芯片未被第一芯片和第二芯片投影覆盖的区域。通过在第一连接芯片与第一芯片重合的第一重合区域和与第二芯片重合的第二重合区域之间设置第二辅助触点，第二辅助触点与重布线层连接，相当于通过第二辅助触点来增加了支撑点，以提高对第一芯片和第二芯片间隙处的支撑强度，避免芯片封装结构在第一芯片和第二芯片的间隙处断裂。
在一些实施例中，至少部分第二辅助触点与部分第一辅助触点在第一连接芯片内部电性连接；重布线层还包括第五线路路径，第五线路路径用于将多个导电柱中的部分导电柱与第二辅助触点电性连接。芯片封装结构中可包含的一条新的供电路径，可丰富芯片封装结构的供电网络，提高芯片封装结构的适用范围。
在一些实施例中，重布线层还包括第六线路路径；第六线路路径用于将第一芯片底部的第一触点与第一连接芯片对应位置处的第一辅助触点电性连接。芯片封装结构中可包含的一条新的供电路径，可丰富芯片封装结构的供电网络，提高芯片封装结构的适用范围。
在一些实施例中，重布线层还包括第七线路路径；第七线路路径用于将至少部分第二辅助触点电性连接。芯片封装结构中可包含的一条新的供电路径，可丰富芯片封装结构的供电网络，提高芯片封装结构的适用范围。
在一些实施例中，第一芯片和第二芯片还包括多个第三触点，第三触点分布于第一芯片和第二芯片的底部被第一连接芯片投影覆盖的区域；第一连接芯片还包括多个第三辅助触点，第三辅助触点与第三触点对应分布；重布线层还包括第八线路路径； 第八线路路径用于将第三触点与第三辅助触点电性连接。实现第一芯片和第二芯片通过第一连接芯片互连的方式。
在一些实施例中，第一线路路径用于传输知识产权电源信号和地信号；第二线路路径用于传输知识产权电源信号、核心电源信号以及地信号。
在一些实施例中，芯片封装结构还包括第二连接芯片；第二连接芯片与第一连接芯片并排设置在重布线层的第二表面上；第二连接芯片的投影覆盖第一芯片和第二芯片的部分区域。在第一芯片和第二芯片互连区域较大，或者多组需要互连的功能区相隔较远的情况下，设置多个互连芯片可减小线路路径，提高互连后的性能。满足不同结构需求。
在一些实施例中，芯片封装结构还包括第三芯片；第三芯片设置在重布线层的第一表面上，与第一芯片和第二芯片间存在间隔；第三芯片的部分区域被第一连接芯片的投影覆盖。芯片封装结构设计灵活，适用性强。
本申请实施例的第二方面，提供一种电子设备，包括第一方面任一项的芯片封装结构和印刷线路板，芯片封装结构设置在印刷线路板上。
本申请实施例提供的电子设备包括第一方面的芯片封装结构，其有益效果与芯片封装结构的有益效果相同，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的一种芯片封装结构的结构示意图；
图3A为本申请实施例提供的另一种芯片封装结构的结构示意图；
图3B为本申请实施例提供的又一种芯片封装结构的结构示意图；
图4A为本申请实施例提供的一种芯片封装结构的部分供电路径示意图；
图4B为本申请实施例提供的一种芯片封装结构的俯视图；
图4C为本申请实施例提供的另一种芯片封装结构的部分供电路径示意图；
图5A为本申请实施例提供的一种沿图4B中A1-A2向的剖视图；
图5B为本申请实施例提供的一种沿图4B中B1-B2向的剖视图；
图6A为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图6B为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图6C为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图7为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图8为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图9A为本申请实施例提供的另一种芯片封装结构的俯视图；
图9B为本申请实施例提供的又一种芯片封装结构的俯视图；
图9C为本申请实施例提供的一种沿图9A中C1-C2向的剖视图；
图9D为本申请实施例提供的一种沿图9A中D1-D2向的剖视图；
图9E为本申请实施例提供的一种沿图9A中E1-E2向的剖视图；
图10A为本申请实施例提供的又一种芯片封装结构的俯视图；
图10B为本申请实施例提供的一种沿图10A中F1-F2向的剖视图；
图10C为本申请实施例提供的一种沿图10A中G1-G2向的剖视图；
图11A为本申请实施例提供的又一种芯片封装结构的俯视图；
图11B为本申请实施例提供的一种沿图11A中H1-H2向的剖视图；
图11C为本申请实施例提供的一种沿图11A中I1-I2向的剖视图；
图12A为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图12B为本申请实施例提供的又一种芯片封装结构的部分供电路径示意图；
图13A为本申请实施例提供的又一种芯片封装结构的俯视图；
图13B为本申请实施例提供的又一种芯片封装结构的俯视图；
图14A为本申请实施例提供的又一种芯片封装结构的俯视图；
图14B为本申请实施例提供的又一种芯片封装结构的俯视图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一搭接部分实施例，而不是全部的实施例。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“电性连接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“电性连接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“电性连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实 施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种电子设备，该电子设备可以为手机、电视、显示器、平板电脑、车载电脑等具有显示界面的终端设备，或者为智能手表、智能手环等智能显示穿戴设备，或者为服务器、存储器、基站等通信设备，或者为智能汽车等。本申请实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。
上述电子设备1还包括设置于PCB上的处理器(center processing unit，CPU)芯片、射频芯片、射频功率放大器((power amplifier，PA)芯片、系统级芯片(system on a chip，SOC)、电源管理芯片(power management integrated circuits，PMIC)、存储芯片(例如高带宽存储器(high bandwidth memory，HBM))、音频处理器芯片、触摸屏控制芯片、NAND flash(闪存)、图像传感器芯片等电子器件，PCB用于承载上述电子器件，并与上述电子器件完成信号交互。
随着电子技术的发展，电子设备1的功能不断的区域丰富化、全面化，使得高阶芯片演进迭代需求与日俱增，电子设备1中芯片的集成度持续增加，多芯片、高密度集成合封成为趋势。
基于此，为了提高电子设备1中芯片的集成度，本申请实施例提供一种芯片封装结构，如图2所示，芯片封装结构包括封装基板10，第一连接芯片21设置在封装基板10上，第一连接芯片21具有多个硅通孔(through silicon via，TSV)。导电柱30设置在封装基板10上，位于第一连接芯片21的外围。第一芯片41设置在导电柱30和第一连接芯片21上，与导电柱30和第一连接芯片21电性连接。第二芯片42设置在导电柱30和第一连接芯片21上，与导电柱30和第一连接芯片21电性连接。
如图2所示，在第一芯片41和第二芯片42被第一连接芯片21投影覆盖的区域中，第一芯片41和第二芯片42无法直接通过导电柱30来传输信号，而是通过第一连接芯片21中的硅通孔TSV来将封装基板10上的电源信号传输至第一芯片41和第二芯片42上。这就导致为了实现第一芯片41和第二芯片42被第一连接芯片21投影覆盖的区域中电源信号的传输，而增加了第一连接芯片21的结构复杂度和成本。
基于此，本申请实施例还提供一种芯片封装结构，如图3A所示，芯片封装结构包括：封装基板10、第一连接芯片21、多个导电柱30、第一芯片41、第二芯片42 以及重布线层50。
重布线层(也可以称为重新布线层或再布线层)(redistribution layer，RDL)50包括相对的第一表面和第二表面。
其中，重布线层50包括交替排布的金属层和绝缘层。金属层的材料例如可以包括铜、铝、镍、金、银、钛中的一种或多种导电材料。绝缘层的材料例如可以包括氧化硅、氮化硅、氮氧化硅、硅胶、聚酰亚胺中的一种或多种。
第一芯片41和第二芯片42并排设置在重布线层50的第一表面上，与重布线层50键合，第一芯片41和第二芯片42间存在间隔。
本申请实施例对第一芯片41和第二芯片42的具体结构不做限定，可以是电子设备所需要的任意芯片。例如，每个芯片都包括衬底以及设置在衬底上的功能层，功能层在工作过程中可以使得芯片实现其自身的功能，例如逻辑计算功能或者存储功能等。其中，功能层主要包括功能器件、电路结构、互连金属线以及电介质层等。
另外，本申请实施例芯片封装结构中的第一芯片41和第二芯片42可以是从晶圆上切割下来的裸芯片(或者称之为裸die、晶粒或颗粒)。也可以是对裸芯片进行封装后得到的封装后的芯片。当然，不限定为第一芯片41和第二芯片42需同为裸芯片或者同为封装后的芯片。也可以是第一芯片41为裸芯片(例如上述SOC)，第二芯片42为封装后的芯片(例如上述HBM)。
再者，将芯片封装结构中的第一芯片41和第二芯片42与重布线层16电性连接时，可以是一次一个芯片电性连接至重布线层16上，也可以是一次多个芯片电性连接至重布线层16上。
此外，第一芯片41和第二芯片42沿垂直于封装基板10方向上的厚度可以相同。第一芯片41和第二芯片42沿垂直于封装基板10方向上的厚度也可以不同，本申请实施例对此不做限定。
为了简化结构，便于电性连接。在一些实施例中，每个第一芯片41的有源面和每个第二芯片42的有源面均朝向基板10。其中，暴露在第一芯片41和第二芯片42的有源面的可以是焊盘(pad)，也可以是在焊盘上形成凸点(bump)结构，凸点结构例如可以是焊球凸点(ball bump)，或者铜柱凸点(Cu bump)等。
第一连接芯片21被设置在重布线层50的第二表面上，与重布线层50电性连接，第一连接芯片21位于重布线层50与封装基板10之间。
其中，第一连接芯片21的投影覆盖第一芯片41和第二芯片42的部分区域。
也就是说，第一芯片41的部分区域位于第一连接芯片21的正上方，第二芯片42的部分区域位于第一连接芯片21的正上方。或者理解为，第一芯片41的部分区域与第一连接芯片21搭接，第二芯片42的部分区域与第一连接芯片21搭接。第一芯片41和第二芯片42通过第一连接芯片21互连。
关于第一连接芯片21，例如，可以是根据需要在晶圆上直接做出需要的线路，然后切割后得到第一连接芯片21，应用于芯片封装结构中。例如可以将第一连接芯片21理解为桥接硅芯片(silicon bridge die，SBD)。当然，第一连接芯片21的衬底的材料例如可以包括硅(Si)、锗(Ge)、氮化镓(GaN)、砷化镓(GaAs)或其它半导体材料中的一种或多种。此外，衬底的材料例如还可以为玻璃(glass)、有机材料等。 桥接硅芯片仅为一种示意。
在一些实施例中，第一连接芯片21的有源面朝向重布线层50，与重布线层50电性连接。第一连接芯片21的背面设置在封装基板10上，与封装基板10固定连接。
在一些实施例中，第一连接芯片21的内部不设置TSV。
在这种情况下，在一些实施例中，第一连接芯片21的背面与封装基板10粘接。
示例的，通过芯片粘结膜(die attach film，DAF)将第一连接芯片21的背面与封装基板10粘接。或者，示例的，通过双面胶将第一连接芯片21的背面与封装基板10粘接。
在另一些实施例中，第一连接芯片21的内部设置有TSV。
在这种情况下，在一些实施例中，第一连接芯片21中的TSV在第一连接芯片21的背面与封装基板10电性连接。
示例的，通过熔融键合(fusion bonding)的方式或者粘合剂键合(adhesive bonding)的方式将第一连接芯片21中的TSV与基板10耦接。
其中，本申请实施例中，第一连接芯片21内部的TSV，不用于将封装基板10上的电源信号传输至第一芯片41和第二芯片42上，而是用于其他功能。其他功能，例如可以是将封装基板10上的电源信号传输至第一连接芯片21内，提高第一连接芯片21下方封装基板10上引脚的利用率。
重布线层50被多个导电柱30支撑于封装基板10上方，多个导电柱30设置在第一连接芯片21的外围，多个导电柱30与封装基板10和重布线层50分别电性连接，以实现将封装基板10上的信号传输至重布线层50中。
导电柱30的材料例如可以包括钛(Ti)、铜(Cu)、镍(Ni)、钴(Co)、钨(W)或相关合金中的一种或多种。
关于实现导电柱30与封装基板10电性连接的方式，在一些实施例中，如图3A所示，导电柱30与封装基板10通过可控塌陷芯片连接凸块(controlled collapse chip connection bump，C4 bump)或者焊球焊接。
在另一些实施例中，如图3B所示，导电柱30与封装基板10之间还设置有第二重布线层90，第二重布线层90与封装基板10通过C4 bump或者焊球焊接。
其中，第二重布线层90中可以仅包括单层金属层，也可以包括多层金属层，本申请实施例对此不做限定。
当然，实现导电柱30与封装基板10电性连接的方式，还可以是其他方式，本申请实施例对此不做限定。
在一些实施例中，芯片封装结构还包括第一塑封层60，第一塑封层60包裹第一连接芯片21和导电柱30的侧面，露出第一连接芯片21的有源面和导电柱30的顶面，对第一连接芯片21和导电柱30起到保护作用。
第一塑封层60的材料，例如可以是塑封料(molding)、环氧树脂胶粘剂(epoxy molding compound，EMC)或者绝缘材料等。
在一些实施例中，芯片封装结构还包括第二塑封层70，第二塑封层至少包裹第一芯片41的侧面和第二芯片42的侧面，对第一芯片41和第二芯片42起到保护作用。
在一些实施例中，如图3A和图3B所示，芯片封装结构还包括填充在C4 bump 或者焊球外围的底部填充层80。
如图3A所示，底部填充层80位于第一塑封层60与封装基板10之间。或者，如图3B所示，底部填充层80位于第二重布线层90与封装基板10之间。
例如，可以采用毛细底填料(capillary underfill，CUF)工艺、模塑底填料(mold underfill，MUF)工艺、非导电膜(non-conductive film，NCF)工艺或非导电浆料(non-conductive paste，NCP)工艺中的任意一种工艺形成底部填充层80。
在一些实施例中，芯片封装结构还包括压环(ring)、散热盖、或者第三塑封层中的至少一种。
压环设置在封装基板10的表面上，位于第一塑封层60的外围。
散热盖与封装基板10对合连接，第一连接芯片21、导电柱30、第一芯片41、第二芯片42、第一塑封层60、第二塑封层70以及底部填充层80均位于散热盖与封装基板10对合形成的容纳腔内。
第三塑封层至少包裹第一塑封层60、第二塑封层70以及底部填充层80的侧面。第三塑封层还可以覆盖第二塑封层70、第一芯片41和第二芯片42的顶面。
其中，图3A以芯片封装结构包括第三塑封层为例进行示意，图3B以芯片封装结构包括散热盖为例进行示意。
需要说明的是，上述仅是示意了芯片封装结构中一组第一芯片41和第二芯片42通过第一连接芯片21互连，芯片封装结构中可以具有多个包括第一芯片41、第二芯片42以及第一连接芯片21的单元组。
本申请实施例提供的芯片封装结构，通过第一连接芯片21将第一芯片41和第二芯片42互连，相比于在封装基板10上做连接走线的方式，第一连接芯片21的集成度更高，使得得到的芯片封装结构的集成度更高，可适用于超高集成度高性能计算(high performance computing，HPC)封装。
下面，对实现上述芯片封装结构中电源供电的方法进行示例说明。
示例一
如图4A所示，第一芯片41和第二芯片42的底部上设有多个第一触点43和多个第二触点44。
第一触点43分布于第一芯片41和第二芯片42的底部被第一连接芯片21投影覆盖的区域。也就是说，第一触点43分布于第一芯片41和第二芯片42的位于第一连接芯片21正上方，与第一连接芯片21交叠的区域。
第二触点44分布于第一芯片41和第二芯片42的底部未被第一连接芯片21投影覆盖的区域。也就是说，第二触点44分布于第一芯片41和第二芯片42未与第一连接芯片21交叠的区域。
其中，第一触点43和第二触点44可以是焊盘、焊球、导电柱等导电结构。
重布线层60中设置有第一线路路径1，第一线路路径1用于将多个导电柱30中的部分导电柱30与第一触点43电性连接。以实现封装基板10上的电源信号经导电柱30传输至第一线路路径1，然后经第一线路路径1传输至第一芯片41和第二芯片42底部的第一触点43，然后再传输至第一芯片41和第二芯片42被第一连接芯片21投影覆盖的区域的内部。
重布线层60中还设置有第二线路路径2，第二线路路径2用于将多个导电柱30中的部分导电柱30与第二触点44电性连接。以实现封装基板10上的电源信号经导电柱30传输至第二线路路径2，然后经第二线路路径2传输至第一芯片41和第二芯片42底部的第二触点44，然后再传输至第一芯片41和第二芯片42未被第一连接芯片21投影覆盖的区域的内部。
其中，不对第一线路路径1传输的信号的类型进行限定。例如，部分第一线路路径1可以用于传输知识产权(intellectual property，IP)电源信号，向第一芯片41和第二芯片42内部的IP单元供电。部分第一线路路径1可以用于传输地(ground)信号，实现第一芯片41和第二芯片42的电源和信号的回流。
同理，不对第二线路路径2传输的信号的类型进行限定。例如，部分第二线路路径2可以用于传输IP电源信号，部分第二线路路径2可以用于传输地信号。部分第二线路路径2还可以用于传输核心(core)电源信号，向第一芯片41和第二芯片42的core单元供电。
另外，第一线路路径1和第二线路路径2可通过调整重布线层50中的金属层的层数和每层金属层的图案来实现，具体的路径不做限定，能够实现第一线路路径1和第二线路路径2的供电效果即可。
基于此，如图4B所示，芯片封装结构中多个导电柱30可以包括多个IP电源导电柱31、多个core电源导电柱33以及多个地导电柱32。
多个IP电源导电柱31、多个core电源导电柱33以及多个地导电柱32分布在重布线层60限定出的区域内，部分导电柱30位于第一芯片41和第二芯片42的下方，部分导电柱30位于第一芯片41和第二芯片42的外围。
芯片封装结构中的多个第一触点43包括第一IP电源触点431以及第一地触点432。
其中，第一芯片41的被第一连接芯片21投影覆盖的区域(本申请实施例中称之为第一覆盖区域)M1分布有第一IP电源触点431以及第一地触点432，第二芯片42的被第一连接芯片21投影覆盖的区域(本申请实施例中称之为第二覆盖区域)N1也分布有第一IP电源触点431以及第一地触点432。
芯片封装结构中的多个第二触点44包括第二IP电源触点441、第二地触点442以及core电源触点443。
其中，第一芯片41的未被第一连接芯片21投影覆盖的区域(本申请实施例中称之为第一未覆盖区域)M2分布有第二IP电源触点441、第二地触点442以及core电源触点443，第二芯片42的未被第一连接芯片21投影覆盖的区域(本申请实施例中称之为第二未覆盖区域)N2也分布有第二IP电源触点441、第二地触点442以及core电源触点443。
以图4A所示的导电柱30为IP电源导电柱31，第一触点43为第一IP电源触点431，第二触点44为第二IP电源触点441为例进行说明。
结合图4A和图4B来看，多个IP电源导电柱31中的部分IP电源导电柱31与第一线路路径1电性连接，将封装基板10上的IP电源信号经IP电源导电柱31传输至第一线路路径1。第一线路路径1与第一IP电源触点431电性连接，左侧的第一线路路径1将IP电源信号传输至第一芯片41的第一IP电源触点431中，然后传输至第一 芯片41的第一覆盖区域M1中。右侧的第一线路路径1将IP电源信号传输至第二芯片42的第一IP电源触点431中，然后传输至第二芯片42的第二覆盖区域N1中。
多个IP电源导电柱31中的部分IP电源导电柱31与第二线路路径2电性连接，将封装基板10上的IP电源信号经IP电源导电柱31传输至第二线路路径2。第二线路路径2与第二IP电源触点441电性连接，左侧的第二线路路径2将IP电源信号传输至第一芯片41的第二IP电源触点441中，然后传输至第一芯片41的第一未覆盖区域M2中。右侧的第二线路路径2将IP电源信号传输至第二芯片42的第二IP电源触点441中，然后传输至第二芯片42的第二未覆盖区域N2中。
同理，以图4A所示的导电柱30为地导电柱32，第一触点43为第一地触点432，第二触点44为第二地触点442为例进行说明。
结合图4A和图4B来看，多个地导电柱32中的部分地导电柱32与第一线路路径1电性连接，该部分地导电柱32通过第一线路路径1与第一地触点432电性连接。以实现封装基板10上的地信号经左侧的地导电柱32传输至左侧的第一线路路径1。左侧的第一线路路径1将地信号传输至第一芯片41的第一地触点432中，然后传输至第一芯片41的第一覆盖区域M1中。封装基板10上的地信号经右侧的地导电柱32传输至右侧的第一线路路径1。右侧的第一线路路径1将地信号传输至第二芯片42的第一地触点432中，然后传输至第二芯片42的第二覆盖区域N1中。
多个地导电柱32中的部分地导电柱32与第二线路路径2电性连接，该部分地导电柱32通过第二线路路径2与第二地触点442电性连接。以实现封装基板10上的地信号经左侧的地导电柱32传输至左侧的第二线路路径2。左侧的第二线路路径2将地信号传输至第一芯片41的第二地触点442中，然后传输至第一芯片41的第一未覆盖区域M2中。封装基板10上的地信号经右侧的地导电柱32传输至右侧的第二线路路径2。右侧的第二线路路径2将地信号传输至第二芯片42的第二地触点442中，然后传输至第二芯片42的第二未覆盖区域N2中。
如图4C所示，以导电柱30为core电源导电柱33，第二触点44为core电源触点443为例进行说明。
结合图4B和图4C来看，多个core电源导电柱33与第二线路路径2电性连接，core电源导电柱33通过第二线路路径2与core电源触点443电性连接。以实现封装基板10上的core电源信号经左侧的core电源导电柱33传输至左侧的第二线路路径2。左侧的第二线路路径2将core电源信号传输至第一芯片41的core电源触点443中，然后传输至第一芯片41的第一未覆盖区域M2中。封装基板10上的core电源信号经右侧的core电源导电柱33传输至右侧的第二线路路径2。右侧的第二线路路径2将core电源信号传输至第二芯片42的core电源触点443中，然后传输至第二芯片42的第二未覆盖区域N2中。
应当明白的是，上述从图4A和图4C所示的截面图来看，第一连接芯片21的左右两边具有第一线路路径1和第二线路路径2。但从图4B所示的俯视图上来看，第一连接芯片21的上、下、左以及右四周都可以设置有第一线路路径1和第二线路路径2。也就是说，第一连接芯片21四周的导电柱30都可以通过第一线路路径1和/或第二线路路径2向第一芯片41和第二芯片42传输信号。
例如，如图4B所示，位于第一连接芯片21下方的IP电源导电柱31可以通过第一线路路径1将IP电源信号传输至第一芯片41和第二芯片42中。
另外，如图4A所示，本申请实施例中，并不限定为左侧的导电柱30仅能通过第一线路路径1向左侧的第一芯片41传输电源信号。左侧的导电柱30也可以通过第一线路路径1向右侧的第一芯片41传输电源信号。同理，右侧的导电柱30也可以通过第一线路路径1向左侧的第一芯片41传输电源信号。
在一些实施例中，考虑到线路越短，损耗和电阻越小，因此，在选择与第一线路路径1和第二线路路径2相连接的导电柱30时，可采取就近原则。
如图5A(沿图4B中A1-A2向的剖视图)所示，第一连接芯片21朝向重布线层50的一侧还设有多个第一辅助触点210，第一辅助触点210与第一触点43对应设置。
其中，第一辅助触点210与第一触点43对应设置，可以理解为，第一触点43的投影与第一辅助触点210交叠。也就是说，第一触点43位于第一辅助触点210的上方。
即，在第一连接芯片21的与第一芯片41的第一交叠区域M1重合的第一重合区域L1设置有第一辅助触点210。在在第一连接芯片21的与第二芯片42的第一交叠区域N1重合的第二重合区域L2也设置有第一辅助触点210。
在一些实施例中，第一触点43包括第一IP电源触点431以及第一地触点432。对应的，第一辅助触点210包括第一辅助IP电源触点211以及第一辅助地触点212。
如图5A所示，第一辅助IP电源触点211与第一IP电源触点431对应设置。如图5B(沿图4B中B1-B2向的剖视图)所示，第一辅助地触点212与第一地触点432对应设置。
在一些实施例中，如图6A所示，重布线层50还包括第三线路路径3，第三线路路径3用于将多个导电柱30中的部分导电柱30与第一辅助触点210电性连接。
以实现封装基板10上的电源信号经导电柱30传输至第三线路路径3，然后经第三线路路径3传输至第一辅助触点210，然后根据需要再传输至第一连接芯片21的内部。
其中，不对第三线路路径3传输的信号的类型进行限定。例如，部分第三线路路径3可以用于传输IP电源信号，部分第三线路路径3可以用于传输地信号。
在一些实施例中，如图6A所示，第一线路路径1与第三线路路径3不重合。
在另一些实施例中，如图6B所示，第一线路路径1与第三线路路径3部分重合。
在又一些实施例中，如图6C所示，第一线路路径1与第三线路路径3基本完全重合，在靠近第一触点43和第一辅助触点210的位置处，分开传输，分别传输至重布线层50上方的第一触点43和重布线层50下方第一辅助触点210中。
在这种情况下，图4B中的第一线路路径1也可以看做是第三线路路径3。
基于此，结合图5A和图6C来看，多个IP电源导电柱31中的部分IP电源导电柱31与第三线路路径3电性连接，将封装基板10上的IP电源信号经IP电源导电柱31传输至第三线路路径3。第三线路路径3与第一辅助IP电源触点211电性连接，左侧的第三线路路径3将IP电源信号传输至第一重合区域L1中的第一辅助IP电源触点211。右侧的第三线路路径3将IP电源信号传输第二重合区域L2中的第一辅助IP电源触点211。
多个第一电源触点211根据需要，可以在第一连接芯片21内部电性连接，也可以不电性连接。在多个第一电源触点211在需要在第一连接芯片21内部电性连接的情况下，例如可以通过第一连接芯片21内部的金属层P1实现电性连接。也就是说，金属层P1作为实现第一电源触点211互连的网络平面。
其中，金属层P1，例如可以是第一连接芯片21的焊盘层。第一辅助触点210例如可以设置在金属层P1上，金属层P1通过金属层之间的过孔(via)实现与金属层的连接。
结合图5B和图6C来看，多个地导电柱32中的部分地导电柱32与第三线路路径3电性连接，将封装基板10上的地信号经地导电柱32传输至第三线路路径3。第三线路路径3与第一辅助地触点212电性连接，左侧的第三线路路径3将地信号传输至第一重合区域L1中的第一辅助地触点212。右侧的第三线路路径3将地信号传输第二重合区域L2中的第一辅助地触点212。
多个第一辅助地触点212，例如可以通过第一连接芯片21内部的金属层P2可以实现电性连接。
应当明白的是，上述从图6A-图6C所示的截面图来看，第一连接芯片21的左右两边具有第三线路路径3。但实际上第一连接芯片21的上、下、左以及右四周都可以设置有第三线路路径3，根据需要合理设置即可。
在一些实施例中，如图5A所示，第一芯片41和第二芯片42还包括第三触点45，第三触点45分布于第一芯片41的底部被第一连接芯片21投影覆盖的区域(第一覆盖区域M1)和第二芯片42的底部被第一连接芯片21投影覆盖的区域(第二覆盖区域N1)。
如图5A所示，第一连接芯片21还包括第三辅助触点213，第三辅助触点213与第三触点45对应分布。即，第三触点45的投影与第三辅助触点213交叠。也就是说，第一连接芯片21的第一重合区域L1中分布有与第一覆盖区域M1中的第三触点45对应的第三辅助触点213，第一连接芯片21的第二重合区域L2中分布有与第二覆盖区域N1中的第三触点45对应的第三辅助触点213。
其中，第一重合区域L1中的第三辅助触点213和第二重合区域L2中的第三辅助触点213在第一连接芯片21内部电性连接。例如，第一重合区域L1中的第三辅助触点213和第二重合区域L2中的第三辅助触点213通过第一连接芯片21内部的金属层P3实现电性连接。金属层P3的数量可以是一层，也可以是多层，根据需要合理设置即可。
在一些实施例中，如图5A所示，为了使用于传输地信号的金属层P2能够起到降噪隔离作用，相邻金属层P3之间可以设置有一层金属层P2。当然，根据金属层的设计，每层金属层中也可以有部分图案用于传输地信号。并不限定每层金属层只能传输一种信号。
可以理解的是，图5A中虽然部分第三辅助触点213未电性连接，但并不表示其不电性连接，仅是该部分第三辅助触点213在B1-B2截面处未电性连接，该部分第三辅助触点213在其他截面处可实现电性连接。
如图7所示，重布线层50还包括第八线路路径8；第八线路路径8用于将第三触 点45与第三辅助触点213电性连接。以实现第一芯片41上的互连信号经第三触点45传输至第八线路路径8后传输至第一重合区域L1中的第三辅助触点213，然后在第一连接芯片21内部传输至第二重合区域L2中的第三辅助触点213，再经第八线路路径8传输至第二芯片42上的第三触点45，随后传输至第二芯片42内部，以实现第一芯片41和第二芯片42的互连。
图7所示的芯片封装结构的电源供电路径包括：
第一条路径：部分导电柱30将封装基板10中的电源信号经第一线路路径1传输至第一芯片21的第一覆盖区域M1，部分导电柱30将封装基板10中的电源信号经第二线路路径2传输至第一芯片41的第一未覆盖区域M2。实现从封装基板10经导电柱30和重布线层50上的第一线路路径1和第二线路路径2向第一芯片41的供电。
第二条路径：部分导电柱30将封装基板10中的电源信号经第一线路路径1传输至第二芯片22的第二覆盖区域N1，部分导电柱30将封装基板10中的电源信号经第二线路路径2传输至第二芯片42的第二未覆盖区域N2。实现从封装基板10经导电柱30和重布线层50上的第一线路路径1和第二线路路径2向第二芯片42的供电。
第三条路径：部分导电柱30将封装基板10中的电源信号经第三线路路径3传输至第一连接芯片21的第一重合区域L1，部分导电柱30将封装基板10中的电源信号经第三线路路径3传输至第一连接芯片21的第二重合区域L2，实现从封装基板10经导电柱30和重布线层50上的第三线路路径3向第一连接芯片21的供电。
实现第一芯片41和第二芯片42互连的路径：第一芯片41内的互连信号经第八供电路径8传输至第一连接芯片21的第一重合区域L1，互连信号在第一连接芯片21内部从第一重合区域L1传输至第二重合区域L2，互连信号再从第二重合区域L2经第八供电路径8传输至第二芯片42，从而实现第一芯片41与第二芯片42的互连。
在一些实施例中，至少部分第一辅助触点210在第一连接芯片21内部电性连接。
其中，在第一连接芯片21内部电性连接的第一辅助触点210可以包括用于传输地信号的第一辅助地触点212，也可以包括用于传输IP电源信号的第一电源辅助触点211。
如图8所示，重布线层50还包括第四线路路径4，第四线路路径4用于将第二芯片42底部的第一触点43，与，第一连接芯片21对应位置处(第二重合区域L2)的第一辅助触点210电性连接。
以实现第一辅助触点210接收的电源信号经第四线路路径4传输至第二芯片42上的第一触点43，随后传输至第二芯片42内部。
在一些实施例中，经过第四线路路径4电性连接的第一辅助触点210为第一电源辅助触点211，第一触点43为第一IP电源触点431。
基于此，如图8所示，在图7所示的电源供电路径的基础上，芯片封装结构的电源供电路径还包括：
第四条供电路径：部分导电柱30将封装基板10中的电源信号经第三线路路径3传输至第一连接芯片21的第一重合区域L1，电源信号在第一连接芯片21的内部经第一重合区域L1传输至第二重合区域L2，电源信号在第二重合区域L2经第四线路路径4传输至第二芯片42的第二覆盖区域N1，随后传输至第二芯片42内。实现从封装基板10经第一芯片41侧的导电柱30和重布线层50上的第三线路路径3到第一连接芯 片21，然后从第一连接芯片21经重布线层50上的第四线路路径4向第二芯片42的供电。
应当明白的是，重布线层50上的第四线路路径4与第八线路路径8的不同之处在于，第四线路路径4是用于向第二芯片42传输电源信号，第八线路路径8是用于传输第一芯片41和第二芯片42之间的互连信号。
本申请实施例通过在重布线层50中设置第四线路路径4，可将靠近第一芯片41的导电柱30中的电源信号经第一连接芯片21传输至第二芯片42中。这样一来，在第二芯片42的供电需求较大，而第二芯片42所在侧用于设置导电柱30的空间又不够时，通过第一芯片41所在侧的导电柱30向第二芯片42供电，可满足第二芯片42的供电需求。
需要说明的是，图4B中示意了芯片封装结构的俯视图，俯视图中示意了一种多个导电柱30(包括IP电源导电柱31、地导电柱32以及core电源导电柱33)的排布和第一触点43(第一IP电源触点431和第一地触点432)以及第二触点44(第二IP电源触点441、第二地触点442以及core电源触点443)的排布方式，但图中仅为一种示意，不做任何限定，每行的排布顺序也可以调换。
导电柱30和第一触点43以及第二触点44的排布方式还可以如图9A和图9B所示，本申请实施例对此不做限定。
关于导电柱30的排布，在一些实施例中，多个导电柱30沿第一方向X和第二方向Y排布成多行多列，本申请实施例中，从图9A的视角来看，将位于第一芯片41和第二芯片42边缘(图中的点划线)上方和下方的导电柱30排布成多行，将位于第一芯片41和第二芯片42边缘左侧和右侧的导电柱30排布成多列。其中，相邻行导电柱30错位排布，相邻列导电柱30错位排布。
在一些实施例中，IP电源导电柱31相对core电源导电柱33靠近第一连接芯片21设置。
在一些实施例中，相邻行地导电柱32之间设置有一行电源导电柱。其中，一行电源导电柱可以是包括IP电源导电柱31；一行电源导电柱也可以是包括core电源导电柱33；一行电源导电柱也可以是即包括IP电源导电柱31，又包括core电源导电柱33。
在一些实施例中，最靠近第一连接芯片21的一行导电柱30为一行IP电源导电柱31或者一行地导电柱32。最靠近第一连接芯片21的一列导电柱30为一列IP电源导电柱31或者一列地导电柱32。
关于第二触点44的排布，在一些实施例中，第二触点44与位于第一芯片41和第二芯片42下方的导电柱30对应设置。第二触点44位于与其对应设置的导电柱30的外围。
也就是说，如图9C(沿图9A中C1-C2向的剖视图)所示，与IP电源导电柱31对应设置的第二触点44为第二IP电源触点441，一个IP电源导电柱31可以对应设置至少一个第二IP电源触点441。在一个IP电源导电柱31可以对应设置有多个第二IP电源触点441的情况下，如图9A所示，多个第二IP电源触点441的投影位于与其对应设置的IP电源导电柱31的外围，以增强导电通路。
同理，如图9C所示，与core电源导电柱33对应设置的第二触点44为core电源 触点443。一个core电源导电柱33可以对应设置至少一个core电源触点443。在一个core电源导电柱33可以对应设置有多个core电源触点443的情况下，如图9A所示，多个core电源触点443的投影位于与其对应设置的core电源导电柱33的外围。
同理，如图9D所示，与地导电柱32对应设置的第二触点44为第二地触点442。一个地导电柱32可以对应设置至少一个第二地触点442。在一个地导电柱32可以对应设置有多个第二地触点442的情况下，如图9A所示，多个第二地触点442的投影位于与其对应设置的core电源导电柱33的外围。
关于第一覆盖区M1和第二覆盖区N1中触点的排布，在一些实施例中，如图9A所示，将多个第一触点43沿第二方向Y排布成多行，每行中的多个第一触点43沿第一方向X依次排布。将多个第三触点45沿第二方向Y排布成多行，每行中的多个第三触点45沿第一方向X依次排布。
按至少一行第一IP电源触点431、至少一行第三触点45、至少一行第一地触点432、至少一行第三触点45为一个循环单元，沿第二方向Y循环排布。
可选的，如图9A所示，相邻行中的触点错位排布。
可选的，如图9A所示，与每行第一IP电源触点431相邻的导电柱30为IP电源导电柱31，与每行第一地触点432相邻的导电柱30为地导电柱32。
在另一些实施例中，如图9B所示，将多个第一触点43沿第一方向X排布成多列，每列中的多个第一触点43沿第二方向Y依次排布。将多个第三触点45沿第一方向X排布成多列，每列中的多个第三触点45沿第二方向Y依次排布。
按至少一列第一IP电源触点431、至少一列第三触点45、至少一列第一地触点432、至少一列第三触点45为一个循环单元，沿第一方向X循环排布。
可选的，如图9B所示，相邻列中的触点错位排布。
可选的，如图9B所示，最靠近导电柱30的一列第一触点43为第一IP电源触点431。
在又一些实施例中，如图4B所示，将多个第一触点43沿第一方向X排布成多列，每列中的多个第一触点43沿第二方向Y依次排布。将多个第三触点45沿第一方向X排布成多列，每列中的多个第三触点45沿第二方向Y依次排布。
按至少一列第一触点43和至少一列第三触点45沿第一方向X交替排布的规律设置。其中，每列第一触点43由第一IP电源触点431和第一地触点432交替排布构成。
可选的，最靠近导电柱30的一列第一触点43中，与第一IP电源触点431相邻的导电柱30为IP电源导电柱31，与第一地触点432相邻的导电柱30为地导电柱32。
关于第一连接芯片21上触点的分布，在一些实施例中，如图9C所示，第一辅助触点210中的第一辅助IP电源触点211与第一芯片41和第二芯片42中的第一IP电源触点431对应设置。
在一些实施例中，如图9D所示，第一辅助触点210中的第一辅助地触点212与第一芯片41和第二芯片42中的第一地触点一432对应设置。
在一些实施例中，如图9E所示，第三辅助触点213与第一芯片41和第二芯片42中的第三触点45对应设置。
也就是说，第一连接芯片21的第一重合区域L1中触点的排布规律，与第一芯片 41的第一交叠区域M1中触点的排布规律相同。第一连接芯片21的第二重合区域L2中触点的排布规律，与第二芯片42的第二交叠区域N1中触点的排布规律相同。
本申请实施例提供的芯片封装结构，封装基板10通过C4 bump或者焊球与导电柱30焊接，将封装基板10上的信号传输至导电柱30上。导电柱30排布在第一连接芯片21的外围，与重布线层50电性连接。导电柱30上的信号经重布线层50上的线路路径传输至第一连接芯片21、第一芯片41以及第二芯片42，为第一连接芯片21、第一芯片41以及第二芯片42供电。相比采用在第一连接芯片21中形成TSV的供电方式，本申请实施例采用的供电方式，在保证芯片封装结构内部电路的供电需求的基础上，可降低成本。相比采用没有连接芯片，而是采用重布线层实现第一芯片41和第二芯片42的互连和供电的方式，本申请实施例采用的供电方式可减少重布线层50中金属层的层数，减薄重布线层50的厚度。
另外，由于第一连接芯片21中无需为了传输封装基板上的电源信号而形成TSV，可缩小第一连接芯片21的面积，有助于实现第一芯片和第二芯片间短距离高密度的互连，从而满足大带宽、高速率、高性能且低成本芯片的需求。
示例二
示例二与示例一的不同之处在于，第一连接芯片21在第一重合区域L1和第二重合区域L2之间还设置有第二辅助触点。
如图10A所示，第一连接芯片21朝向重布线层50的一侧还设有多个第二辅助触点214，第二辅助触点214分布于第一连接芯片21未被第一芯片41和第二芯片42投影覆盖的区域。
如图10B(沿图10A中F1-F2向的剖视图)和图10C(沿图10A中G1-G2向的剖视图)所示，在一些实施例中，第二辅助触点214分布于第一重合区域L1和第二重合区域L2之间。也就是，第二辅助触点214分布于第一芯片41和第二芯片42的间隙的下方。
其中，根据需要，第二辅助触点214可全部为第二辅助IP电源触点215；或者，第二辅助触点214全部为第二辅助地触点216；或者，如图10A所示，第二辅助触点214部分为第二辅助IP电源触点215，部分为第二辅助地触点216。
如图10A和图11A所示，根据第一芯片41和第二芯片42中第一触点43和第三触点45的排布方式的不同，第二辅助触点214的排布方式也可以对应调整。
在一些实施例中，如图10B和图11B(沿图11A中H1-H2向的剖视图)所示，第一辅助IP电源触点211和第二辅助IP电源触点215同行设置。
在一些实施例中，如图10C和图11C(沿图11A中I1-I2向的剖视图)所示，第一辅助地触点212和第二辅助地触点216同行设置。
通过在第一连接芯片21的第一重合区域L1和第二重合区域L2之间设置第二辅助触点214，第二辅助触点214与重布线层50连接，相当于通过第二辅助触点214来增加了支撑点，以提高对第一芯片41和第二芯片42间隙处的支撑强度，避免芯片封装结构在第一芯片41和第二芯片42的间隙处断裂。
在一些实施例中，至少部分第二辅助触点214与部分第一辅助触点210电性连接。
例如，可以通过第一连接芯片21内部的金属层实现第一辅助触点210和第二辅助 触点214的电性连接。
或者，例如可以通过重布线层50上的线路路径电性连接。
应当明白的是，第二辅助触点214与第一辅助触点210电性连接。也就是说，第一辅助触点210中的第一辅助IP电源触点211和第二辅助触点214中的第二辅助IP电源触点215电性连接，用于传输第一电源信号。第一辅助触点210中的第一辅助地触点212和第二辅助触点214中的第二辅助地触点216电性连接，用于传输地信号。
如图10A和图11A所示，重布线层50还包括第五线路路径5。第五线路路径5用于将多个导电柱30中的部分导电柱30与第二辅助触点214电性连接。
例如，IP电源导电柱31通过第五线路路径5与第二辅助IP电源触点215电性连接。地导电柱32通过第五线路路径5与第二辅助地触点216电性连接。
这样一来，芯片封装结构可增加两条供电路径：
第五条路径：部分导电柱30将封装基板10中的电源信号经第五线路路径5传输至第二辅助触点214，电源信号经第一连接芯片21内部传输至第一连接芯片21的第一重合区域L1和第二重合区域L2。实现从封装基板10经导电柱30和重布线层50上的第五线路路径5向第一连接芯片21的供电。
第六条路径：部分导电柱30将封装基板10中的电源信号经第五线路路径5传输至第二辅助触点214，随后传输第一连接芯片21后，部分电源信号还可以在第二重合区域L2经第四线路路径4传输至第二芯片42。实现从封装基板10经导电柱30和重布线层50上的第五线路路径5到第一连接芯片21，然后再经过重布线层50上的第四线路路径4向第二芯片42供电。
在一些实施例中，如图10A、图11A以及图12A所示，重布线层50还包括第六线路路径6。第六线路路径6用于将第一芯片41底部的第一触点43，与，第一连接芯片21对应位置处(第一重合区域L1)的第一辅助触点210电性连接。
这样一来，芯片封装结构可增加一条供电路径：
第七条路径：部分导电柱30将封装基板10中的电源信号经第五线路路径5传输至第二辅助触点214，随后传输第一连接芯片21后，部分电源信号还可以在第一重合区域L1经第六线路路径6传输至第一芯片41。实现从封装基板10经导电柱30和重布线层50上的第五线路路径5到第一连接芯片21，然后再经过重布线层50上的第六线路路径6向第一芯片41供电。
应当明白的是，重布线层50上的第六线路路径6与第八线路路径8的不同之处在于，第六线路路径6是用于向第一芯片41传输电源信号，第八线路路径8是用于传输第一芯片41和第二芯片42之间的互连信号。
根据需要，在一些实施例中，如图11A和图12B所示，重布线层50还包括第七线路路径7。第七线路路径7用于将至少部分第二辅助触点214电性连接。
在另一些实施例中，至少部分第二辅助触点214在第一连接芯片21内部电性连接。
通过在第一重合区域L1和第二重合区域L2之间设置第二辅助触点214，一方面，可以对重布线层50起到支撑作用，均衡重布线层50上的受力。另一方面，可以在重布线层50上增加线路路径，实现封装基板10上的信号从外围导电柱30到第一重合区域L1和第二重合区域L2之间，再到第一连接芯片21或者第一芯片41或者第二芯片 42内部，可丰富第一连接芯片21的电源网络和地网络，加强对芯片封装结构内部的供电和回流。
示例三
示例三与示例一和示例二的不同之处在于，芯片封装结构还包括第二连接芯片。
如图13A所示，芯片封装结构还包括第二连接芯片22，第二连接芯片22与第一连接芯片21并排设置在重布线层50的第二表面上。
其中，第二连接芯片22的投影覆盖第一芯片41和第二芯片42的部分区域。也就是说，第一芯片41的部分区域位于第二连接芯片22的正上方，第二芯片42的部分区域位于第二连接芯片22的正上方。或者理解为，第一芯片41的部分区域与第二连接芯片22搭接，第二芯片42的部分区域与第二连接芯片22搭接。第一芯片41和第二芯片42通过第二连接芯片22互连。
也就是说，如图13A所示，第一芯片41和第二芯片42的部分功能区通过第一连接芯片21互连，第一芯片41和第二芯片42的部分功能区通过第二连接芯片22互连。
当然，第一芯片41和第二芯片42可以通过多个连接芯片互连，本申请实施例提供的芯片封装结构对连接芯片的数量不做限定，根据需要合理设置即可。
另外，如图13A所示，第一连接芯片21和第二连接芯片22之间可以设置导电柱30。如图13B所示，第一连接芯片21和第二连接芯片22之间也可以不设置导电柱30。
第二连接芯片22的结构，可以和第一连接芯片21的相同，与第一芯片41和第二芯片42对应设置即可。
在第一芯片41和第二芯片42互连区域较大，或者多组需要互连的功能区相隔较远的情况下，设置多个互连芯片可减小线路路径，提高互连后的性能。满足不同结构需求。
示例四
示例四与示例一至示例三的不同之处在于：芯片封装结构还包括第三芯片。
如图14A所示，芯片封装结构还包括第三芯片43。
第三芯片43设置在重布线层50的第一表面上，与第一芯片41和第二芯片42间存在间隔；第三芯片43的部分区域被第一连接芯片21的投影覆盖。
第三芯片43的结构和设计，可参考上述第一芯片41和第二芯片42的结构。第三芯片43可以通过第一连接芯片21与第一芯片41互连，第三芯片43还可以通过第一连接芯片21与第二芯片42互连，第三芯片43还可以通过第一连接芯片21与第一芯片41和第二芯片42均互连。
其中，第三芯片43的供电路径，可以参考上述对第一芯片41和第二芯片42的供电路径的描述。
当然，本申请实施例对通过第一连接芯片21互连的芯片的数量不做限定，可以是两个，可以是图14A所示的三个，也可以是图14B所示的四个(还包括第四芯片44)，还可以是更多个，根据需要合理设置即可。
本申请实施例提供的芯片封装结构，设计灵活，适用性强。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换， 都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种芯片封装结构，其特征在于，包括：第一芯片、第二芯片、第一连接芯片、重布线层、多个导电柱以及封装基板；
    所述重布线层包括相对的第一表面和第二表面，
    所述第一芯片和第二芯片并排设置在所述重布线层的所述第一表面上，所述第一芯片和第二芯片间存在间隔，
    所述第一连接芯片被设置在所述重布线层的所述第二表面上，
    所述第一芯片和第二芯片的底部上设有多个第一触点和多个第二触点，所述第一触点分布于所述第一芯片和第二芯片的底部被所述第一连接芯片投影覆盖的区域，所述第二触点分布于所述第一芯片和第二芯片的底部未被所述第一连接芯片投影覆盖的区域，
    所述重布线层被所述多个导电柱支撑于所述封装基板上方，所述多个导电柱设置在所述第一连接芯片的外围，
    所述重布线层中设置有第一线路路径和第二线路路径，所述第一线路路径用于将所述多个导电柱中的部分导电柱与所述第一触点电性连接；所述第二线路路径用于将所述多个导电柱中的部分导电柱与所述第二触点电性连接。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述第一连接芯片朝向所述重布线层的一侧还设有多个第一辅助触点，所述第一辅助触点与所述第一触点对应设置；
    所述重布线层还包括第三线路路径，所述第三线路路径用于将所述多个导电柱中的部分导电柱与所述第一辅助触点电性连接。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，至少部分所述第一辅助触点在所述第一连接芯片内部电性连接；
    所述重布线层还包括第四线路路径，所述第四线路路径用于将所述第二芯片底部的所述第一触点，与，所述第一连接芯片对应位置处的所述第一辅助触点电性连接。
  4. 根据权利要求1-3任一项所述的芯片封装结构，其特征在于，所述第一连接芯片朝向所述重布线层的一侧还设有多个第二辅助触点，所述第二辅助触点分布于所述第一连接芯片未被所述第一芯片和所述第二芯片投影覆盖的区域。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，至少部分所述第二辅助触点与部分第一辅助触点在所述第一连接芯片内部电性连接；
    所述重布线层还包括第五线路路径，所述第五线路路径用于将所述多个导电柱中的部分导电柱与所述第二辅助触点电性连接。
  6. 根据权利要求5所述的芯片封装结构，其特征在于，所述重布线层还包括第六线路路径；所述第六线路路径用于将所述第一芯片底部的所述第一触点与所述第一连接芯片对应位置处的所述第一辅助触点电性连接。
  7. 根据权利要求5所述的芯片封装结构，其特征在于，所述重布线层还包括第七线路路径；所述第七线路路径用于将至少部分所述第二辅助触点电性连接。
  8. 根据权利要求1-7任一项所述的芯片封装结构，其特征在于，所述第一芯片和所述第二芯片还包括多个第三触点，所述第三触点分布于所述第一芯片和第二芯片的 底部被所述第一连接芯片投影覆盖的区域；
    所述第一连接芯片还包括多个第三辅助触点，所述第三辅助触点与所述第三触点对应分布；
    所述重布线层还包括第八线路路径；所述第八线路路径用于将所述第三触点与所述第三辅助触点电性连接。
  9. 根据权利要求1-8任一项所述的芯片封装结构，其特征在于，所述第一线路路径用于传输知识产权电源信号和地信号；
    所述第二线路路径用于传输知识产权电源信号、核心电源信号以及地信号。
  10. 根据权利要求1-9任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第二连接芯片；
    所述第二连接芯片与所述第一连接芯片并排设置在所述重布线层的所述第二表面上；所述第二连接芯片的投影覆盖所述第一芯片和第二芯片的部分区域。
  11. 根据权利要求1-10任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括第三芯片；
    所述第三芯片设置在所述重布线层的所述第一表面上，与所述第一芯片和第二芯片间存在间隔；所述第三芯片的部分区域被所述第一连接芯片的投影覆盖。
  12. 一种电子设备，其特征在于，包括权利要求1-11任一项所述的芯片封装结构和印刷线路板，所述芯片封装结构设置在所述印刷线路板上。
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