CN112385024A - 扇出封装方法及扇出封装板 - Google Patents
扇出封装方法及扇出封装板 Download PDFInfo
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- CN112385024A CN112385024A CN201880095500.4A CN201880095500A CN112385024A CN 112385024 A CN112385024 A CN 112385024A CN 201880095500 A CN201880095500 A CN 201880095500A CN 112385024 A CN112385024 A CN 112385024A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims abstract description 195
- 239000012815 thermoplastic material Substances 0.000 claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000005538 encapsulation Methods 0.000 claims description 40
- 210000001503 joint Anatomy 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000005022 packaging material Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 238000000465 moulding Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- WABPQHHGFIMREM-AKLPVKDBSA-N lead-210 Chemical compound [210Pb] WABPQHHGFIMREM-AKLPVKDBSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73217—Layer and HDI connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
在基板(100)的一侧或两侧制作电路图案(110A,110B),将电子零件(200A,200B)安装于所述基板(100)的一侧或两侧,在基板(100)的两侧制作封装层(300),所述基板(100)两侧的所述封装层(300)将所述基板(100)、所述电路图案(110A,110B)、和所述电子零件(200A,200B)包封在内,所述封装层(300)为热塑性材料制成;其中,所述基板(100)设有过孔(120),所述过孔(120)将所述基板(100)的两侧连通,在基板(100)的两侧制作封装层(300)时,所述封装层(300)的部分穿过所述过孔(120),所述基板(100)两侧的所述封装层(300)通过所述过孔(120)相连接。减小封装材料的耗散系数,信号损耗小,能够很好地应用于高频射频器件的封装。
Description
PCT国内申请,说明书已公开。
Claims (17)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/109773 WO2020073265A1 (zh) | 2018-10-11 | 2018-10-11 | 扇出封装方法及扇出封装板 |
Publications (2)
Publication Number | Publication Date |
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CN112385024A true CN112385024A (zh) | 2021-02-19 |
CN112385024B CN112385024B (zh) | 2023-11-10 |
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CN201880095500.4A Active CN112385024B (zh) | 2018-10-11 | 2018-10-11 | 扇出封装方法及扇出封装板 |
Country Status (3)
Country | Link |
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US (1) | US11710646B2 (zh) |
CN (1) | CN112385024B (zh) |
WO (1) | WO2020073265A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113078070A (zh) * | 2021-03-30 | 2021-07-06 | 无锡闻泰信息技术有限公司 | 器件塑封方法 |
CN115910821A (zh) * | 2023-03-10 | 2023-04-04 | 广东省科学院半导体研究所 | 芯片粒精细互连封装结构及其制备方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110416139B (zh) * | 2019-09-11 | 2021-08-31 | 京东方科技集团股份有限公司 | 一种转移载板、其制作方法及发光二极管芯片的转移方法 |
US11557706B2 (en) * | 2020-09-30 | 2023-01-17 | Ford Global Technologies, Llc | Additive manufacturing of electrical circuits |
Citations (10)
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US20020140108A1 (en) * | 2001-03-30 | 2002-10-03 | International Business Machines Corporation | Molded body for pbga and chip-scale packages |
US20020180024A1 (en) * | 2001-05-29 | 2002-12-05 | Siliconware Precision Industries Co., Ltd., Taiwan R.O.C. | Semiconductor package and method for fabricating the same |
US20060118941A1 (en) * | 2004-12-02 | 2006-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
CN1820360A (zh) * | 2003-08-29 | 2006-08-16 | 株式会社瑞萨科技 | 半导体器件的制造方法 |
KR20120051992A (ko) * | 2010-11-15 | 2012-05-23 | 삼성전기주식회사 | 방열 기판 및 그 제조 방법, 그리고 상기 방열 기판을 구비하는 패키지 구조체 |
CN102610533A (zh) * | 2011-01-20 | 2012-07-25 | 群成科技股份有限公司 | 注射封胶系统及其方法 |
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KR20140060994A (ko) * | 2012-11-13 | 2014-05-21 | 엘지이노텍 주식회사 | 칩 패키지용 기판 및 그 제조방법 |
US20140268619A1 (en) * | 2011-09-02 | 2014-09-18 | Lg Innotek Co., Ltd. | Method of Manufacturing Substrate for Chip Packages and Method of Manufacturing Chip Package |
US20160035678A1 (en) * | 2014-07-30 | 2016-02-04 | Samsung Electro-Mechanics Co., Ltd. | Semiconductor package and method of manufacturing the same |
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JP2007235004A (ja) * | 2006-03-03 | 2007-09-13 | Mitsubishi Electric Corp | 半導体装置 |
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KR101496172B1 (ko) * | 2012-07-12 | 2015-02-27 | 이노악 코포레이션 | 탄소 섬유 강화 복합시트 및 그 제조 방법 |
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KR101982040B1 (ko) | 2016-06-21 | 2019-05-24 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
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US20190326257A1 (en) * | 2018-04-24 | 2019-10-24 | Rahul Agarwal | High density fan-out packaging |
-
2018
- 2018-10-11 WO PCT/CN2018/109773 patent/WO2020073265A1/zh active Application Filing
- 2018-10-11 CN CN201880095500.4A patent/CN112385024B/zh active Active
- 2018-10-11 US US17/274,720 patent/US11710646B2/en active Active
Patent Citations (10)
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US20020140108A1 (en) * | 2001-03-30 | 2002-10-03 | International Business Machines Corporation | Molded body for pbga and chip-scale packages |
US20020180024A1 (en) * | 2001-05-29 | 2002-12-05 | Siliconware Precision Industries Co., Ltd., Taiwan R.O.C. | Semiconductor package and method for fabricating the same |
CN1820360A (zh) * | 2003-08-29 | 2006-08-16 | 株式会社瑞萨科技 | 半导体器件的制造方法 |
US20060118941A1 (en) * | 2004-12-02 | 2006-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
KR20120051992A (ko) * | 2010-11-15 | 2012-05-23 | 삼성전기주식회사 | 방열 기판 및 그 제조 방법, 그리고 상기 방열 기판을 구비하는 패키지 구조체 |
CN102610533A (zh) * | 2011-01-20 | 2012-07-25 | 群成科技股份有限公司 | 注射封胶系统及其方法 |
CN102768962A (zh) * | 2011-01-24 | 2012-11-07 | 美国博通公司 | 一种集成电路封装及其组装方法 |
US20140268619A1 (en) * | 2011-09-02 | 2014-09-18 | Lg Innotek Co., Ltd. | Method of Manufacturing Substrate for Chip Packages and Method of Manufacturing Chip Package |
KR20140060994A (ko) * | 2012-11-13 | 2014-05-21 | 엘지이노텍 주식회사 | 칩 패키지용 기판 및 그 제조방법 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113078070A (zh) * | 2021-03-30 | 2021-07-06 | 无锡闻泰信息技术有限公司 | 器件塑封方法 |
CN115910821A (zh) * | 2023-03-10 | 2023-04-04 | 广东省科学院半导体研究所 | 芯片粒精细互连封装结构及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US20220051908A1 (en) | 2022-02-17 |
CN112385024B (zh) | 2023-11-10 |
WO2020073265A1 (zh) | 2020-04-16 |
US11710646B2 (en) | 2023-07-25 |
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