KR100392061B1 - 드랍-인 방법으로 패키징하는 피비쥐에이에서 전기적안정성을 확보하는 방법 - Google Patents
드랍-인 방법으로 패키징하는 피비쥐에이에서 전기적안정성을 확보하는 방법 Download PDFInfo
- Publication number
- KR100392061B1 KR100392061B1 KR10-2001-0056692A KR20010056692A KR100392061B1 KR 100392061 B1 KR100392061 B1 KR 100392061B1 KR 20010056692 A KR20010056692 A KR 20010056692A KR 100392061 B1 KR100392061 B1 KR 100392061B1
- Authority
- KR
- South Korea
- Prior art keywords
- heat sink
- pbga
- pcb substrate
- drop
- chip
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (1)
- 상측에 그라운드용 레이어(11)가 부분적으로 노출된 PCB기판(10)에 칩(20)을 세팅시키고, 몰드캐버티(70) 내측에 전도성 재질의 방열판(40)을 거꾸로 드랍-인(Drop-in)시킨 후, 상기 방열판(40)의 돌출형성된 레그(41)가 상기 PCB기판(10)에 부분적으로 노출된 그라운드용 레이어(11)에 밀착되도록 칩(20)이 세팅된 PCB기판(10)을 상기 몰드캐버티(70)에 거꾸로 넣고, 상기 몰드캐버티(70) 내에 몰딩화합물을 주입하여 응고시켜 몰딩함으로써, 상기 방열판(40)이 그라운드 효과를 발휘하여 패키지내에 전기적 안정성을 확보하도록 이루어진 것을 특징으로 하는 드랍-인 방법으로 패키징하는 PBGA에서 전기적 안정성을 확보하는 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0056692A KR100392061B1 (ko) | 2001-09-14 | 2001-09-14 | 드랍-인 방법으로 패키징하는 피비쥐에이에서 전기적안정성을 확보하는 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0056692A KR100392061B1 (ko) | 2001-09-14 | 2001-09-14 | 드랍-인 방법으로 패키징하는 피비쥐에이에서 전기적안정성을 확보하는 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030023932A KR20030023932A (ko) | 2003-03-26 |
KR100392061B1 true KR100392061B1 (ko) | 2003-07-22 |
Family
ID=27723987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0056692A KR100392061B1 (ko) | 2001-09-14 | 2001-09-14 | 드랍-인 방법으로 패키징하는 피비쥐에이에서 전기적안정성을 확보하는 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100392061B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101009525B1 (ko) * | 2009-03-24 | 2011-01-18 | 주식회사 영일프레시젼 | 피비쥐에이용 센터게이트 방열판 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63126237A (ja) * | 1986-11-15 | 1988-05-30 | Matsushita Electric Works Ltd | 半導体パツケ−ジの製法 |
US5432742A (en) * | 1992-04-30 | 1995-07-11 | Ihara; Makoto | System memory and a microcomputer comprising the same |
KR19990036925A (ko) * | 1997-10-08 | 1999-05-25 | 가네꼬 히사시 | 밀봉 수지부 내에 방열판을 내장한 반도체 패키지 및 그 제조방법 |
US5977626A (en) * | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
-
2001
- 2001-09-14 KR KR10-2001-0056692A patent/KR100392061B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63126237A (ja) * | 1986-11-15 | 1988-05-30 | Matsushita Electric Works Ltd | 半導体パツケ−ジの製法 |
US5432742A (en) * | 1992-04-30 | 1995-07-11 | Ihara; Makoto | System memory and a microcomputer comprising the same |
KR19990036925A (ko) * | 1997-10-08 | 1999-05-25 | 가네꼬 히사시 | 밀봉 수지부 내에 방열판을 내장한 반도체 패키지 및 그 제조방법 |
US5977626A (en) * | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101009525B1 (ko) * | 2009-03-24 | 2011-01-18 | 주식회사 영일프레시젼 | 피비쥐에이용 센터게이트 방열판 |
Also Published As
Publication number | Publication date |
---|---|
KR20030023932A (ko) | 2003-03-26 |
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