WO2020073265A1 - 扇出封装方法及扇出封装板 - Google Patents

扇出封装方法及扇出封装板 Download PDF

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Publication number
WO2020073265A1
WO2020073265A1 PCT/CN2018/109773 CN2018109773W WO2020073265A1 WO 2020073265 A1 WO2020073265 A1 WO 2020073265A1 CN 2018109773 W CN2018109773 W CN 2018109773W WO 2020073265 A1 WO2020073265 A1 WO 2020073265A1
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WIPO (PCT)
Prior art keywords
substrate
layer
sides
fan
circuit pattern
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Application number
PCT/CN2018/109773
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English (en)
French (fr)
Inventor
胡川
燕英强
郭跃进
皮迎军
刘俊军
普拉克·爱德华
Original Assignee
深圳市修颐投资发展合伙企业（有限合伙）
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Application filed by 深圳市修颐投资发展合伙企业（有限合伙） filed Critical 深圳市修颐投资发展合伙企业（有限合伙）
Priority to US17/274,720 priority Critical patent/US11710646B2/en
Priority to PCT/CN2018/109773 priority patent/WO2020073265A1/zh
Priority to CN201880095500.4A priority patent/CN112385024B/zh
Publication of WO2020073265A1 publication Critical patent/WO2020073265A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention belongs to the field of electronics, and specifically relates to a fan-out packaging method and a fan-out packaging board.
  • thermosetting packaging materials such as epoxy (epoxy resin) are injected into the mold and then cured by heating.
  • This type of thermosetting material has poor high-frequency electrical performance and large dissipation factor (disspation factor or loss tangent). It will cause large signal loss in the high frequency section and affect the reception and transmission of high-frequency signals in the packaged device.
  • the present invention is to overcome the defects of the prior art, provide a fan-out packaging method and a fan-out packaging board, reduce the dissipation coefficient of the packaging material, and reduce the signal loss, which can be well applied to high-frequency RF devices Package.
  • a fan-out packaging method includes: making a circuit pattern on one or both sides of a substrate, installing electronic parts on one or both sides of the substrate, making a packaging layer on both sides of the substrate, and two sides of the substrate
  • the encapsulation layer encapsulates the substrate, the circuit pattern, and the electronic parts.
  • the encapsulation layer is made of a thermoplastic material; wherein, the substrate is provided with vias, and the vias will The two sides of the substrate are connected, and when the encapsulation layer is made on both sides of the substrate, a part of the encapsulation layer passes through the via, and the encapsulation layers on both sides of the substrate are connected through the via.
  • the thickness of the electronic component is reduced, and then the encapsulation layer is fabricated.
  • an external connection hole is formed on the packaging layer, the external connection hole is docked with the circuit pattern, or the external connection hole is docked with the electronic component, and the external connection hole is in the package
  • the layer surface is provided with openings.
  • an external pin is made in the external connecting hole through the opening of the external connecting hole, the external pin is electrically connected to the circuit pattern, or the external pin and the electronic The parts are electrically connected, and the external pin is BGA or LGA.
  • an interconnect hole is formed on the substrate and the encapsulation layer, the interconnect hole is provided with an opening on the surface of the encapsulation layer, the interconnect hole connects the chip and the circuit
  • the patterns are butted, an interconnection layer is formed in the interconnection hole through the opening of the interconnection hole, and the chip and the circuit pattern are electrically connected through the interconnection layer.
  • a substrate having circuit patterns and electronic parts is placed in a mold, a thermoplastic material is injected into the mold, the thermoplastic material wraps both sides of the substrate, and the thermoplastic material is placed in the mold Inner molding is the encapsulation layer on both sides of the substrate.
  • a support column is provided in the mold, and the support column abuts and supports the substrate, and a gap between the two sides of the substrate and the mold is for the injection of the thermoplastic material.
  • the substrate is provided with a via or a via is formed on the substrate, the via connects both sides of the substrate, and an encapsulation layer is formed on both sides of the substrate, the encapsulation layer Part passes through the via, and the encapsulation layers on both sides of the substrate are connected through the via.
  • the whole of the substrate, the circuit pattern, the electronic component, and the encapsulation layer is flexible and bendable.
  • thermoplastic material is LCP.
  • a fan-out package board includes a substrate and a packaging layer made of a thermoplastic material; wherein, a circuit pattern or an electronic part is provided on one side of the substrate, and the substrate and the packaging layer combine the circuit pattern or the Encapsulation of the electronic parts; or, the substrate is provided with circuit patterns or electronic parts, and both sides of the substrate have encapsulation layers, and the encapsulation layers on both sides of the substrate combine the substrate, the circuit pattern, and all The electronic component encapsulation, wherein the substrate is provided with vias, parts of the packaging layer on both sides of the substrate pass through the vias, and the packaging layers on both sides of the substrate pass through the vias Connected.
  • an external connection hole is provided on the packaging layer, the external connection hole is docked with the circuit pattern or the electronic component, and the external connection hole is provided with an opening on the surface of the packaging layer.
  • an external pin is provided in the external connecting hole, the external pin is electrically connected to the circuit pattern, or the external pin is electrically connected to the electronic part, the external lead
  • the feet are BGA or LGA.
  • an interconnect hole is provided on the substrate and the packaging layer, the interconnect hole is provided with an opening on the surface of the packaging layer, the interconnect hole and the chip and the The circuit patterns are butted, an interconnection layer is provided in the interconnection hole, and the chip is electrically connected to the circuit pattern through the interconnection layer.
  • the whole of the substrate, the circuit pattern, the electronic component, and the encapsulation layer is flexible and bendable.
  • the fan-out packaging method includes packaging on one side of the substrate or packaging on both sides of the substrate.
  • the encapsulation layer is made on one side of the substrate. The encapsulation layer and the substrate encapsulate the circuit pattern or electronic parts.
  • the encapsulation layer is made of thermoplastic material; the encapsulation layer can be directly attached Attached to the surface of the substrate, the encapsulation layer may be wrapped around a part of the substrate so that the encapsulation layer may be fixed on the substrate, or another structure of mutual hooks may be provided on the substrate or the encapsulation layer to fix the encapsulation layer on the substrate.
  • the encapsulation layer encapsulates the substrate, circuit pattern, and electronic parts, and the encapsulation layer is made of thermoplastic material.
  • the encapsulation layer is directly attached to the substrate, or the encapsulation layers on both sides of the substrate are connected across the edge of the substrate, or other interlocking structures are provided on the substrate or the encapsulation layer to fix the encapsulation layer on the substrate.
  • thermoplastic materials instead of traditional thermosetting materials for fan-out and packaging, and the loss of electronic performance is small, faster, especially the loss of high-frequency devices, such as 5G, vehicle safety 24GHz and 77GHz sensors, 60GHz high-frequency wireless HDMI and other environments.
  • the substrate is provided with a via hole or a via hole is made on the substrate, the via hole connects the two sides of the substrate, a packaging layer is made on both sides of the substrate, part of the packaging layer passes through the via hole, and the packaging layers on both sides of the substrate pass through
  • the holes are connected to connect the encapsulation layers on both sides of the substrate into a whole.
  • the encapsulation layers on both sides of the substrate are pulled by the part of the encapsulation layer passing through the via hole to sandwich the substrate, so that the encapsulation layers on both sides are fixed on the substrate.
  • thermoplastic material is LCP.
  • the position of the electronic parts relative to the substrate is fixed at this time, and the thickness of the electronic parts is reduced by grinding, cutting or other methods (thickness refers to the height of the electronic parts relative to the protrusion of the substrate) , And then make the encapsulation layer.
  • the thickness of the electronic component is reduced, the thickness of the packaging layer can be reduced, and the overall thickness of the final packaged substrate, circuit pattern, electronic component, and packaging layer can be greatly reduced.
  • the thickness of the electronic parts can be reduced drop to lowest.
  • the circuit pattern and the electronic parts are blocked by the encapsulation layer, and the outer connection hole is made on the encapsulation layer, the outer connection hole is connected with the circuit pattern, or the outer connection hole is connected with the electronic part, and the outer connection hole is on the surface of the encapsulation layer
  • There is an opening to expose part of the circuit pattern or part of the electronic component through the external connection hole for example, the circuit pattern is used for externally connected circuit pins, and the electronic component is used for externally connected parts pins from the package layer and the substrate The exposure allows circuit patterns and electronic parts to be electrically connected to other devices through external connection holes.
  • the two sides of the substrate are denoted as “first side” and “second side” respectively, when the electronic component or circuit pattern is located on the first side of the substrate, but the electronic component or circuit pattern needs to be externally viewed from the second side of the substrate During connection, the circuit pattern or the electronic component is blocked by the substrate and the encapsulation layer. At this time, an external connection hole is formed on the encapsulation layer and the substrate. The external connection hole is provided with an opening on the second side of the encapsulation layer. A part of the pattern or a part of the electronic part is exposed for external connection.
  • the external connection hole itself and the opening of the external connection hole provide an operation space for external connection.
  • the external pin is made in the external connection hole through the opening of the external connection hole, the external pin is electrically connected to the circuit pattern, or the external pin is connected to the electronic Parts are electrically connected.
  • the external pin can be accommodated in the space of the external connection hole, or the external pin extends out of the external connection hole, and the external pin is provided on the outer surface of the packaging layer.
  • the external pins are BGA (Ball Grid Array, solder ball array package) or LGA (Land Grid Array, grid array package).
  • the electronic parts are provided with part pins for wiring.
  • the electronic parts are arranged on the first side of the substrate.
  • the part pins face the substrate, and interconnect holes are formed on the substrate and the encapsulation layer.
  • the interconnect holes are provided on the surface of the encapsulation layer. Openings, interconnection holes pass through the packaging layer and the substrate to expose part pins, and the interconnection holes connect the chip and the circuit pattern, and an interconnection layer is made in the interconnection holes through the openings of the interconnection holes, so that the electronic parts and the circuit
  • the patterns are electrically connected through the interconnection layer, thereby achieving the electrical connection between the electronic parts and the circuit patterns.
  • thermoplastic material encapsulation process is used in conjunction with the traditional flip-out fan-out process. If it is replaced with the encapsulation method of the present invention, it is easy to produce incompatibility between the two processes, and fan-out and encapsulation cannot be completed. Therefore, it is preferable to adopt the method of providing interconnection holes in the present invention to realize the interconnection of electronic parts and circuit patterns, which can be well compatible with the packaging process using thermoplastic materials in the present invention.
  • the unformed thermoplastic material in the mold is pressurized, and the unformed thermoplastic material has fluidity.
  • the pressurization can make the unformed thermoplastic material flow to cover the gaps and grooves on the substrate, the circuit pattern, and the electronic parts, to avoid the occurrence of packaging Hollow.
  • a support column is provided in the mold.
  • the support column abuts the support substrate.
  • the gap between the two sides of the substrate and the mold is for the injection of thermoplastic material.
  • the support column abuts the first side or the second side of the substrate, or both The side and the second side provide support for the substrate, avoid displacement of the substrate during injection molding, and improve the molding quality of the encapsulation layer.
  • Pressure P is applied to the unformed thermoplastic material in the mold; wherein, 1.1 atmospheres ⁇ P ⁇ 10 atmospheres. In order to make the unformed thermoplastic material flow and cover the gaps and grooves on the substrate, the circuit pattern, and the electronic parts, to avoid voids during packaging.
  • the whole of the substrate, circuit pattern, electronic parts, and packaging layer is flexible and bendable. Since the fan-out packaging method of the present invention is compatible with FPC substrates, the PFC substrate can be used and the structure of the electronic parts can be reasonably configured, as well as factors such as the composition and thickness of the packaging layer, so that the package product (substrate) obtained by the fan-out packaging method of the present invention , The circuit pattern, the electronic components, and the package layer as a whole) the whole is flexible and bendable.
  • FIG. 1 is a structural diagram of manufacturing circuit patterns, external connection holes, and interconnect holes on a substrate according to Embodiment 1 of the present invention
  • FIG. 2 is a structural diagram of mounting electronic parts on a substrate according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of a substrate placed in a mold according to an embodiment of the present invention.
  • thermoplastic material filled into a mold according to an embodiment of the present invention
  • FIG. 5 is a structural diagram of a molded packaging layer according to an embodiment of the present invention.
  • FIG. 6 is a structural diagram of manufacturing an outer connecting hole and an interconnecting hole in a packaging layer according to Embodiment 1 of the present invention.
  • FIG. 7 is a structural diagram of a packaged circuit board according to Embodiment 1 of the present invention.
  • FIG. 8 is a structural diagram of manufacturing circuit patterns, external connection holes, and interconnect holes on a substrate according to Embodiment 2 of the present invention.
  • FIG. 9 is a structural diagram of mounting electronic parts on a substrate according to Embodiment 2 of the present invention.
  • FIG. 10 is a structural diagram of a thinned electronic part according to Embodiment 2 of the present invention.
  • FIG. 11 is a structural diagram of a thermoplastic material filled into a mold according to an embodiment of the present invention.
  • FIG. 12 is a structural diagram of a molded encapsulation layer according to Embodiment 2 of the present invention.
  • FIG. 13 is a structural diagram of manufacturing an outer connecting hole and an interconnecting hole in a packaging layer according to Embodiment 2 of the present invention.
  • FIG. 14 is a structural diagram of a circuit board after packaging according to Embodiment 2 of the present invention.
  • this embodiment is to encapsulate layers on both sides of the substrate for packaging at the same time, but it is not limited to this method.
  • the method of the present invention can also be used to encapsulate only one side of the substrate.
  • the circuit patterns 110A and 110B are formed on both sides of the substrate 100.
  • the circuit patterns 110A and 110B on both sides of the substrate 100 may be electrically connected or not connected to each other.
  • the circuit patterns 110A, 110B include but are not limited to lines, interconnects, antennas, pins with electronic functions, and the materials for making the circuit patterns 110A, 110B include but are not limited to copper, or silver, or iron, or other conductive materials or semiconductors material.
  • a via hole 120, an outer connecting hole 140, and interconnect holes 130A, 130B are formed in the substrate 100.
  • the electronic components 200A, 200B are pasted on the substrate 100 through the patch material 220.
  • the electronic components 200A, 200B are only provided on the first side of the substrate 100, but it is not limited to this embodiment, and may also be Electronic components 200A and 200B are provided on both sides of the substrate 100.
  • the electronic components 200A and 200B have component pins 210.
  • the component pins 210 on the electronic components 200A and 200B face the substrate 100.
  • the electronic components 200A and 200B can The circuit pattern 110A on one side or the circuit pattern 110B on the second side of the substrate 100 is electrically connected or not connected.
  • the electronic parts 200A and 200B include but are not limited to chips, bare chips, electronic components, and electronic devices.
  • the heights of the electronic parts 200A and 200B shown in FIG. 2 are different.
  • a substrate 100 having circuit patterns 110A, 110B and electronic parts 200A, 200B is placed in a mold 101, and a support post 102 is provided in the mold 101.
  • the support post 102 abuts the support substrate 100, and both sides of the substrate 100
  • the gap between the mold 101 and the thermoplastic material is injected, and the support post 102 abuts the first side and the second side of the substrate 100 to provide support for the substrate 100, avoid displacement of the substrate 100 during injection molding, and improve the molding of the encapsulation layer 300 quality.
  • thermoplastic material is injected into the mold 101, the thermoplastic material wraps both sides of the substrate 100, and the thermoplastic material is molded into the encapsulation layer 300 on both sides of the substrate 100 in the mold 101.
  • the unformed thermoplastic material in the mold 101 is pressurized, and the unformed thermoplastic material has fluidity. Pressing can make the unformed thermoplastic material flow to cover the substrate 100, the circuit patterns 110A, 100B, and the electronic parts 200A, 200B
  • the gaps and ravines avoid voids during packaging, and the vias 120 communicate with the thermoplastic materials on both sides of the substrate 100, and the thermoplastic materials fill the vias 120.
  • the thermoplastic material is cured on both sides of the substrate 100 to form an encapsulation layer 300, and encapsulates the substrate 100, the circuit patterns 110A, 100B, and the electronic components 200A, 200B.
  • part of the encapsulation layer 300 passes through the via 120, and the encapsulation layers 300 on both sides of the substrate 100 are connected through the via 120, so that the encapsulation layers 300 on both sides of the substrate 100 are connected as a whole, and the encapsulation layers on both sides of the substrate 100 300 is pulled by the portion of the encapsulation layer 300 passing through the via 120 to sandwich the substrate 100, so that the encapsulation layers 300 on both sides are fixed on the substrate 100.
  • thermoplastic materials instead of traditional thermosetting materials for fan-out and packaging, the loss of electronic performance is small and the speed is faster, especially the loss of high-frequency devices, such as 5G, vehicle-mounted 24GHz and 77GHz sensors, 60GHz high-frequency wireless HDMI Wait for the environment.
  • the thermoplastic material is LCP.
  • the circuit patterns 110A, 110B and the electronic components 200A, 200B are blocked by the packaging layer 300, and the external connection hole 140 and the interconnection hole 130 need to be reopened.
  • an external connection hole 140 is formed in the encapsulation layer 300 on the first side of the substrate 100, and the external connection hole 140 is provided with an opening in the encapsulation layer 300, as shown in FIG.
  • the external pin 400 is made in the external connecting hole 140 through the opening of the external connecting hole 140, and the external pin 400 is electrically connected to the circuit pattern 110A.
  • the electronic components 200A and 200B are located on the first side of the substrate 100, but when the electronic components 200A, 200B or the circuit pattern 110A need to be externally connected from the second side of the substrate 100, the circuit pattern 110A or the electronic component 200A and 200B are blocked by the substrate 100 and the encapsulation layer 300. Therefore, an external connection hole 140 is formed on the packaging layer 300 and the substrate 100, and the external connection hole 140 is provided with an opening on the second side of the packaging layer 300 to expose the component pins 210 of the electronic parts 200A and 200B for external connection . As shown in FIG.
  • an external pin 400 is made in the external connecting hole 140 through the opening of the external connecting hole 140, and the external pin 400 is electrically connected to the component pin 210 of the electronic parts 200A, 200B.
  • the outer pin 400 may be accommodated in the space of the outer connecting hole 140, or the outer pin 400 may extend out of the outer connecting hole 140.
  • the electronic parts 200A and 200B are provided with component pins 210 for wiring, the electronic parts 200A and 200B are provided on the first side of the substrate 100, and the component pins 210 face the substrate 100.
  • the interconnect holes 130A and 130B are formed on the substrate 100 and the packaging layer 300.
  • the interconnect holes 130A and 130B are provided with openings on the surface of the packaging layer 300 on the second side.
  • the interconnect holes 130A and 130B pass through the packaging layer 300 and the substrate 100
  • the part pins 210 are exposed, and the interconnect holes 130A, 130B butt the part pins 210 of the electronic parts 200A, 200B and the circuit patterns 110A, 110B, through the openings of the interconnect holes 130A, 130B in the interconnect holes 130A, 130B
  • the interconnection layers 410A, 410B are made so that the electronic component 200A and the first side circuit pattern 110A are electrically connected through the interconnection layer 410A, and the electronic component 200B and the second side circuit pattern 110B are electrically connected through the interconnection layer 410B, wherein the interconnection
  • the layers 410A, 410B can be made of conductive materials or semiconductor materials through deposition growth, electroplating, welding, and other processes.
  • the traditional thermoplastic material encapsulation process is used in conjunction with the traditional flip-out fan-out process. If it is replaced with the encapsulation method of the present invention, it is easy to produce incompatibility between the two processes, and fan-out and encapsulation cannot be completed. Therefore, preferably, the interconnection hole 130 is provided in the present invention to realize the interconnection between the electronic parts 200A, 200B and the circuit patterns 110A, 110B, which can be well compatible with the packaging process using thermoplastic materials in the present invention.
  • the FPC substrate 100 is used, and the obtained packaged product (the whole of the substrate 100, the circuit patterns 110A, 110B, the electronic components 200A, 200B, and the package layer 300) is flexible and bendable.
  • Embodiment 2 The difference between Embodiment 2 and Embodiment 1 is:
  • the electronic parts 200A and 200B are thinned and then packaged.
  • circuit patterns 110A, 110B are formed on both sides of the substrate 100, and via holes 120, external connection holes 140, and interconnect holes 130A, 130B are formed on the substrate 100.
  • the electronic components 200A, 200B are pasted on the substrate 100 through the patch material 220,
  • the positions of the electronic components 200A and 200B relative to the substrate 100 are fixed, and the thickness of the electronic components 200A and 200B is reduced by grinding, cutting or other methods.
  • Thiickness refers to the height of the protrusion of the electronic component relative to the substrate
  • the packaging layer 300 is fabricated.
  • the thickness of the electronic parts 200A and 200B can be reduced by grinding, cutting, grinding, drilling, chemical etching, physical etching, or other methods, and the thickness of the encapsulation layer 300 can be reduced.
  • the overall thickness of the final packaged substrate 100, circuit patterns 110A, 110B, electronic components 200A, 200B, and packaging layer 300 can be greatly reduced. After the electronic parts 200A and 200B are mounted on the substrate 100 and then the electronic parts 200A and 200B are thinned, only the part required for the electronic parts 200A and 200B can be retained, and the excess part can be cut off without having to consider transferring the electronic part 200A, The mechanical strength required at 200B can minimize the thickness of the electronic parts 200A and 200B.
  • the substrate 100 having the circuit patterns 110A, 110B and the electronic parts 200A, 200B is placed in the mold 101, and the gap between the two sides of the substrate 100 and the mold 101 is for the injection of thermoplastic material.
  • a shaping convex is provided in the mold, and the shaping convex is used to form the outer connecting hole 140 in the encapsulation layer (in this embodiment, only the forming outer connecting hole is shown, but not limited to this, the shaped convex may be used to form the interconnect hole or Other structures that need to be molded in the encapsulation layer).
  • a thermoplastic material is injected into the mold 101, the thermoplastic material wraps both sides of the substrate 100, and the thermoplastic material is molded into the encapsulation layer 300 on both sides of the substrate 100 in the mold 101.
  • the thermoplastic material is cured on both sides of the substrate 100 to form an encapsulation layer 300, and encapsulates the substrate 100, the circuit patterns 110A, 100B and the electronic components 200A, 200B. Since the fixed portion 103 occupies a part of the space of the encapsulation layer 300, after the substrate 100 and the mold 101 are separated, the space originally occupied by the fixed portion 103 becomes the external connection hole 310 on the encapsulation layer 300.
  • the circuit patterns 110A, 110B and the electronic parts 200A, 200B are blocked by the packaging layer 300, and the external connection hole 140 and the interconnection hole 130 need to be reopened.
  • an outer connecting hole 140 is made in the packaging layer 300 on the first side of the substrate 100.
  • the outer connecting hole 140 is provided with an opening in the packaging layer 300.
  • the outer connecting hole is opened in the outer connecting hole In 140, an external pin 400 is made, and the external pin 400 is electrically connected to the circuit pattern 110A.
  • an external connection hole 140 is formed on the packaging layer 300 and the substrate 100.
  • the external connection hole 140 is provided with an opening on the second side of the packaging layer 300 to expose the component pins 210 of the electronic parts 200A and 200B For external connections.
  • an external pin 400 is made in the external connecting hole 140 through the opening of the external connecting hole 140, and the external pin 400 is electrically connected to the component pin 210 of the electronic parts 200A, 200B.
  • the external pin 400 on the first side of the substrate 100 is BGA.
  • interconnect holes 130A and 130B are formed in the substrate 100 and the encapsulation layer 300.
  • the interconnect holes 130A and 130B are provided with openings on the surface of the package layer 300 on the second side and interconnect holes 130A, 130B expose the part pins 210 through the packaging layer 300 and the substrate 100, and the interconnect holes 130A, 130B connect the part pins 210 of the electronic parts 200A, 200B and the circuit patterns 110A, 110B through the interconnect holes 130A , 130B openings interconnect layers 410A, 410B are made in the interconnect holes 130A, 130B, so that the electronic component 200A and the first side circuit pattern 110A are electrically connected through the interconnect layer 410A, the electronic component 200B and the second side circuit pattern 110B is electrically connected through an interconnection layer 410B, where the interconnection layers 410A, 410B may be made of conductive materials or semiconductor materials through deposition growth, electroplating, welding, and other processes.

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Abstract

在基板（100）的一侧或两侧制作电路图案（110A，110B），将电子零件（200A，200B）安装于所述基板（100）的一侧或两侧，在基板（100）的两侧制作封装层（300），所述基板（100）两侧的所述封装层（300）将所述基板（100）、所述电路图案（110A，110B）、和所述电子零件（200A，200B）包封在内，所述封装层（300）为热塑性材料制成；其中，所述基板（100）设有过孔（120），所述过孔（120）将所述基板（100）的两侧连通，在基板（100）的两侧制作封装层（300）时，所述封装层（300）的部分穿过所述过孔（120），所述基板（100）两侧的所述封装层（300）通过所述过孔（120）相连接。减小封装材料的耗散系数，信号损耗小，能够很好地应用于高频射频器件的封装。

Description

扇出封装方法及扇出封装板 技术领域
本发明属于电子领域，具体涉及扇出封装方法及扇出封装板。
背景技术
传统的扇出封装在外包注塑成型过程中通常采用压模(compression molding)或者输运中成型(transfer molding)的方法，将热固性封装材料，例如epoxy(环氧树脂)注入模具后加热固化。这类热固性材料，高频电学性能较差，耗散系数(Disspation Factor或loss tangent)大，在高频率段会造成信号损耗大，影响高频信号在被封装器件中的接收和传送。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种扇出封装方法及扇出封装板，减小封装材料的耗散系数，信号损耗小，能够很好地应用于高频射频器件的封装。
其技术方案如下：
一种扇出封装方法，包括：在基板的一侧或两侧制作电路图案，将电子零件安装于所述基板的一侧或两侧，在基板的两侧制作封装层，所述基板两侧的所述封装层将所述基板、所述电路图案、和所述电子零件包封在内，所述封装层为热塑性材料制成；其中，所述基板设有过孔，所述过孔将所述基板的两侧连通，在基板的两侧制作封装层时，所述封装层的部分穿过所述过孔，所述基板两侧的所述封装层通过所述过孔相连接。
在其中一个实施例中，在将所述电子零件安装于所述基板上后，减薄所述电子零件的厚度，再制作所述封装层。
在其中一个实施例中，在封装层上制作外连孔，所述外连孔与所述电路图案对接、或者所述外连孔与所述电子零件对接，所述外连孔在所述封装层表面设有开口。
在其中一个实施例中，通过所述外连孔的开口在所述外连孔内制作外引脚，所述外引脚与所述电路图案电连接、或者所述外引脚与所述电子零件电连接，所述外引脚为BGA或LGA。
在其中一个实施例中，在所述基板和所述封装层上制作互连孔，所述互连孔在所述封装层表面设有开口，所述互连孔将所述芯片及所述电路图案对接，通过所述互连孔的开口在所述互连孔内制作互连层，所述芯片与所述电路图案通过所述互连层电连接。
在其中一个实施例中，将具有电路图案和电子零件的基板置于模具内，将热塑性材料注入所述模具，所述热塑性材料包裹所述基板的两侧，将所述热塑性材料在所述模具内成型为所述基板两侧的所述封装层。
在其中一个实施例中，所述模具内设有支撑柱，所述支撑柱抵靠支撑所述基板，所述基板两侧与所述模具之间的间隙供所述热塑性材料注入。
在其中一个实施例中，所述基板设有过孔或者在所述基板上制作过孔，所述过孔将所述基板的两侧连通，在基板的两侧制作封装层，所述封装层的部分穿过所述过孔，所述基板两侧的所述封装层通过所述过孔相连接。
在其中一个实施例中，所述基板、所述电路图案、所述电子零件、以及所述封装层构成的整体为柔性可弯曲的。
在其中一个实施例中，所述热塑性材料为LCP。
一种扇出封装板，包括基板、以及热塑性材料制成的封装层；其中，所述基板的一侧设有电路图案或电子零件，所述基板和所述封装层将所述电路图案或所述电子零件包封；或者，所述基板设有电路图案或电子零件，所述基板的两侧均有封装层，所述基板两侧的封装层将所述基板、所述电路图案、和所述电子零件包封，其中，所述基板设有过孔，所述基板两侧的所述封装层的部分穿过所述过孔，所述基板两侧的所述封装层通过所述过孔相连接。
在其中一个实施例中，所述封装层上设有外连孔，所述外连孔与所述电路图案或所述电子零件对接，所述外连孔在所述封装层表面设有开口。
在其中一个实施例中，所述外连孔内设有外引脚，所述外引脚与所述电路图案电连接、或者所述外引脚与所述电子零件电连接，所述外引脚为BGA或LGA。
在其中一个实施例中，在所述基板和所述封装层上设有互连孔，所述互连孔在所述封装层表面设有开口，所述互连孔与所述芯片及所述电路图案对接，所述互连孔内设有互连层，所述芯片通过所述互连层与所述电路图案电连接。
在其中一个实施例中，所述基板、所述电路图案、所述电子零件、以及所述封装层构成的整体为柔性可弯曲的。
本发明的有益效果在于：
1、扇出封装方法，包括在基板的其中一侧封装或在基板的两侧封装。
基板的其中一侧封装：
在基板的一侧制作电路图案，将电子零件(电子零件包括但不限于芯片、裸片、电子元件、电子器件，也可以是任一种电路上需要的零件)安装于基板，该步骤中电子零件可以被固定在基板上、也可以不固定，在基板的一侧制作封装层，封装层与基板将电路图案或电子零件包封在内，封装层为热塑性材料制成；封装层可以直接贴附于基板表面，也可以使封装层包裹基板的其中一部分使封装层可以固定于基板上，或者在基板或封装层上设置其他相互挂扣的结构使封装层固定于基板上。
在基板的两侧封装：
在基板的两侧制作电路图案，将电子零件安装于基板，电子零件仅设置于基板的一侧、或者基板的两侧均设有电子零件，在基板的两侧制作封装层，基板两侧的封装层将基板、电路图案、和电子零件包封在内，封装层为热塑性材料制成。封装层直接附着于基板上、或者基板两侧的封装层越过基板边沿相连接、或者在基板或封装层上设置其他相互挂扣的结构使封装层固定于基板上。
采用热塑性材料代替传统的热固性材料进行扇出及封装，且电子性能的损耗小，速度更快，特别是高频器件损耗小，例如应用于5G，车载安全的24GHz和77GHz传感器，60GHz高频无线HDMI等环境。
其中，基板设有过孔或者在基板上制作过孔，过孔将基板的两侧连通，在基板的两侧制作封装层，封装层的部分穿过过孔，基板两侧的封装层通过过孔相连接，使基板两侧的封装层连接成一个整体，基板两侧的封装层被穿过过孔的那部分封装层牵拉从而夹住基板，使两侧封装层被固定在基板上。
优选的，热塑性材料为LCP。
2、在将电子零件安装于基板上后，此时电子零件相对基板的位置固定，采用磨削、切削或其他方法减薄电子零件的厚度(厚度是指电子零件相对于基板凸起的高度)，再制作封装层。减薄电子零件的厚度后，封装层的厚度可以减小，最终封装好的基板、电路图案、电子零件、和封装层构成的整体的厚度可以大幅减小。在将电子零件安装于基板后再将电子零件减薄，可以只保留电子零件所需的那一部分，将多余的部分削去，不必考虑转移电子零件时需要的机械强度，可以将电子零件的厚度降到最低。
3、制作封装层后，电路图案和电子零件被封装层遮挡，在封装层上制作外连孔，外连孔与电路图案对接、或者外连孔与电子零件对接，外连孔在封装层表面设有开口，通过外连孔将电路图案的一部分或者电子零件的一部分暴露出来，例如将电路图案用于对外连接的电路引脚、电子零件用于对外连接的零件引脚从封装层和基板内暴露出来，使得电路图案和电子零件可以通过外连孔与其他设备进行电连接。
或者，基板的两侧分别记为“第一侧”和“第二侧”，当电子零件或电路图案位于基板的第一侧，但是需要从基板的第二侧对电子零件或电路图案进行外连接时，电路图案或者电子零件被基板和封装层遮挡，此时，在所述封装层和所述基板上制作外连孔，外连孔在第二侧的封装层设有开口，如此将电路图案的一部分或者电子零件的一部分暴露出来，用于外连接。
4、外连孔本身及外连孔的开口为外连接提供了操作空间，通过外连孔的开口在外连孔内制作外引脚，外引脚与电路图案电连接、或者外引脚与电子零件电连接。外引脚可以收纳在外连孔的空间内，或者外引脚伸出外连孔，外引脚设置于封装层外表面。所述外引脚为BGA(Ball Grid Array，焊球阵列封装)或LGA(Land Grid Array,栅格阵列封装)。
5、电子零件设有用于连线的零件引脚，电子零件设置于基板的第一侧，零件引脚朝向基板，在基板和封装层上制作互连孔，互连孔在封装层表面设有开口，互连孔穿过封装层和基板将零件引脚暴露出来，并且互连孔将芯片及电路图案对接，通过互连孔的开口在互连孔内制作互连层，使电子零件与电路图案 通过互连层电连接，从而实现电子零件与电路图案的电连接。
传统的热塑性材料封装工艺是配合传统的倒装扇出工艺使用的，如果将其替换为本发明的封装方法，极易产生两种工艺不兼容，不能完成扇出与封装。因此优选地，采用本发明中设置互连孔的方式来实现电子零件与电路图案的互连接，可以很好地兼容本发明中采用热塑性材料的封装工艺。
6、将具有电路图案和电子零件的基板置于模具内，将热塑性材料注入模具，热塑性材料包裹基板的两侧，将热塑性材料在模具内成型为基板两侧的封装层。同时在基板两侧成型封装层，工艺简单，生产效率高。
优选的，对模具内未成型的热塑性材料加压，未成型的热塑性材料具有流动性，加压可以使未成型的热塑性材料流动覆盖基板、电路图案、电子零件上的缝隙沟壑，避免封装时产生空洞。
7、模具内设有支撑柱，支撑柱抵靠支撑基板，基板两侧与模具之间的间隙供热塑性材料注入，支撑柱抵靠基板的第一侧或第二侧，或者同时抵靠第一侧和第二侧，为基板提供支撑，避免基板在注塑成型中发生位移，提高封装层的成型质量。
8、对所述模具内未成型的热塑性材料加压力P；其中，1.1个大气压≤P≤10个大气压。以使未成型的热塑性材料流动覆盖基板、电路图案、电子零件上的缝隙沟壑，避免封装时产生空洞。
9、基板、电路图案、电子零件、以及封装层构成的整体为柔性可弯曲的。由于本发明的扇出封装方法兼容FPC的基板，所以可以采用PFC基板并合理配置电子零件的结构、以及封装层的成分、厚度等因素，使得本发明的扇出封装方法获得的封装产品(基板、电路图案、电子零件、以及封装层构成的整体)整体为柔性可弯曲的。
附图说明
图1为本发明实施例一在基板制作电路图案、外连孔、互连孔的结构图；
图2为本发明实施例一安装电子零件于基板的结构图；
图3为本发明实施例一基板置于模具内的结构图；
图4为本发明实施例一向模具内充注热塑性材料的结构图；
图5为本发明实施例一成型封装层的结构图；
图6为本发明实施例一在封装层制作外连孔、互连孔的结构图；
图7为本发明实施例一封装后的电路板结构图；
图8为本发明实施例二在基板制作电路图案、外连孔、互连孔的结构图；
图9为本发明实施例二安装电子零件于基板的结构图；
图10为本发明实施例二减薄电子零件的结构图；
图11为本发明实施例二向模具内充注热塑性材料的结构图；
图12为本发明实施例二成型封装层的结构图；
图13为本发明实施例二在封装层制作外连孔、互连孔的结构图；
图14为本发明实施例二封装后的电路板结构图。
附图标记说明：
100、基板，101、模具，102、支撑柱，103、定型部，110A、110B、电路图案，120、过孔，130A、130B、互连孔，140、外连孔，200A、200B、电子零件，210、零件引脚，220、贴片材料，300、封装层，310、外连孔，400、外引脚，410A、410B、互连层。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
实施例一
如图1至7所示，本实施例为在基板两侧同时制作封装层进行封装，但不限于比，本发明的方法还可以用于仅对基板的单侧进行封装。
如图1所示，在基板100的两侧制作电路图案110A、110B，基板100两侧的电路图案110A、110B之间可以相互电连接或不连接。电路图案110A、110B包括但不限于具有电子功能的线路、互连线、天线、引脚，制作电路图案110A、110B的材料包括但不限于铜、或银、或铁、或其他导电材料或半导体材料。在基板100上制作过孔120、外连孔140和互连孔130A、130B。
如图2所示，将电子零件200A、200B通过贴片材料220粘贴于基板100， 图2中电子零件200A、200B仅设置于基板100的第一侧，但不限于本实施例，也可以在基板100的两侧均设有电子零件200A、200B，电子零件200A、200B具有零件引脚210，电子零件200A、200B上的零件引脚210朝向基板100，电子零件200A、200B可以与基板100第一侧的电路图案110A或基板100第二侧的电路图案110B电连接、或不连接。其中，电子零件200A、200B包括但不限于芯片、裸片、电子元件、电子器件，图2所示电子零件200A与电子零件200B的高度不一样。
如图3所示，将具有电路图案110A、110B和电子零件200A、200B的基板100置于模具101内，模具101内设有支撑柱102，支撑柱102抵靠支撑基板100，基板100两侧与模具101之间的间隙供热塑性材料注入，支撑柱102抵靠基板100的第一侧、第二侧，为基板100提供支撑，避免基板100在注塑成型中发生位移，提高封装层300的成型质量。
如图4所示，将热塑性材料注入模具101，热塑性材料包裹基板100的两侧，将热塑性材料在模具101内成型为基板100两侧的封装层300。优选的，对模具101内未成型的热塑性材料加压，未成型的热塑性材料具有流动性，加压可以使未成型的热塑性材料流动覆盖基板100、电路图案110A、100B和电子零件200A、200B上的缝隙和沟壑，避免封装时产生空洞，并且过孔120连通基板100两侧的热塑性材料，热塑性材料充满过孔120。
如图5所示，热塑性材料固化于基板100两侧构成封装层300，将基板100、电路图案110A、100B和电子零件200A、200B包封在内。固化后，封装层300的部分穿过过孔120，基板100两侧的封装层300通过过孔120相连接，使基板100两侧的封装层300连接成一个整体，基板100两侧的封装层300被穿过过孔120的那部分封装层300牵拉从而夹住基板100，使两侧封装层300被固定在基板100上。
采用热塑性材料代替传统的热固性材料进行扇出及封装，电子性能的损耗小，速度更快，特别是高频器件损耗小，例如应用于5G，车载安全的24GHz和77GHz传感器，60GHz高频无线HDMI等环境。本实施例中热塑性材料为LCP。
制作封装层300后，电路图案110A、110B和电子零件200A、200B被封装 层300遮挡，需要重新打开外连孔140、互连孔130。
电路图案110A需要进行外连接时被封装层300遮挡，如图6所示，在基板100第一侧的封装层300制作外连孔140，外连孔140在封装层300设有开口，如图7所示，通过外连孔140的开口在外连孔140内制作外引脚400，外引脚400与电路图案110A电连接。又如图6所示，电子零件200A、200B位于基板100的第一侧，但是需要从基板100的第二侧对电子零件200A、200B或电路图案110A进行外连接时，电路图案110A或者电子零件200A、200B被基板100和封装层300遮挡。于是，在封装层300和基板100上制作外连孔140，外连孔140在第二侧的封装层300设有开口，将电子零件200A、200B的零件引脚210暴露出来，用于外连接。如图7所示，通过外连孔140的开口在外连孔140内制作外引脚400，外引脚400与电子零件200A、200B的零件引脚210电连接。其中外引脚400可以收纳在外连孔140的空间内，或者外引脚400伸出外连孔140。
另一方面，如图6、7所示，电子零件200A、200B设有用于连线的零件引脚210，电子零件200A、200B设置于基板100的第一侧，零件引脚210朝向基板100，在基板100和封装层300上制作互连孔130A、130B，互连孔130A、130B在第二侧的封装层300表面设有开口，互连孔130A、130B穿过封装层300和基板100将零件引脚210暴露出来，并且互连孔130A、130B将电子零件200A、200B的零件引脚210与电路图案110A、110B对接，通过互连孔130A、130B的开口在互连孔130A、130B内制作互连层410A、410B，使电子零件200A与第一侧的电路图案110A通过互连层410A电连接、电子零件200B与第二侧的电路图案110B通过互连层410B电连接，其中互连层410A、410B可以采用导电材料或半导体材料通过沉积生长、电镀、焊接等工艺制成。
传统的热塑性材料封装工艺是配合传统的倒装扇出工艺使用的，如果将其替换为本发明的封装方法，极易产生两种工艺不兼容，不能完成扇出与封装。因此优选地，采用本发明中设置互连孔130的方式来实现电子零件200A、200B与电路图案110A、110B的互连接，可以很好地兼容本发明中采用热塑性材料的封装工艺。
本实施例中，采用FPC基板100，所获得的封装产品(基板100、电路图案110A、110B、电子零件200A、200B、以及封装层300构成的整体)整体为柔性可弯曲的。
实施例二
实施例二与实施例一的区别在于：
对电子零件200A、200B进行减薄后再封装。
如图8所示，在基板100的两侧制作电路图案110A、110B，在基板100上制作过孔120、外连孔140和互连孔130A、130B。
如图9所示，将电子零件200A、200B通过贴片材料220粘贴于基板100，
如图10所示，电子零件200A、200B贴装于基板100上后，此时电子零件200A、200B相对基板100的位置固定，采用磨削、切削或其他方法减薄电子零件200A、200B的厚度(厚度是指电子零件相对于基板凸起的高度)，再制作封装层300。减薄电子零件200A、200B的厚度后，可以采用磨削、切削、研磨、钻、化学蚀刻、物理蚀刻等或其他方法减薄电子零件200A、200B的厚度，封装层300的厚度可以减小，最终封装好的基板100、电路图案110A、110B、电子零件200A、200B、和封装层300构成的整体的厚度可以大幅减小。在将电子零件200A、200B安装于基板100后再将电子零件200A、200B减薄，可以只保留电子零件200A、200B所需的那一部分，将多余的部分削去，不必考虑转移电子零件200A、200B时需要的机械强度，可以将电子零件200A、200B的厚度降到最低。
如图11所示，将具有电路图案110A、110B和电子零件200A、200B的基板100置于模具101内，基板100两侧与模具101之间的间隙供热塑性材料注入。模具内设有定型凸，所述定型凸用于在封装层内成型外连孔140(本实施例中仅图示成型外连孔，但不限于此，定型凸可以用于成型互连孔或其他需要在封装层内成型的结构)。将热塑性材料注入模具101，热塑性材料包裹基板100的两侧，将热塑性材料在模具101内成型为基板100两侧的封装层300。
如图12所示，热塑性材料固化于基板100两侧构成封装层300，将基板100、 电路图案110A、100B和电子零件200A、200B包封在内。由于定型部103挤占封装层300的部分空间，将基板100与模具101分离后，原来定型部103所占的空间成为封装层300上的外连孔310。
如图13所示，制作封装层300后，电路图案110A、110B和电子零件200A、200B被封装层300遮挡，需要重新打开外连孔140、互连孔130。
如图13所示，在基板100第一侧的封装层300制作外连孔140，外连孔140在封装层300设有开口，如图14所示，通过外连孔140的开口在外连孔140内制作外引脚400，外引脚400与电路图案110A电连接。
又如图13所示，在封装层300和基板100上制作外连孔140，外连孔140在第二侧的封装层300设有开口，将电子零件200A、200B的零件引脚210暴露出来，用于外连接。如图14所示，通过外连孔140的开口在外连孔140内制作外引脚400，外引脚400与电子零件200A、200B的零件引脚210电连接。不实施例中，基板100的第一侧的外引脚400是BGA。
另一方面，如图13、14所示，在基板100和封装层300上制作互连孔130A、130B，互连孔130A、130B在第二侧的封装层300表面设有开口，互连孔130A、130B穿过封装层300和基板100将零件引脚210暴露出来，并且互连孔130A、130B将电子零件200A、200B的零件引脚210与电路图案110A、110B对接，通过互连孔130A、130B的开口在互连孔130A、130B内制作互连层410A、410B，使电子零件200A与第一侧的电路图案110A通过互连层410A电连接、电子零件200B与第二侧的电路图案110B通过互连层410B电连接，其中互连层410A、410B可以采用导电材料或半导体材料通过沉积生长、电镀、焊接等工艺制成。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进， 这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种扇出封装方法，其特征在于，包括：
    在基板的一侧或两侧制作电路图案，将电子零件安装于所述基板的一侧或两侧，在基板的两侧制作封装层，所述基板两侧的所述封装层将所述基板、所述电路图案、和所述电子零件包封在内，所述封装层为热塑性材料制成；
    其中，所述基板设有过孔，所述过孔将所述基板的两侧连通，在基板的两侧制作封装层时，所述封装层的部分穿过所述过孔，所述基板两侧的所述封装层通过所述过孔相连接。
  2. 根据权利要求1所述的扇出封装方法，其特征在于，在将所述电子零件安装于所述基板上后，减薄所述电子零件的厚度，再制作所述封装层。
  3. 根据权利要求1所述的扇出封装方法，其特征在于，在封装层上制作外连孔，所述外连孔与所述电路图案对接、或者所述外连孔与所述电子零件对接，所述外连孔在所述封装层表面设有开口。
  4. 根据权利要求3所述的扇出封装方法，其特征在于，通过所述外连孔的开口在所述外连孔内制作外引脚，所述外引脚与所述电路图案电连接、或者所述外引脚与所述电子零件电连接，所述外引脚为BGA或LGA。
  5. 根据权利要求1所述的扇出封装方法，其特征在于，在所述基板和所述封装层上制作互连孔，所述互连孔在所述封装层表面设有开口，所述互连孔将所述芯片及所述电路图案对接，通过所述互连孔的开口在所述互连孔内制作互连层，所述芯片与所述电路图案通过所述互连层电连接。
  6. 根据权利要求1所述的扇出封装方法，其特征在于，将具有电路图案和电子零件的基板置于模具内，将热塑性材料注入所述模具，所述热塑性材料包裹所述基板的两侧，将所述热塑性材料在所述模具内成型为所述基板两侧的所述封装层。
  7. 根据权利要求6所述的扇出封装方法，其特征在于，所述模具内设有支撑柱，所述支撑柱抵靠支撑所述基板，所述基板两侧与所述模具之间的间隙供所述热塑性材料注入。
  8. 根据权利要求6所述的扇出封装方法，其特征在于，对所述模具内未成型的热塑性材料加压力P；其中，1.1个大气压≤P≤10个大气压。
  9. 根据权利要求1至8任一项所述的扇出封装方法，其特征在于，
  10. 根据权利要求1至8任一项所述的扇出封装方法，其特征在于，所述基板、所述电路图案、所述电子零件、以及所述封装层构成的整体为柔性可弯曲的。
  11. 根据权利要求1至8任一项所述的扇出封装方法，其特征在于，所述热塑性材料为LCP。
  12. 一种扇出封装板，其特征在于，包括基板、以及热塑性材料制成的封装层；
    所述基板的一侧设有电路图案或电子零件，所述基板和所述封装层将所述电路图案或所述电子零件包封；或者，所述基板设有电路图案或电子零件，所述基板的两侧均有封装层，所述基板两侧的封装层将所述基板、所述电路图案、和所述电子零件包封；
    其中，所述基板设有过孔，所述基板两侧的所述封装层的部分穿过所述过孔，所述基板两侧的所述封装层通过所述过孔相连接。
  13. 根据权利要求12所述的扇出封装板，其特征在于，所述封装层上设有外连孔，所述外连孔与所述电路图案或所述电子零件对接，所述外连孔在所述封装层表面设有开口。
  14. 根据权利要求13所述的扇出封装板，其特征在于，所述外连孔内设有外引脚，所述外引脚与所述电路图案电连接、或者所述外引脚与所述电子零件电连接，所述外引脚为BGA或LGA。
  15. 根据权利要求12所述的扇出封装板，其特征在于，在所述基板和所述封装层上设有互连孔，所述互连孔在所述封装层表面设有开口，所述互连孔与所述芯片及所述电路图案对接，所述互连孔内设有互连层，所述芯片通过所述互连层与所述电路图案电连接。
  16. 根据权利要求11至15任一项所述的扇出封装板，其特征在于，在封装层上制作外连孔，所述外连孔与所述电路图案对接、或者所述外连孔与所述电子零件对接，所述外连孔在所述封装层表面设有开口。
  17. 根据权利要求11至15任一项所述的扇出封装板，其特征在于，所述 基板、所述电路图案、所述电子零件、以及所述封装层构成的整体为柔性可弯曲的。
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