CN103779319B - 具有集成天线的半导体封装及其形成方法 - Google Patents

具有集成天线的半导体封装及其形成方法 Download PDF

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Publication number
CN103779319B
CN103779319B CN201310643238.1A CN201310643238A CN103779319B CN 103779319 B CN103779319 B CN 103779319B CN 201310643238 A CN201310643238 A CN 201310643238A CN 103779319 B CN103779319 B CN 103779319B
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main surface
semiconductor packages
substrate
antenna structure
antenna
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CN103779319A (zh
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G·比尔
O·盖特纳
W·哈特纳
M·波尔穆萨维
K·普雷泽尔
M·沃伊诺夫斯基
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from US13/736,553 external-priority patent/US8952521B2/en
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Priority to CN201711380861.7A priority Critical patent/CN107968084A/zh
Publication of CN103779319A publication Critical patent/CN103779319A/zh
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Abstract

本发明涉及具有集成天线的半导体封装及其形成方法。在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。芯片设置在该衬底中。该芯片包括在该第一主表面的多个接触焊盘。第一天线结构设置在该第一主表面。反射器设置在该第二表面。

Description

具有集成天线的半导体封装及其形成方法
本申请要求2012年10月19日递交的并且通过引用被合并到本文中的欧洲专利申请12007249.1的优先权。
对相关申请的交叉引用
本申请涉及下面的共同未决的和共同转让的专利申请：序号13／736097，2013年1月8日递交；和序号___，代理人案号：INF2012P51103US，2013年1月8日递交，这些申请通过引用被合并到本文中。
技术领域
本发明通常涉及半导体封装，并且更具体地涉及具有集成天线的半导体封装及其形成方法。
背景技术
近来，对在10GHz到300GHz的毫米波光谱的兴趣大大地增加。低成本高性能CMOS技术的出现为系统设计师和服务提供商开启了新视角，因为其能够以在千兆赫范围或更低范围中运行的无线电器件的相同成本结构来开发毫米波无线电器件。与可用的超宽带宽结合，这使得毫米波光谱对于支撑从所有类型的超高速数据传输、视频分布、便携式雷达、感测、检测和成像范围内的新类别的系统和应用而言比以前的更有吸引力。然而，利用这个光谱要求有设计和制造与毫米波半导体器件一起运行的可靠的、低成本的、高效的天线的能力。
在毫米波系统诸如例如用于汽车安全和舒适的雷达中，天线结构被放置在高频衬底或高频印刷电路板(HF PCB)上。诸如微带天线(例如贴片天线)的天线通常建立在这些专门的高频衬底上。HF PCB通常构造性地基于罗杰斯(Rogers)、泰康利(Taconic)或其它PTFE材料。然而，归因于这些高频衬底及其装配的额外的高费用，这样的构造增加了总体成本。
可在半导体单片微波集成电路(MMIC)上生成毫米波输出功率，MMIC还可被定位在HF PCB上。MMIC器件上的输入和输出往往匹配于特性阻抗(例如50欧姆)并与天线互连。MMIC器件和天线之间的这些互连通常涉及有损芯片／板接口(例如接合线)。
因此，存在对用于毫米波应用的高效、低费用和成本有效的天线封装的需求。
发明内容
根据本发明的实施例，半导体封装包括具有第一主表面和相对的第二主表面的衬底。第一芯片设置在衬底中。该第一芯片包括在第一主表面的多个接触焊盘。第一天线结构设置在衬底中。反射器设置在衬底中。
根据本发明的可选的实施例，半导体系统包括半导体封装和印刷电路板。该半导体封装包括衬底，衬底包括密封剂。该衬底具有第一主表面和相对的第二主表面。芯片设置在衬底中。该芯片包括在第一主表面的多个接触焊盘。第一天线结构接近于第一主表面。反射器接近于第二主表面。多个外部接触设置在第二主表面。印刷电路板具有前侧和后侧。印刷电路板包括在前侧的电耦合到该多个外部接触的接触焊盘。该前侧面对该半导体封装的第二主表面。
根据本发明的可选的实施例，形成半导体封装的方法包括形成包括嵌入在密封剂中的芯片的重构的衬底。该重构的衬底包括第一主表面和相对的第二主表面。该芯片包括在该第一主表面的多个接触焊盘。前侧再分配层形成在该重构的衬底的第一主表面上。该前侧再分配层包括天线结构。背侧再分配层形成在该重构的衬底的第二主表面之下。背侧再分配层包括反射器。
根据本发明的可选的实施例，形成半导体封装的方法包括形成具有第一主表面和相对的第二主表面的衬底。该衬底包括芯片，芯片包括在该第一主表面的多个接触焊盘。天线结构和反射器形成在衬底中。
附图说明
为了更完整地理解本发明及其优点，现在参考与附图一起作出的下面的描述，其中：
包括图1A-1C的图1图示了根据本发明的实施例的半导体封装，其中图1A图示了横截面图而图1B和1C图示了俯视截面图；
图2图示了根据本发明的可选实施例的图示了偶极天线的半导体封装的俯视截面图；
图3图示了根据本发明的可选实施例的图示了折叠的偶极天线的半导体封装的俯视截面图；
图4图示了根据本发明的可选实施例的图示了环形天线的半导体封装的俯视截面图；
图5图示了根据本发明的可选实施例的图示了回路天线的半导体封装的俯视截面图；
图6图示了根据本发明的可选实施例的图示了共面的贴片天线的半导体封装的俯视截面图；
图7图示了根据本发明的可选实施例的图示了天线阵列的半导体封装的俯视截面图；
图8图示了根据本发明的可选实施例的包括无源器件的半导体封装的俯视截面图；
图9图示了根据本发明的可选实施例的包括多个半导体芯片的半导体封装的横截面图；
图10图示了根据本发明的可选实施例的包括多个堆叠半导体芯片的半导体封装的横截面图；
包括图11A-11B的图11图示了根据本发明的可选实施例的包括散热器的半导体封装，其中图11A为横截面图而图11B为俯视图；
包括图12A-12B的图12图示了根据本发明的可选实施例的包括嵌入的散热器的半导体封装，其中图12A为半导体封装的横截面图而图12B为半导体封装的俯视图；
图13图示了根据本发明的可选实施例的包括设置在天线结构上的电介质透镜的半导体封装；
包括图14A-14F的图14图示了根据本发明的实施例的在制作的各个阶段期间的半导体封装；
图15描述了具有设置在通孔条中的集成天线的半导体封装；
图16描述了根据本发明的实施例的具有包含附加的微带线的集成天线的半导体封装；
图17图示了根据本发明的可选实施例的具有集成到通孔条中的反射器的半导体封装；
包括图18A-18B的图18图示了根据本发明的可选实施例的具有集成到一个或多个通孔条中的多维天线的半导体封装；
图19图示了根据本发明的可选实施例的具有集成到通孔条中的导向器的半导体封装；
包括图20A-20C的图20图示了根据本发明的实施例的集成到半导体封装中的天线结构的放大图；以及
包括图21A-21G的图21图示了根据本发明的实施例的在制作的各个阶段期间的半导体封装。
在不同图中的对应数字和符号一般指代对应的部分，除非另外指示。绘制这些图以清楚地图示实施例的相关方面并且这些图不一定按比例绘制。
具体实施方式
在下面详细地讨论各种实施例的制造和使用。然而，应当意识到本发明提供许多可应用的发明构思，其可体现在广泛的各种具体上下文中。讨论的具体实施例仅仅说明了用于制造和使用本发明的具体方式，并且不限制发明的范围。
集成在半导体封装中的传统天线有很多问题。在传统天线设计中，该天线集成在半导体封装的扇出区域中。在这样的传统天线设计中，反射器放置在天线之下的印刷电路板的上表面处。因此，天线的临界参数(诸如阻抗匹配、带宽、方向特性等)强烈地依赖于天线和印刷电路板(PCB)之间的距离。然而，这个距离在半导体封装的安装期间确定并且不是一个严格受控过程，导致天线的电参数中的大变化。特别地，这个距离依赖于将半导体封装与PCB贴附的回流处理、焊膏、焊球的尺寸。
此外，天线和反射器之间的距离或间隔应当不超过λ／4(这里λ表示自由空间波长)以确保在垂直于PCB的方向上的最大辐射并避免辐射的任何多重最大值(所谓的光栅波瓣)。例如，当焊球的高度大约是200μm时，这对应于80GHz时的λ／20和100GHz时的λ/15的可接受间隔。然而，天线的带宽相反地依赖于这个距离。PCB上的反射器和天线之间200μm的距离不是最佳的，因为其限制了天线可用的带宽。更大的距离对于宽带应用和减小对装配容差的敏感性是有利的。因此，使用焊球来限定间隔限制了天线的带宽。
另外，由于在印刷电路板内的反射器的放置，PCB上的宝贵基板面(real estate)被失去，否则其可被用于布线功能。另外，这样的设计约束或限制了在半导体封装和印刷电路板之间使用底层填充材料。另外，焊球被放置在半导体芯片上以改进芯片的热管理。然而，焊球消耗了不能用于其它接触的大面积的芯片表面。
在各种实施例中，本发明的实施例通过形成作为半导体封装的一侧上的薄膜层的反射器同时形成作为半导体封装的相对侧上的另一个薄膜层的天线而克服了这些和其它问题。因而，有利地，不同于传统的设计，半导体封装的厚度确定天线和反射器之间的间隔。半导体封装的厚度可被控制在比传统的焊球形成过程更高的过程容差内。半导体封装的相对侧可使用形成在半导体封装内的贯穿通孔互连。
本发明的结构实施例将使用图1描述。本发明的进一步的结构实施例将使用图2-13和再次在图15-20中描述。制作半导体封装的方法将使用图14和21描述。
包括图1A-1C的图1图示了根据本发明的实施例的半导体封装，图1A图示了横截面图而图1B和1C图示了俯视截面图。
参照图1A，半导体封装1安装在印刷电路板100上。在各种实施例中，半导体封装1包括嵌入在密封剂20内的至少一个半导体芯片10。在一个或多个实施例中，该半导体芯片10可包括任何类型的电路。在一个或多个实施例中，半导体芯片10包括用于无线通讯的集成电路芯片。在一个或多个实施例中，半导体芯片10包括用于无线通讯的天线结构的输出和／或输入。在一个或多个实施例中，半导体芯片10可以是硅芯片。在各种实施例中，半导体芯片10可以是用于微波工程过程的单片微波集成电路(MMIC)芯片。MMIC芯片可执行诸如微波混合、功率放大、低噪声放大以及高频切换的功能。MMIC芯片可以是大批量生产的并且是小尺寸的，例如从大约1mm2到大约10mm2，其例如能够实现诸如智能电话和蜂窝电话的高频器件的运行、雷达应用。
在一个或多个实施例中，半导体封装1包括耦合到半导体芯片10的集成天线结构50。在各种实施例中，天线结构50可配置用于传输／接收通讯信号给半导体芯片10。在一个或多个实施例中，天线结构50可配置为传输或接收毫米波信号。
在一个或多个实施例中，半导体封装1可包括例如晶圆级封装和嵌入的晶圆级封装。在一个或多个实施例中，晶圆级封装可以是嵌入的晶圆级球栅阵列封装。在一个或多个实施例中，半导体封装1可包括“芯片在层压片中封装(chip in laminate-package)”。如图示的，半导体芯片10被嵌入在密封剂20内，密封剂20将半导体芯片10和其它器件隔离而同时保护半导体芯片10。
半导体芯片10包括电路，该电路包括形成在第一主表面上的诸如晶体管、二极管、晶闸管和其它的有源器件。如图示的，有源器件11临近半导体芯片10的上表面形成。相比之下，半导体芯片10的底表面可不具有任何有源器件。因此，半导体芯片10的上表面包括用于连接到半导体芯片10内的器件的多个接触焊盘35。
在各种实施例中，半导体封装1包括扇出封装。嵌入的晶圆级封装是标准晶圆级封装的增强，其中封装实现在人工晶圆上。在扇出型封装中，将半导体芯片10连接到外部接触焊盘的外部接触焊盘和／或导线中的至少一些横向地定位在半导体芯片10的轮廓的外侧或至少与半导体芯片10的轮廓相交。因此，在扇出型封装中，半导体芯片10的封装的外围外侧部分通常(附加地)用于将封装电接合到诸如应用板等的外部应用。包围半导体芯片10的封装的这个外侧部分相对于半导体芯片10的覆盖区有效地扩大了封装的接触面积，因此就稍后的处理(例如第二级装配)而言导致在封装焊盘尺寸和节距方面的松弛约束。
在各种实施例中，半导体封装1包括在前侧6处的前侧再分配层61和在背侧7处的背侧再分配层71。该前侧再分配层61包括前侧绝缘层30(包括前侧再分配线40)、多个通孔焊盘60和至少一个天线结构50。因此，在前侧再分配层61中可用的传输线在半导体芯片10和天线结构50之间提供低损耗互连。对于本领域技术人员明显的是，前侧可承载以距该天线结构(未描绘)的一定距离安装到前侧再分配层61的焊盘上的附加器件。该前侧再分配层61和背侧再分配层71可由多于一个的金属层构成。
类似地，该背侧再分配层71包括背侧绝缘层55(包括再分配线)、多个外部接触65和反射器45。该反射器45改进天线的定向性使得天线主要地在垂直于半导体封装1的主表面的方向上传输。在缺少反射器45时，传输自天线的能量的相当一部分将被导向到下层印刷电路板中。
在各种实施例中，半导体封装1包括在半导体封装1的背侧7处的多个外部接触65。半导体封装1的背侧7与半导体封装1的前侧6相对，半导体封装1的前侧6临近半导体芯片10的上表面而半导体封装1的背侧7临近半导体芯片10的底表面。
半导体芯片10的上表面上的多个接触焊盘35耦合到在半导体封装1的背侧7处的多个外部接触65。在各种实施例中，半导体芯片10的上表面上的多个接触焊盘35通过前侧再分配线40和贯穿密封剂通孔70耦合到多个外部接触65。该前侧再分配线40形成在半导体芯片10的上表面上并且将多个接触焊盘35耦合到多个通孔焊盘60(也参见图1B)。该多个通孔焊盘60使用贯穿密封剂通孔70耦合到多个外部接触65。
参照1B，半导体芯片10的上表面上的多个接触焊盘35中的一些耦合到多个天线结构50。在图1B中，图示了两个天线结构50而在各种实施例中，可使用较少或较多数量的天线结构。多个接触焊盘35被用于外部电源／地和低频信号接触并且还提供机械支撑。
在各种实施例中，集成天线结构50可包括诸如平面天线的任何类型的天线。图1B图示了根据实施例的贴片天线。在可选实施例中，天线结构50可包括鞭状天线(直金属线)。在一个实施例中，天线结构50包括形成在半导体封装1的再分配层内的金属贴片。在该背侧7处的反射器45大于形成天线结构50的金属贴片并且接地。
参照图1C，多个外部接触65布置在半导体封装1的背侧7处。此外，反射器45设置在半导体封装1的背侧7处。在各种实施例中，反射器45与前侧6处的天线结构50重叠。
在一个或多个实施例中，反射器45大于形成天线结构50的金属贴片以便产生稳定模式和较低的环境敏感性。在一个或多个实施例中，该反射器45至少是天线结构50的尺寸的1.5倍。在一个或多个实施例中，该反射器45至少是天线结构50的尺寸的2倍。在一个或多个实施例中，该反射器45至少是天线结构50的尺寸的5倍。在一个或多个实施例中，该反射器45是天线结构50的尺寸的大约1.1倍到大约10倍。在一个或多个实施例中，该反射器45是天线结构50的尺寸的大约1.5倍到大约5倍。然而，在一些实施例中，该反射器45大约是天线结构50的贴片的相同尺寸或仅略微大于天线结构50的贴片(为～1.05倍)。
如图1A和1C中图示的，多个接触焊球80设置在多个外部接触65之下并延伸到半导体封装1之外。在多个外部接触65和印刷电路板100的上表面处的PCB接触焊盘110之间耦合多个接触焊球80。
类似地，多个热焊球90设置在芯片背侧之下和／或在反射器45之下。该多个热焊球90接合到印刷电路板100的上表面处的热接触焊盘120。多个热焊球90是可选的并且在一一些实施例中可不使用。
印刷电路板100包括在上表面处的PCB接触焊盘110和热接触焊盘120。该印刷电路板100包括在背表面处的背侧散热器130。热接触焊盘120通过贯穿通孔140耦合到背侧散热器130。该印刷电路板100可包括其它电路，例如用于将半导体封装1与印刷电路板100上的其它部件连接的金属线和通孔。半导体封装1的前侧再分配层61可承载以距天线结构(未描绘)的一定距离安装到前侧再分配层61的焊盘上的附加器件。在各种实施例中，前侧再分配层61和背侧再分配层71可包括多于一个金属层。在各种实施例中，多于一个芯片和／或无源器件可被嵌入到半导体封装1中。
有利地，本发明的实施例克服了传统天线设计的许多限制。例如，天线和反射器之间的距离由封装厚度设置并且对装配容差不敏感。天线和反射器之间的增加的距离(例如大于200μm)使得可能实现较宽带宽的天线。进一步，可改变半导体封装1的厚度以满足不同的天线要求并因此满足不同的毫米波应用。因此本发明的实施例能够形成具有较好的电属性的稳定天线。进一步，不同于传统的天线设计，对PCB内的布线没有约束，因为反射器没有形成在PCB内而是集成在半导体封装1内。
作为附加的优点，在半导体芯片10之下的整个区域可被用于热焊球90而不影响现在放置在硅芯片的相对侧上的片上电路。这导致更好的热消散并能够在没有损害热管理的情况下将半导体芯片10缩放到更小的尺寸。
图2图示了根据本发明的可选实施例的半导体封装的俯视截面图。图2的俯视截面图可对应于图1A中图示的切割线1B-1B。
如图2图示的，在这个实施例中天线结构50具有偶极天线。该偶极天线包括彼此平行且在同一线上定向的两个金属线，其中小间隔分离该两个金属线。
图3图示了根据本发明的可选实施例的半导体封装的俯视截面图。图3的俯视截面图可对应于图1A中图示的切割线1B-1B。
参照图3，天线结构50是折叠的偶极天线。天线结构50的末端被折叠回到中心点。这个天线结构50可具有比图2中图示的偶极天线更大的带宽。
图4图示了根据本发明的可选实施例的半导体封装的俯视截面图。图4的俯视截面图可对应于图1A中图示的切割线1B-1B。
如图4中接下来图示的，在这个实施例中，天线结构50是环形天线。在进一步的实施例中，天线结构50可以是扼流环天线。
图5图示了根据本发明的可选实施例的半导体封装的俯视截面图。图5的俯视截面图可对应于图1A中图示的切割线1B-1B。
如图5中进一步图示的，在可选实施例中，天线结构50是矩形回路天线。
图6图示了根据本发明的可选实施例的半导体封装的俯视截面图。图6的俯视截面图可对应于图1A中图示的切割线1B-1B。
如图6中进一步图示的，在可选实施例中，天线结构50可以是共面的贴片天线。
图7图示了根据本发明的可选实施例的半导体封装的俯视截面图。图7的俯视截面图可对应于图1A中图示的切割线1B-1B。
在各种实施例中，天线结构50可包括天线阵列。在各种实施例中，天线阵列可用(上面描述的)结构的任何合适的图案或阵列形成。在各种实施例中，天线阵列的天线元件可被布置为形成1维或2维图案。在各种实施例中，天线结构50可包括包含其它缝隙天线、单极天线等等的其它天线结构。
图8图示了根据本发明的可选实施例的包括无源器件的半导体封装的俯视截面图。
在各种实施例中，半导体封装1可包括设置在密封剂20(例如图1)和／或前侧再分配层61内的诸如电感器、电阻器、电容器的无源器件51。例如，在一个实施例中，无源器件51可包括设置在接近于天线结构50的前侧再分配层61中的线圈。
图9图示了根据本发明的可选实施例的包括多个半导体芯片的半导体封装的横截面图。
参照图9，在一个或多个实施例中，半导体封装1可包括多于一个半导体芯片。如图示的，第一半导体芯片10A和第二半导体芯片10B可形成在密封剂20内。在一个或多个实施例中，至少一个半导体芯片耦合到天线结构50。在一些实施例中，第一半导体芯片10A和第二半导体芯片10B二者都可被耦合到天线结构50。
图10图示了根据本发明的可选实施例的包括多个堆叠的半导体芯片的半导体封装的横截面图。
不同于先前的实施例，这个实施例可进一步包括设置在第一和第二半导体芯片10A和10B上的堆叠的半导体芯片。如图示的，第三半导体芯片11A可被设置在第一半导体芯片10A上并且第四半导体芯片11B可被设置在第二半导体芯片10B上。在各种实施例中，第三半导体芯片11A和第四半导体芯片11B可包括集成电路或分立芯片或无源器件。第三半导体芯片11A和第四半导体芯片11B可由第二密封剂320密封。第三半导体芯片11A和第四半导体芯片11B可被面朝下安装(例如第三半导体芯片11A的有源区域面对第一半导体芯片10A的有源区域)。第三半导体芯片11A和第四半导体芯片11B可通过贯穿密封剂通孔70被耦合到多个外部接触65。可选地，第三半导体芯片11A和第四半导体芯片11B可被面朝上安装并通过接合线而接合到多个通孔焊盘60。
包括图11A-11B的图11图示了根据本发明的可选实施例的包括散热器的半导体封装。图11A为横截面图而图11B为俯视图。
在各种实施例中，如图11中图示的，散热器210可被安装在半导体封装1上以高效地移除在半导体芯片10内生成的热量。贴附散热器210使得天线结构50不被阻塞。例如，散热器210可具有用于天线结构50的槽(图11B)。在一个或多个实施例中，该槽大于天线结构50以避免遮蔽效应。在各种实施例中，该槽可具有斜坡或可能3维地成形。
包括图12A-12B的图12图示了根据本发明的可选实施例的包括嵌入的散热器的半导体封装。图12A为该半导体封装的横截面图而图12B为该半导体封装的俯视图。
在这个实施例中，除了关于图11描述的散热器210之外，嵌入的散热器220设置在密封剂20内。在各种实施例中，嵌入的散热器220可包括诸如硅的半导体材料或可包括金属化材料。在各种实施例中，嵌入的散热器220可包括通孔或其它结构。在一个实施例中，该嵌入的散热器220被形成为围绕半导体芯片10的一个或多个侧壁的沟槽(也参见图12B)。在各种实施例中，嵌入的散热器220不形成在天线结构50之下以防止干扰天线的运行。在各种实施例中，该嵌入的散热器220被设计为从项侧到底侧的地或电源连接。在各种实施例中，散热器220被设计为多层金属板以提供从顶侧到底侧的地和电源连接。
图13图示了根据本发明的可选实施例的包括安装在天线结构上的电介质透镜的半导体封装。
参照图13，电介质透镜310可被设置在天线结构50上和在半导体封装1的前侧上。电介质透镜310的基部可被对齐得平行于天线结构50。电介质透镜310的侧壁可配置为改进天线结构50的定向性。在各种实施例中，电介质透镜310可具有棱锥形状、圆锥、截棱锥／截圆锥形状结构或旋转对称抛物线／更高阶的形状结构。
包括图14A-14F的图14图示了根据本发明的实施例的在制作的各个阶段期间的半导体封装。
参照图14A，形成包括半导体芯片10的重构的晶圆400。参照图14A，多个半导体芯片10被放置在载体500上。可使用常规处理例如在晶圆内形成多个半导体芯片10，该晶圆被切块以形成多个半导体芯片10。如上面描述的，可在诸如体硅衬底或绝缘体上硅(SOI)衬底的硅衬底上形成多个半导体芯片10。可选地，半导体芯片10可以是形成在碳化硅(SiC)或砷化镓(GaAs)上的器件。本发明的实施例还可包括形成在化合物半导体衬底上的器件并且可包括异质外延衬底上的器件。在一个实施例中，半导体芯片10是至少部分地形成在氮化镓(GaN)上的器件，氮化镓可以是蓝宝石或硅衬底上的GaN。
接下来，多个半导体芯片10使用粘结层510贴附到载体500。载体500在处理期间提供机械支撑和稳定性。在各种实施例中，载体500可以是粘结带、框架、由刚性材料(例如金属，诸如镍、钢或不锈钢)制造的板、层压片、薄膜或材料堆叠。
密封剂20被施加到多个半导体芯片10上并至少部分地封闭多个半导体芯片10。在一个实施例中，使用诸如压缩模塑、传递模塑过程、注射模塑、粒化模塑、粉末模塑、液态模塑的模塑过程和诸如模版印刷或丝网印刷的印刷过程来施加密封剂20。
在各种实施例中，密封剂20包括介电材料并且在一个实施例中可包括模制化合物。在其它的实施例中，该密封剂20可包括聚合物、共聚物、生物聚合物、纤维浸渍聚合物(例如树脂中的碳或玻璃纤维)、颗粒填充聚合物和其它有机材料中的一个或多个。在一个或多个实施例中，密封剂20包括不使用模制化合物形成的密封剂和诸如环氧树脂和／或硅胶的材料。在各种实施例中，密封剂20可由任何合适的硬质塑料、热塑性塑料、热固性材料或层压片制成。在一些实施例中密封剂20的材料可包括填充剂材料。在一个实施例中，该密封剂20可包括环氧树脂材料和填充材料，其包括玻璃或其它电绝缘矿物填充剂材料比如氧化铝或有机填充材料的小颗粒。该密封剂20可被固化，即经受热过程以变硬因此形成保护多个半导体芯片10的气密密封。该固化过程使密封剂20变硬由此形成保持多个半导体芯片10的单个衬底。这样的衬底称为重构的晶圆400。在各种实施例中，衬底的形式不限于晶圆并且可以是类似平板物。
在一个或多个实施例中，重构的晶圆400的厚度可被配置来改进天线的阻抗匹配和带宽。在随后步骤中形成的天线结构50和反射器45之间的间隔可由重构的晶圆400的厚度控制。在各种实施例中，重构的晶圆的厚度可从大约20μm变化高达大约2000μm。
包括图14B-1和14B-2的图14B图示了根据本发明的实施例的在制作期间从载体分离重构的晶圆之后的半导体封装。
参照图14B，移除载体500以分离重构的晶圆400或人工晶圆。密封剂20在随后的处理期间提供机械和热稳定性。在各种实施例中，在随后的处理期间，依赖于密封剂20的热稳定性，重构的晶圆400可经受高达300℃的温度。
在一个实施例中，在形成重构的晶圆400之后，如图14C中图示的，贯穿密封剂通孔70形成在密封剂20内。该贯穿密封剂通孔70可通过在密封剂20中形成开口和用导电材料填充该开口而形成。可选地，在一些实施例中，在重构的晶圆400的形成期间，可形成贯穿密封剂通孔70。例如，在一个或多个实施例中，例如硅条、PCB条或／和金属条的通孔条可在形成密封剂20之前与半导体芯片10一起放置。在各种实施例中，在直径和／或形状上，贯穿密封剂通孔70的尺寸从大约15μm到大约500μm变化，并且深度依赖于重构的晶圆的厚度。
在各种实施例中，该贯穿密封剂通孔70可由光刻和刻蚀组合或可选地由激光钻孔过程来图案化。因为贯穿密封剂通孔70被形成为嵌入介电材料(密封剂20)中，所以有利地避免额外形成围绕贯穿密封剂通孔70的介电间隔物。
前侧再分配层61形成在半导体芯片10的有源侧上。前侧绝缘层30沉积在重构的晶圆400上。接下来，前侧再分配线40和天线结构50形成在前侧绝缘层30内。在各种实施例中再分配层的数量不限于一个。
前侧绝缘层30可形成在半导体芯片10的金属化部的最后金属层级上，其可包括多个接触焊盘35。前侧绝缘层30被图案化形成再分配线和接触焊盘。在一个或多个实施例中，前侧绝缘层30可包括氧化物层或氧化物／氮化物层堆叠。在其它的实施例中，前侧绝缘层30可包括氮化硅、氮氧化硅、FTEOS、SiCOH、聚酰亚胺、光电酰亚胺、BCB或其它有机聚合物、或其组合。可选的绝缘衬垫可被形成在前侧绝缘层30上。在一个实施例中，可选的绝缘衬垫可包括氮化物层。在各种实施例中，可选的绝缘衬垫可包括FTEOS、SiO2、SiCOH或其它低k材料。使用光刻过程，前侧绝缘层30被图案化以打开最后金属层级上的接合焊盘，例如半导体芯片10的多个接触焊盘35。
例如通过沉积后面是种子层的金属衬垫(诸如例如钛、钨-钛、氮化钛或氮化钽)和电镀过程，在图案化的前侧绝缘层30中形成前侧再分配线40和天线结构50。在一个或多个实施例中，前侧再分配线40包括接受(amenable to)电镀过程的铜或导电材料。在各种实施例中，前侧再分配线40可包括多个层，在一个实施例中例如Cu／Ni、Cu／Ni／Pd／Au、Cu／NiMoP／Pd／Au或Cu／Sn。在各种实施例中，前侧再分配线40可与天线结构50同时形成。
接下来参照图14D，背侧再分配层71形成在重构的晶圆的背侧之下。如图14D中图示的，前侧再分配线40在随后的处理期间可被绝缘材料层覆盖。这个绝缘材料层可以是能够互连装配在前侧再分配层61之上的附加器件的图案。
背侧绝缘层55被沉积在重构的晶圆400之下。多个外部接触65形成在背侧绝缘层55内。背板(例如反射器45)形成在半导体芯片10的下面以便重叠天线结构50。在各种实施例中，多个外部接触65和反射器45在背侧再分配线形成期间使用共同的电镀过程来形成。在各种实施例中，在前侧和背侧处的诸如前侧再分配层61和背侧再分配层71的再分配层的数量可以更多并且可以不限于一个，一个仅用于图示。
如接下来图14E中图示的，焊球被形成在背侧再分配层71之下。多个接触焊球80形成在多个外部接触65之下。多个热焊球90形成在反射器45之下。
如由箭头图示的，重构的晶圆400被切块以形成个体的半导体封装1。在一个或多个实施例中，可使用机械锯开过程或激光切块过程执行该切块。该半导体封装1包括多个外部接触65用于形成外部接触。因此形成的该半导体封装1可在随后的封装之前被测试。例如，测试探针可被施加到多个外部接触65上以标识缺陷单元。
在一些实施例中因此形成的半导体封装1可被直接使用并且安装在电路板上。在其它的实施例中，半导体封装1可被进一步封装在引线框、接线柱框(clip frame)和其它合适的衬底上以形成半导体模块。本发明的实施例包括形成例如与JEDEC标准兼容的任何合适类型的封装。示例包括晶体管轮廓封装、小轮廓封装、薄小轮廓封装、薄收缩小轮廓封装、单列直插式封装、BGA和其它。
参照图14F，在一个或多个实施例中，半导体封装1被安装到印刷电路板100上。多个热焊球90可被贴附到印刷电路板100上的热接触焊盘而多个接触焊球80被贴附到PCB接触焊盘110。
根据本发明的实施例将被描述具有集成天线结构的半导体封装的可选的结构实施例。
图15描述了根据本发明实施例的具有设置在通孔条中的集成天线的半导体封装。
参照图15，半导体封装1被安装在印刷电路板100上。在各种实施例中，半导体封装1包括嵌入在密封剂20内的半导体芯片10。在一个或多个实施例中，半导体封装1包括耦合到半导体芯片10的集成天线结构50。
在各种实施例中，半导体封装1包括在前侧6处的前侧再分配层61。该前侧再分配层61包括前侧绝缘层30，前侧绝缘层30包括前侧再分配线40。
至少一个天线结构50设置在通孔条450中，通孔条450被设置在密封剂20中。在各种实施例中，该通孔条450是嵌入在密封剂20内的结构并且可在上述的重构的晶圆的形成期间形成。因此，通孔条450可包括许多不同的结构。在一个或多个实施例中，通孔条450可包括硅条、PCB通孔条或任何其它具有在其中形成用于天线结构的金属化部的衬底。
在各种实施例中，通孔条450可以类似PCB的方式制造。在各种实施例中，通孔条450可包括像层压片、陶瓷、热固性塑料、密封剂、热塑性塑料或其它材料的衬底材料。在一个或多个实施例中，通孔条450的结构可包括模拟PCB或薄膜技术。在各种实施例中，通孔条450是如使用图14所描述的嵌入的“类似芯片物”。
通孔条450通过前侧再分配层61耦合到半导体芯片10。因此，前侧再分配层61中可用的传输线在半导体芯片10和天线结构50之间提供低损耗互连。反射器45设置在半导体封装1的前侧6处。在各种实施例中，反射器45在前侧6处重叠天线结构50。在图15中通过箭头图示了来自天线结构50的辐射。在这个实施例中，嵌入的通孔条450被对齐得垂直于半导体芯片10的主平面，使得辐射的方向垂直于前侧6。因此，辐射的方向类似于先前的实施例，例如，图1A中描述的。
在各种实施例中，通孔条450可包括任何合适的天线图案。例如，在一个或多个实施例中，可在通孔条450处形成维瓦尔第(vivaldi)天线阵列。如先前的实施例中所描述的，在进一步的实施例中，电介质透镜可被安装在半导体封装1上以进一步聚焦天线辐射。进一步，在一些实施例中，天线结构50在通孔条450内可以不同的角度被定向。
图16描述了根据本发明实施例的具有集成天线的半导体封装，该集成天线具有附加的微带线。
在图16中，第二馈送线42被用于馈送天线结构50。因此，辐射特性中的归因于第一馈送线41的任何不对称性可被最小化。
图17图示了根据本发明的可选实施例的具有集成到通孔条中的反射器的半导体封装。
图17图示了示出在沿半导体封装的前侧6的方向上的辐射的可选实施例。例如，在一个或多个实施例中，天线结构50可以是偶极或贴片天线结构。在这个实施例中反射器45可被包括在通孔条450内。有利地，为了最小化吸收，具有天线结构50的通孔条450可被放置得接近半导体封装1的边缘。
包括图18A和18B的图18图示了具有集成到半导体封装中的一个或多个通孔条中的多维天线的半导体封装的进一步实施例。
这个实施例组合图16和17中描述的实施例以形成三维天线。因此，在图18A中图示的实施例中，天线结构50可以能够在多个方向上辐射。参照图18B，在一个或多个实施例中，通孔条450可包括天线结构50，天线结构50包括第一轴天线50A、第二轴天线50B和第三轴天线50C。在各种实施例中，这个功能可被分成个体的通孔条或／和可与上面描述的(图1-11)天线结构组合。这样的三维天线结构可有利地用于场感测或能量传递。
图19图示了根据本发明的可选实施例的具有集成到平行于表面6设置的通孔条中的无源天线／导向器的半导体封装。
在另一个实施例中，天线结构50可被放置在半导体封装1的前侧6上，其中无源天线结构145设置在通孔条450上的相对侧上。反射器45可形成在印刷电路板100上。
包括图20A-20C的图20图示了根据发明实施例的集成到半导体封装中的天线结构的放大图。
图20A图示了在本发明的一个实施例中的单个天线结构50，单个天线结构50放置在密封剂中并且通过第一和第二馈送线41和42被耦合。图20B图示了示出由单个天线的阵列形成的天线结构50的可选的实施例。图20C图示了示出具有第一轴天线50A和第二轴天线50B的天线结构50的可选实施例。
包括图21A-21G的图21图示了根据本发明实施例的在制作的各个阶段期间的半导体封装。
参照图21A，可在分离的衬底中个体地制作包括天线结构的通孔条。例如，在第一通孔条衬底501中的第一天线结构500A可使用平面制作技术诸如印刷电路板制作方法和／或薄膜图案化技术来制作。第一通孔条衬底501被单颗化以形成如图21B中图示的第一通孔条511。在一些实施例中，例如，在与在其上形成第一天线结构500A的侧相对的背侧上，第一通孔条衬底501可包括另一一个天线结构。
在一个或多个实施例中，不同的天线结构可在不同的衬底中制作。如图21C中示出的，第二天线结构500B可在第二通孔条衬底502内形成，第二通孔条衬底502被单颗化以形成如图21D中图示的第二通孔条512。类似地，如图21E中示出的，第三天线结构500C可在第三通孔条衬底503内形成，第三通孔条衬底503被单颗化以形成如图21F中图示的第三通孔条513。
参照图21G，可形成包括半导体芯片10、第一通孔条511、第二通孔条512和第三通孔条513的重构的晶圆400。多个半导体芯片10被放置在载体500上。
依赖于预期的天线结构的定向性，一个或多个通孔条可在放置到载体500上之前被旋转。多个第一通孔条511、多个第二通孔条512和多个第三通孔条513相应地放置在载体500上。如图示的，多个第二通孔条512和多个第三通孔条513被旋转。接下来，多个半导体芯片10、多个第一通孔条511、多个第二通孔条512和多个第三通孔条513使用粘结层510贴附到载体500。
密封剂20被施加到多个半导体芯片10、多个第一通孔条511、多个第二通孔条512和多个第三通孔条513上。密封剂20可被固化以形成重构的晶圆400。后续的处理可如使用图14图示和描述的那样进行。因此，在各种实施例中，可以使用一个或多个通孔条来合并不同的天线结构。
虽然已参照说明性的实施例描述了本发明，但是这本描述不意图被解释成限制的意义。在参考本描述后，本发明的说明性实施例以及其它实施例的各种修改和组合对于本领域技术人员来说将是显而易见的。作为说明，图1-21中描述的实施例可彼此结合在一个或多个实施例中。因此意图是附加的权利要求书包括任何这样的修改或实施例。
尽管本发明及其优点已被详细地描述，但是应当理解，在不脱离由附加的权利要求书限定的本发明的精神和范围的情况下，本文中可做出各种改变、替换和变更。例如，本领域技术人员将容易理解，这里描述的许多特征、功能、过程和材料可以变化同时保持在本发明的范围内。
而且，本申请的范围不意图限制到说明书中描述的过程、机器、制造、物质组成、手段、方法和步骤的特定实施例。作为一个本领域普通技术人员从本发明的公开内容中将容易理解，根据本发明，可利用与本文中描述的对应实施例执行基本上相同功能或获得基本上相同结果的目前存在的或以后发展的过程、机器、制造、物质组成、手段、方法或步骤。因此，附加的权利要求意图在其范围内包括这样的过程、机器、制造、物质组成、手段、方法或步骤。

Claims (24)

1.一种半导体封装，包括：
具有第一主表面和相对的第二主表面的衬底；
设置在该衬底中的第一芯片，该第一芯片包括在该第一主表面的多个接触焊盘；
设置在该衬底中的第一天线结构；
形成在该第二主表面之下的背侧再分配层；
设置在该衬底中的反射器；以及
设置在该反射器上的多个热焊球；
其中所述第一天线结构设置在该第一主表面；
其中所述反射器设置在该第二主表面；
其中多个外部接触和背侧绝缘层设置在该第二主表面，所述背侧绝缘层、所述多个外部接触和所述反射器被包括在形成在该第二主表面之下的同一个背侧再分配层。
2.根据权利要求1所述的半导体封装，进一步包括：
围绕该第一芯片的侧壁设置的密封剂，该密封剂形成该衬底；以及
设置在该密封剂中并耦合到该多个接触焊盘的贯穿密封剂通孔。
3.根据权利要求2所述的半导体封装，进一步包括设置在该第一主表面上的再分配层，其中该贯穿密封剂通孔通过该再分配层而耦合到该多个接触焊盘，并且其中该天线结构是该再分配层的部分。
4.根据权利要求3所述的半导体封装，进一步包括设置在该再分配层中的第二天线结构。
5.根据权利要求2所述的半导体封装，进一步包括设置在该密封剂中接近该第一芯片的嵌入的散热器。
6.根据权利要求1所述的半导体封装，其中该第一天线结构包括偶极天线、折叠的偶极天线、环形天线、矩形回路天线、贴片天线或共面的贴片天线。
7.根据权利要求1所述的半导体封装，其中该第一天线结构包括天线阵列。
8.根据权利要求1所述的半导体封装，进一步包括第二芯片，该第二芯片包括接近该第一芯片设置的有源器件和/或无源器件。
9.根据权利要求1所述的半导体封装，其中该天线结构包括配置为在垂直于该第一主表面的方向上发射辐射的部件。
10.根据权利要求9所述的半导体封装，进一步包括第二天线结构，其中该第一天线结构包括配置为在垂直于该第一主表面的第一方向上发射辐射的第一部件；并且其中该第二天线结构包括用于在平行于第一主表面的第二方向上发射辐射的第二部件。
11.根据权利要求1所述的半导体封装，进一步包括设置在该第一芯片上的散热器。
12.根据权利要求1所述的半导体封装，进一步包括设置在该第一天线结构上的电介质透镜。
13.根据权利要求1所述的半导体封装，进一步包括：
设置在该衬底中的第一通孔条，其中该第一天线结构设置在该第一通孔条内。
14.根据权利要求13所述的半导体封装，进一步包括设置在该第一通孔条内的第二天线结构。
15.根据权利要求13所述的半导体封装，进一步包括：
设置在该衬底中的第二通孔条；
设置在该第二通孔条内的第二天线结构；以及
设置在该封装中的第三天线结构。
16.一种半导体系统，包括：
半导体封装，包括：
包括密封剂的衬底，该衬底具有第一主表面和相对的第二主表面，
设置在该衬底中的芯片，该芯片包括在该第一主表面的多个接触焊盘，
接近该第一主表面的第一天线结构，
接近该第二主表面的反射器，
在该第二主表面的背侧绝缘层；以及
在该第二主表面的多个外部接触，
其中所述背侧绝缘层、所述多个外部接触和所述反射器被包括在形成在该第二主表面之下的同一个背侧再分配层；
具有前侧和背侧的印刷电路板，该印刷电路板包括：
在该前侧处的电耦合到该多个外部接触的接触焊盘，其中该前侧面对该半导体封装的该第二主表面；以及
设置在该反射器上的多个热焊球，其中该半导体封装至少通过使用该多个热焊球而贴附到该印刷电路板。
17.根据权利要求16所述的半导体系统，其中该印刷电路板进一步包括：
在该前侧处的热耦合到该衬底的该第二主表面的热接触焊盘；
设置在该印刷电路板的该背侧处的背板；以及
将该热接触焊盘与该背板耦合的多个贯穿通孔。
18.根据权利要求16所述的半导体系统，进一步包括设置在该密封剂中并耦合到该多个接触焊盘的贯穿密封剂通孔，其中该密封剂围绕该芯片的侧壁设置。
19.一种形成半导体封装的方法，该方法包括：
形成包括嵌入在密封剂中的第一芯片的重构的衬底，该重构的衬底包括第一主表面和相对的第二主表面，该第一芯片包括在该第一主表面的多个接触焊盘；
在该重构的衬底的该第一主表面上形成前侧再分配层，该前侧再分配层包括天线结构；
在该重构的衬底的该第二主表面之下形成背侧再分配层，该背侧再分配层包括反射器；以及
在该反射器上形成多个热焊球；
其中形成该背侧再分配层包括在第二主表面形成多个外部接触和背侧绝缘层。
20.根据权利要求19所述的方法，进一步包括在该重构的衬底的密封剂中嵌入通孔条、无源器件和/或管芯。
21.根据权利要求19所述的方法，其中形成该重构的衬底包括在该密封剂中嵌入散热器。
22.根据权利要求19所述的方法，进一步包括在该天线结构上形成电介质透镜。
23.一种形成半导体封装的方法，该方法包括：
形成具有第一主表面和相对的第二主表面的衬底，该衬底包括第一芯片，该第一芯片在该第一主表面包括多个接触焊盘；
在该衬底中形成第一天线结构；
在该衬底中形成反射器；以及
在该反射器上形成多个热焊球；
其中形成该第一天线结构包括在第一主表面的第一再分配层内形成该第一天线结构；
其中形成该反射器包括在该第二主表面的第二再分配层内形成该反射器，所述第二再分配层包括多个外部接触。
24.根据权利要求23所述的方法，其中形成该第一天线结构包括在通孔条内形成该第一天线结构，该通孔条被形成在该衬底内。
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