WO2019033608A1 - 雷达组件封装体及其制造方法 - Google Patents

雷达组件封装体及其制造方法 Download PDF

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Publication number
WO2019033608A1
WO2019033608A1 PCT/CN2017/113113 CN2017113113W WO2019033608A1 WO 2019033608 A1 WO2019033608 A1 WO 2019033608A1 CN 2017113113 W CN2017113113 W CN 2017113113W WO 2019033608 A1 WO2019033608 A1 WO 2019033608A1
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Prior art keywords
insulator
chip
antenna
millimeter wave
wave radar
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PCT/CN2017/113113
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English (en)
French (fr)
Inventor
张文奇
陈�峰
Original Assignee
华进半导体封装先导技术研发中心有限公司
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Priority claimed from CN201710709853.6A external-priority patent/CN107546181B/zh
Priority claimed from CN201710717924.7A external-priority patent/CN107479034B/zh
Application filed by 华进半导体封装先导技术研发中心有限公司 filed Critical 华进半导体封装先导技术研发中心有限公司
Priority to US16/080,655 priority Critical patent/US11346920B2/en
Publication of WO2019033608A1 publication Critical patent/WO2019033608A1/zh

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    • G—PHYSICS
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    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention generally relates to the field of semiconductor fabrication, and more particularly to a millimeter wave radar component package and a method for fabricating such a millimeter wave radar component package.
  • a packaged millimeter wave radar transceiver assembly is disclosed in the Chinese Patent Application No. 201510149446.5, which is incorporated herein by reference.
  • the components including the millimeter wave radar chip and the antenna are arranged on the inner surface of the casing in a wire bonding manner, and a cavity is formed between the casing and the cover.
  • the packaged millimeter wave radar transceiver assembly has the disadvantage that it uses a wire bonding method to arrange the chip, which not only causes the line length to be too long and thus causes a large loss, but also needs to reserve a certain height in the box body for use.
  • the wire is bonded to the wire, resulting in a larger thickness of the assembly.
  • the packaged millimeter wave radar transceiver assembly is manufactured using a conventional packaging process including patching, wire bonding, and substrate fabrication steps, such that the thickness of the substrate and chip limits the further reduction in thickness of the component.
  • the object of the present invention is to provide a millimeter wave radar component package and a method for manufacturing such a millimeter wave radar component package, by which the loss can be reduced and the thickness of the package can be greatly reduced .
  • a millimeter wave radar component package comprising: a lid having a metal layer disposed on an inner surface of the lid, The metal layer is opposite the aperture of the case, wherein a cavity is formed between the cover and the case;
  • the first insulator is connected to the cover, wherein a hole is opened in the first insulator, one end of the hole corresponds to the position of the antenna and the other end is in communication with the cavity;
  • One or more chips arranged in a flip-chip manner on the second insulator and covered by the first insulator;
  • An antenna and a conductive line are disposed in the third insulator and connected to the pad of the chip through the second insulator, wherein the conductive trace is exposed from the third insulator for electrical contact.
  • a millimeter wave radar component package comprising:
  • a lid having a metal layer disposed on an inner surface of the lid, the metal layer being opposite the orifice of the cartridge, wherein a cavity is formed between the lid and the cartridge;
  • the first insulator is connected to the cover, wherein a hole is opened in the first insulator, one end of the hole corresponds to the position of the antenna and the other end is in communication with the cavity;
  • One or more chips arranged in a flip-chip manner on the second insulator and covered by the first insulator;
  • An antenna and a conductive line disposed in the third insulator and connected to the pad of the chip through the second insulator, wherein between the antenna and the pad and between the conductive line and the pad, respectively A metal barrier layer and the conductive traces are exposed from the third insulator for electrical contact.
  • the millimeter wave radar component package according to the present invention has at least the following advantages: (1) The millimeter wave radar package according to the present invention has a lower loss because the millimeter wave radar package according to the present invention is arranged in a flip chip manner Chip, thereby reducing the length of the line, thereby reducing the loss; (2) in the present invention, by burying the chip, the antenna and the conductive line into the corresponding insulator of the case, the thickness of the entire package can be reduced; 3) In the present invention, since the chip, the antenna, and the conductive line are buried in the corresponding insulator of the case and the conductive line is exposed (ie, Fan Out package), the substrate can be omitted, thereby further reducing The thickness of the package.
  • the chip further comprises a solder ball or other metal connector which is arranged on the third insulator and which is electrically connected to the electrically conductive line.
  • a solder ball or other metal connector is electrically connected to the conductive line through a portion of the third insulator.
  • the function of the solder balls or other metal connectors is to interconnect the conductive traces of the millimeter wave radar component package with other external devices, such as another substrate.
  • the chip comprises:
  • a millimeter wave radar chip comprising a receiving chip, a radar transmitting chip, and/or a radar transceiver chip;
  • driver chip multifunction chip
  • final stage power amplifier low noise amplifier
  • limiter limiter
  • preselection filter RF switch
  • drive control circuit power supply modulation for each chip operation timing Circuits, and power management circuits for voltage conversion.
  • the millimeter wave radar chip and related functional chips can be integrated in the same package, thereby achieving improved integration.
  • the cover is made of polytetrafluoroethylene.
  • Polytetrafluoroethylene has a lower dielectric constant and is therefore suitable as a material for the lid.
  • the antenna has titanium, copper, nickel, aluminum, silver, gold or an alloy thereof, and the shape of the antenna is circular, square or irregular.
  • the size of the tunnel is smaller than the size of the antenna.
  • the arrangement of the channels is to facilitate the reception and transmission of signals by the antenna.
  • the holes can be made by drilling, etching, chemical etching, photolithography, and the like.
  • the first insulator, the second insulator and the third insulator are made of the same or different insulating material. With this expansion, the materials of the first, second and third insulating layers can be flexibly selected to achieve the corresponding characteristics.
  • the metal barrier layer has TiCu or TiWCu and has a thickness of from 1 to 10 ⁇ m.
  • the metal barrier layer functions to act as an etch stop layer when etching the second insulator or starting the via, and further to achieve electrical contact between the die pad and the antenna and the conductive trace.
  • the metal layer faces the bore.
  • paired means that the center of the tunnel and the center of the metal layer are collinear in the thickness direction of the package.
  • an optimal antenna signal transmission and reception can be ensured.
  • the metal layer does not have to be facing the channel.
  • the metal layer may be offset from the channel by a distance in the thickness direction of the package.
  • the metal layer has titanium, copper, nickel, tungsten, silver, gold or an alloy thereof. With this extension, good reception and transmission of the antenna signal can be achieved.
  • the aforementioned task is solved by a method for manufacturing a millimeter wave radar component package, the method comprising the steps of:
  • forming a lid wherein a metal layer is formed on the inner surface of the lid, the position of the associated metal layer corresponding to the position of the tunnel;
  • the method according to the invention likewise has the advantage of a package according to the invention, namely reducing losses and reducing the thickness of the package.
  • the method further comprises the step of:
  • Solder balls are disposed in a portion of the third insulator that is removed for electrical contact with the conductive traces, the solder balls being electrically connected to the conductive traces.
  • the conductive interconnection of the package with other substrates can be achieved. It should be noted here that the arrangement of the solder balls on the package is not necessary, and in other embodiments, the pads may be arranged or placed on another substrate to be interconnected.
  • step i is carried out in a vacuum or that a protective gas is filled in the cavity.
  • the vacuum or the cavity filled with the protective gas can provide the air-tight environment required for the internal bare chips to work reliably for a long time, and at the same time, it acts as an electromagnetic shield. With this preferred solution, good antenna signal transmission and reception can be achieved. It should be noted, however, that the vacuum environment and shielding gas in the cavity are not necessary. Conversely, the cavity of the millimeter wave radar component package of the present invention may also be filled with air.
  • Figure 1 shows a schematic view of a millimeter wave radar component package in accordance with the present invention
  • FIG. 2 shows a flow of a method for manufacturing a millimeter wave radar component package in accordance with the present invention
  • Figure 3 shows a schematic view of a millimeter wave radar component package in accordance with the present invention
  • FIGS. 4a-4i show schematic views of a package when the steps of the method for fabricating a millimeter wave radar component package in accordance with the present invention are completed.
  • FIG. 1 shows a schematic diagram of a millimeter wave radar component package 100 in accordance with the present invention.
  • a millimeter wave radar module package 100 includes a cover 101 and a case 102.
  • the lid 101 may be made of a material having a low dielectric constant such as polytetrafluoroethylene.
  • a metal layer 103 is disposed on the inner wall of 101, which is made of, for example, titanium, copper, nickel, tungsten, silver, gold or alloys thereof. By arranging the metal layer 103, the channel 106 can be combined to facilitate the transmission and reception of signals by the antenna 112.
  • a cavity 108 is formed between the lid 101 and the casing 102, and the cavity 108 may be vacuum or may be filled with a protective gas.
  • the vacuum or the cavity 108 filled with the shielding gas can provide a hermetic environment required for the internal bare chips 107 to operate reliably for a long time, and at the same time function as an electromagnetic shield. It should be noted, however, that the vacuum environment and shielding gas in the cavity 108 are not required.
  • the cavity 108 of the millimeter wave radar module package 100 of the present invention may also be filled with air.
  • the case 102 has a first insulator 104, a second insulator 105, and a third insulator 110 which are sequentially arranged in the thickness direction of the chip.
  • the first insulator 104, the second insulator 105, and the third insulator 110 may be made of, for example, the same or different insulating materials such as an insulating resin.
  • the first insulator 104 is connected to the cover 101, wherein a hole 106 is opened in the first insulator 104, one end of which corresponds to the position of the antenna 112 and the other end communicates with the cavity 108.
  • By providing the channel 106 it is advantageous for the antenna 112 to transmit and receive wireless signals.
  • the tunnel 106 can be fabricated by drilling, etching, chemical etching, photolithography, and the like.
  • the metal layer 103 may preferably be disposed opposite the cells 106.
  • the term "paired" means that the center of the cell 106 and the center of the metal layer 103 are substantially collinear in the thickness direction of the package 100. With such a facing arrangement, optimal antenna signal transmission and reception can be ensured.
  • the metal layer 103 need not necessarily face the cell 106.
  • the metal layer 103 may be offset from the cell 106 by a distance in the thickness direction of the package.
  • the cartridge 102 also has one or more chips 107 that are flip-chip mounted on the second insulator 105 and covered by the first insulator 104.
  • the chip 107 includes a millimeter wave radar chip and other functional chips.
  • the millimeter wave radar chip has, for example, a transmitting end (Tx) and a receiving end (Rx), and the transmitting end and the receiving end are electrically connected to the antenna 112.
  • the casing 102 also has an antenna 112 and a conductive line 113 disposed in the third insulator 110 and connected to the pad 109 of the chip 107 through the second insulator 105, wherein the conductive line 113 is from the third The insulator 110 is exposed for electrical contact.
  • the millimeter wave radar package 100 according to the present invention has at least the following advantages: (1) The millimeter wave radar package 100 according to the present invention has a lower loss because the millimeter wave radar package 100 according to the present invention is flipped The chip is arranged in a manner to reduce the length of the line, thereby reducing the loss; (2) in the present invention, by embedding the chip 107, the antenna 112, and the conductive line 113 into the case 101 The corresponding insulator, in particular, the antenna 112 is disposed in the first insulator 104, and the antenna 112 and the conductive line 113 are disposed in the second and third insulators 105, 110 (ie, the redistribution layer RDL), which can reduce the entire The thickness of the package 100; (3) In the present invention, since the chip 107, the antenna 112, and the conductive line 113 are buried in the corresponding insulator of the case 102 and the conductive line 113 is exposed (ie, Fan Out package) In this way, the substrate can be omitted
  • FIG. 2 shows a flow of a method for manufacturing a millimeter wave radar component package 100 in accordance with the present invention.
  • one or more chips 107 are mounted on the temporary bonding layer 115 of the carrier 116 by flip-chip mounting.
  • the chip 107 is covered with a first insulator 104 by plastic sealing to form the case 102 and the carrier 116 and the temporary bonding material 115 are removed to expose the pads 109 of the chip 107.
  • a second insulator 105 is applied over the first insulator, and a portion of the second insulator 105 is removed to expose the pads 109 of the chip 107.
  • the antenna 112 and the conductive line 113 are disposed on the second insulator 105, and the antenna 112 and the conductive line 113 are connected to the pad 109 of the chip 107.
  • a third insulator 110 is coated on the surface of the second insulator 105 of the cartridge 102, and a portion of the third insulator 110 is removed for electrical contact with the conductive traces 113.
  • This step 210 optionally includes disposing solder balls 114 in portions of the third insulator 110 that are removed for electrical contact with the conductive traces 113, the solder balls 114 being electrically coupled to the conductive traces 113.
  • a tunnel 106 is formed on the surface of the casing 102 facing away from the third insulator 110, one end of which corresponds to the position of the antenna 112, and the other end is outwardly communicated.
  • the depth of the tunnel 106 may be through the first insulator 104 up to the second insulator 105.
  • a lid 101 is formed in which a metal layer 103 is formed on the inner surface of the lid 101, and the position of the associated metal layer 103 corresponds to the position of the tunnel 106.
  • the lid 101 is joined to the surface of the cartridge 102 facing away from the third insulator 110, wherein a cavity 108 is formed between the lid 101 and the cartridge 102.
  • FIG. 3 shows a schematic diagram of a millimeter wave radar component package 300 in accordance with the present invention.
  • the millimeter wave radar component package 300 includes a cover 301 and a case Body 302.
  • the lid 301 may be made of a material having a low dielectric constant such as polytetrafluoroethylene.
  • a metal layer 303 made of, for example, titanium, copper, nickel, tungsten, silver, gold or alloys thereof.
  • a cavity 308 is formed between the lid 301 and the casing 302, and the cavity 308 may be vacuum or may be filled with a protective gas.
  • the vacuum or cavity 308 filled with the shielding gas can provide a hermetic environment required for the internal bare chips 307 to operate reliably for a long period of time, while at the same time functioning as an electromagnetic shield. It should be noted, however, that the vacuum environment and shielding gas in the cavity 308 are not necessary.
  • the cavity 308 of the millimeter wave radar module package 300 of the present invention may also be filled with air.
  • the case 302 has a first insulator 304, a second insulator 305, and a third insulator 310 which are sequentially arranged in the thickness direction of the chip.
  • the first insulator 304, the second insulator 305, and the third insulator 310 may be made of, for example, the same or different insulating materials such as an insulating resin.
  • the first insulator 304 is coupled to the lid 301, wherein a bore 306 is defined in the first insulator 304, one end of the bore 306 corresponding to the position of the antenna 312 and the other end being in communication with the cavity 308. By providing the tunnel 306, it is possible to facilitate the transmission and reception of wireless signals by the antenna 312.
  • the tunnel 306 can be fabricated by drilling, etching, chemical etching, photolithography, and the like.
  • Metal layer 303 may preferably be disposed opposite apertures 306.
  • the term "paired" means that the center of the tunnel 306 and the center of the metal layer 303 are substantially collinear in the thickness direction of the package 300. With such a facing arrangement, optimal antenna signal transmission and reception can be ensured.
  • the metal layer 303 need not necessarily face the via 306.
  • the metal layer 303 may be offset from the via 306 by a distance in the thickness direction of the package.
  • the case 302 also has one or more chips 307 which are arranged in a flip-chip manner on the second insulator 305 and are covered by the first insulator 304.
  • the chip 307 includes a millimeter wave radar chip and other functional chips.
  • the millimeter wave radar chip has, for example, a transmitting end (Tx) and a receiving end (Rx), and the transmitting end and the receiving end are electrically connected to the antenna 312.
  • the casing 302 also has an antenna 312 and a conductive line 313 disposed in the third insulator 310 and connected to the pad 309 of the chip 307 through the second insulator 305, wherein the antenna 312 and the solder are respectively
  • a metal barrier layer 311 is disposed between the disks 309 and between the conductive traces 313 and the pads 309, and the conductive traces 313 are exposed from the third insulator 310 for electrical contact.
  • the metal barrier layer 311 functions to etch when etching the second insulator 305 and opening the via 306.
  • the metal barrier layer 311 should be deposited on the pad 309 of the chip 307 and at the location on the first insulator 304 where the via 307 should be opened, wherein the metal barrier layer 311 acts as an etch stop layer at these locations in order to achieve The desired etch depth.
  • the metal barrier layer 311 also enables electrical contact between the pads 109 of the chip 307 and the antenna 312 and conductive lines 313.
  • the metal barrier layer may have, for example, TiCu or TiWCu, and may have a thickness of 1-10 ⁇ m.
  • the millimeter wave radar package 300 according to the present invention has at least the following advantages: (1) The millimeter wave radar package 300 according to the present invention has a lower loss because the millimeter wave radar package 300 according to the present invention is flipped The chip is arranged in a manner to reduce the length of the line, thereby reducing the loss; (2) in the present invention, by embedding the chip 307, the antenna 312, and the conductive line 313 into the corresponding insulator of the case 301, specifically Arranging the antenna 312 in the first insulator 304, arranging the antenna 312 and the conductive line 313 in the second and third insulators 305, 310 (ie, the redistribution layer RDL), the thickness of the entire package 300 can be reduced; In the present invention, since the chip 307, the antenna 312, and the conductive line 313 are buried in the corresponding insulator of the case 302 and the conductive line 313 is exposed (ie, fan out), the substrate can be omitted. This further reduces the thickness of the
  • FIGS 4a-4f show schematic views of the package when the steps of the method for fabricating the millimeter wave radar component package 300 in accordance with the present invention are completed.
  • Figure 4a shows a schematic view of the package 300 when step a of the method is completed.
  • one or more chips 307 are mounted on the temporary bonding layer 315 of the carrier 316 by flip-chip mounting.
  • Figure 4b shows a schematic of the package 300 when step b of the method is completed.
  • the chip 307 is covered with a first insulator 304 by plastic sealing to form the case 302 and the carrier 316 and the temporary bonding material 315 are removed to expose the pads 309 of the chip 307.
  • Figure 4c shows a schematic of the package 300 when step c of the method is completed.
  • a metal barrier layer 311 is deposited on the surface of the pad 309 of the case 302, and the excess metal barrier layer 311 is removed.
  • the metal barrier layer 311 functions as an etch stop layer when etching the second insulator 305 and opening the via 306. Therefore, the metal barrier layer 311 should be deposited on the pad 309 of the chip 307 and the via 307 should be opened on the first insulator 304.
  • the metal barrier layer 311 can be formed by sputtering, plating, etching, or the like.
  • Figure 4d shows a schematic of the package 300 when step d of the method is completed.
  • a second insulator 305 is applied on the surface of the barrier layer 311 of the case 302, and a portion of the second insulator 305 is removed to expose the pad 309 of the chip 307.
  • Figure 4e shows a schematic view of the package 300 when step e of the method is completed.
  • an antenna 312 and a conductive line 313 are disposed on the second insulator 305, and the antenna 312 and the conductive line 313 are connected to the pad 309 of the chip 307.
  • the antenna 312 and the conductive line 313 are connected to the pad 309 through the metal barrier layer 311.
  • Figure 4f shows a schematic view of the package 300 when step f of the method is completed.
  • a third insulator 310 is applied on the surface of the second insulator 305 of the casing 302, and a portion of the third insulator 310 is removed for electrical contact with the conductive traces 313.
  • This step f optionally includes disposing solder balls 314 in a portion of the third insulator 310 that is removed for electrical contact with the conductive traces 313, the solder balls 314 being electrically connected to the conductive traces 313.
  • Figure 4g shows a schematic of the package 300 when the step g of the method is completed.
  • a via 306 is formed on the surface of the case 302 facing away from the third insulator 310 and the metal barrier layer 311 at the bottom of the via 306 is removed, one end of the via 306 corresponding to the position of the antenna 312, and the other end Connected outwards.
  • the depth of the tunnel 306 may be through the first insulator 304 and the metal barrier layer 311 up to the second insulator 305.
  • Figure 4h shows a schematic of the package 300 when the step h of the method is completed.
  • a lid 301 is formed in which a metal layer 303 is formed on the inner surface of the lid 301, and the position of the associated metal layer 303 corresponds to the position of the tunnel 306.
  • Figure 4i shows a schematic view of the package 300 when step i of the method is completed.
  • the lid 301 is engaged with the surface of the cartridge 302 facing away from the third insulator 310, wherein a cavity 308 is formed between the lid 301 and the cartridge 302.

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Abstract

一种毫米波雷达组件封装体，包括：盒盖(101)，其具有布置在盒盖(101)的内表面上的金属层(103)，其中在盒盖(101)与盒体(102)之间形成空腔(108)；以及盒体(102)，其具有：第一绝缘体(104)，其与盒盖(101)连接，其中在第一绝缘体(104)中开设有孔道(106)，孔道(106)的一端与天线(112)的位置相对应并且另一端与空腔(108)连通；一个或多个芯片(107)，芯片(107)以倒装方式布置在第二绝缘体(105)上并且被第一绝缘体(104)覆盖；第二绝缘体(105)；第三绝缘体(110)；以及天线(112)和导电线路(113)，天线(112)和导电线路(113)布置在第三绝缘体(110)中并且穿过第二绝缘体(105)与芯片(107)的焊盘(109)连接，其中分别在天线(112)与焊盘(109)之间以及在导电线路(113)与焊盘(109)之间布置有金属阻挡层，并且导电线路(113)从第三绝缘体(110)中露出以用于电接触。一种封装体的制造方法。

Description

雷达组件封装体及其制造方法 技术领域
本发明总体上涉及半导体制造领域，具体而言涉及一种毫米波雷达组件封装体以及一种用于制造这样的毫米波雷达组件封装体的方法。
背景技术
随着消费产品的功能日趋多样化，在诸如汽车、机器人以及智能手机等诸多领域出现了对无线探测(例如运动物体及其速度的探测)的需求，因此毫米波雷达组件的应用日益增多。但是诸如在智能手机、气球、飞艇等许多领域中的应用对毫米波雷达组件的尺寸和重量提出严苛的要求，因此技术人员一直以来不断地尝试提高毫米波雷达组件封装体的集成度，以降低其重量和尺寸。
从名称为“一种四面扁平无引线封装式毫米波雷达收发组件的装置”的中国专利申请201510149446.5中公开了一种封装式毫米波雷达收发组件，其具有一体化盒体和盖板，其中包括毫米波雷达芯片和天线在内的各组件以线接合(Wire Bonding)方式布置在盒体的内表面上，并且盒体与盒盖之间形成空腔。但是，该封装式毫米波雷达收发组件的缺点是，其采用线接合方式布置芯片，这不仅造成线路长度过长并由此造成较大损耗，而且在盒体中还需预留一定高度以用于线接合的线路，从而造成该组件的厚度较大。此外，该封装式毫米波雷达收发组件的制造采用了包括贴片、打线、基板制作步骤的传统封装工艺，使得基板和芯片的厚度限制了组件的厚度的进一步降低。
发明内容
本发明的任务是提供一种毫米波雷达组件封装体以及一种用于制造这样的毫米波雷达组件封装体的方法，通过该封装体或该方法，可以减小损耗并且大大降低封装体的厚度。
在本发明的第一方面，该任务通过一种毫米波雷达组件封装体来解决，该毫米波雷达组件封装体包括：盒盖，其具有布置在盒盖的内表面上的金属层，所述金属层与盒体的孔道相对，其中在盒盖与盒体之间形成空腔；以及
盒体，其具有：
第一绝缘体，所述第一绝缘体与盒盖连接，其中在第一绝缘体中开设有孔道，所述孔道的一端与天线的位置相对应并且另一端与空腔连通；
一个或多个芯片，所述芯片以倒装方式布置在第二绝缘体上并且被第一绝缘体覆盖；
第二绝缘体，其布置在第一绝缘体与第三绝缘体之间；
第三绝缘体；以及
天线和导电线路，所述天线和导电线路布置在第三绝缘体中并且穿过第二绝缘体与芯片的焊盘连接，其中导电线路从第三绝缘体中露出以用于电接触。
在本发明的第二方面，该任务通过一种毫米波雷达组件封装体来解决，该毫米波雷达组件封装体包括：
盒盖，其具有布置在盒盖的内表面上的金属层，所述金属层与盒体的孔道相对，其中在盒盖与盒体之间形成空腔；以及
盒体，其具有：
第一绝缘体，所述第一绝缘体与盒盖连接，其中在第一绝缘体中开设有孔道，所述孔道的一端与天线的位置相对应并且另一端与空腔连通；
一个或多个芯片，所述芯片以倒装方式布置在第二绝缘体上并且被第一绝缘体覆盖；
第二绝缘体，其布置在第一绝缘体与第三绝缘体之间；
第三绝缘体；以及
天线和导电线路，所述天线和导电线路布置在第三绝缘体中并且穿过第二绝缘体与芯片的焊盘连接，其中分别在天线与焊盘之间以及在导电线路与焊盘之间布置有金属阻挡层，并且导电线路从第三绝缘体中露出以用于电接触。
根据本发明的毫米波雷达组件封装体至少具有下列优点：(1)根据本发明的毫米波雷达封装体具有较低的损耗，这是因为根据本发明的毫米波雷达封装体采用倒装方式布置芯片，从而减小了线路长度，由此降低了损耗；(2)在本发明中，通过将芯片、天线和导电线路埋入到盒体的相应绝缘体内，可以降低整个封装体的厚度；(3)在本发明中，由于将芯片、天线和导电线路埋入到盒体的相应绝缘体内并且将导电线路露出(即扇出(Fan Out)封装方式)，可以省去基板，由此进一步降低封装体的厚度。
在本发明的一个扩展方案中规定，所述芯片还包括焊球或其它金属连接器，所述焊球或其它金属连接器布置在第三绝缘体上并且与导电线路电连接。在此，焊球或其它金属连接器穿过第三绝缘体的一部分与导电线路电连接。焊球或其它金属连接器的作用是将毫米波雷达组件封装体的导电线路与外部的其它设备、例如另一基板互连。
在本发明的另一扩展方案中规定，所述芯片包括：
毫米波雷达芯片，所述毫米波雷达芯片包括接收芯片、雷达发射芯片、和/或雷达收发一体芯片；以及
下列各项中的一个或多个：驱动芯片、多功能芯片、末级功率放大器、低噪声放大器、限幅器、预选滤波器、射频开关、驱动控制电路、用于各个芯片工作时序的电源调制电路、以及用于电压转换的电源管理电路。
通过该扩展方案，可以将毫米波雷达芯片以及相关功能芯片集成在同一封装体内，从而实现提高的集成度。
在本发明的另一扩展方案中规定，盒盖由聚四氟乙烯制成。聚四氟乙烯具有较低介电常数，因此适于作为盒盖的材料。
在本发明的又一扩展方案中规定，天线具有钛、铜、镍、铝、银、金或其合金，并且天线的形状为圆形、方形或不规则形状。通过该扩展方案，可以灵活地选择天线的材料和形状以适应不同的应用场景。
在本发明的另一扩展方案中规定，孔道的尺寸小于天线的尺寸。在本发明中，孔道的布置是为了促进天线对信号的接收和发射。当孔道的洞口面积小于天线的面积时，即可实现天线信号的良好的接收和发射。孔道可以通过钻孔、刻蚀、化学腐蚀、光刻等方法来制作。
在本发明的又一扩展方案中规定，第一绝缘体、第二绝缘体和第三绝缘体由相同或不同的绝缘材料制成。通过该扩展方案，可以灵活地选择第一、第二和第三绝缘层的材料以实现相应的特性。
在本发明的又一扩展方案中规定，金属阻挡层具有TiCu或TiWCu，并且具有1-10μm厚度。在本发明中，金属阻挡层的作用是在蚀刻第二绝缘体或开始孔道时充当蚀刻停止层，此外还实现芯片焊盘与天线和导电线路之间的电接触。通过该优选方案，可以实现具有良好蚀刻阻挡性能和导电性能的金属阻挡 层。
在本发明的另一扩展方案中规定，金属层与孔道正对。在此，术语“正对”是指，孔道的中心与金属层的中心在封装体的厚度方向上共线。在此，能够保证最优的天线信号收发。但是在此应当指出，金属层不必一定与孔道正对，相反，在其它实施例中，金属层可以与孔道在封装体的厚度方向上错开一定距离。
在本发明的另一扩展方案中规定，金属层具有钛、铜、镍、钨、银、金或其合金。通过该扩展方案，可以实现天线信号的良好接收和发射。
在本发明的第三方面，前述任务通过一种用于制造毫米波雷达组件封装体的方法来解决，该方法包括下列步骤：
a.通过倒装方式将一个或多个芯片贴装在载体的临时键合层上；
b.通过塑封方式用第一绝缘体覆盖所述芯片以形成盒体并且除去载体和临时键合材料以露出芯片的焊盘；
c.在盒体的焊盘所在的表面上沉积金属阻挡层，并且除去多余的金属阻挡层；
d.在盒体的阻挡层所在的表面上涂敷第二绝缘体，并且除去第二绝缘体的一部分以露出芯片的焊盘；
e.在第二绝缘体上布置天线和导电线路，并且将天线和导电线路与芯片的焊盘连接；
f.在盒体的第二绝缘体所在的表面上涂敷第三绝缘体，并且除去第三绝缘体的一部分以用于电接触导电线路；
g.在盒体的背向第三绝缘体的表面上形成孔道并且除去孔道的底部的金属阻挡层，所述孔道的一端与天线的位置相对应，并且另一端向外连通；
h.形成盒盖，其中在盒盖的内表面上形成金属层，所属金属层的位置与孔道的位置相对应；以及
i.将盒盖与盒体的背向第三绝缘体的表面接合，其中在盒盖与盒体之间形成空腔。
根据本发明的方法同样具有根据本发明的封装体的优点、即降低损耗并减小封装体厚度。
在本发明的一个扩展方案中规定，该方法还包括步骤：
在第三绝缘体的为了电接触导电线路而被除去的部分中布置焊球，所述焊球与导电线路电连接。
通过该扩展方案，可以实现封装体与其它基板的导电互联。在此应当指出，封装体上的焊球的布置不是必需的，在其它实施例中，也可以布置焊盘，或者在另一要互连的基板上布置焊球。
在本发明的另一扩展方案中规定，步骤i在真空中执行或者在空腔中填充保护气体。真空或填充有保护气体的空腔可以提供内部各裸芯片长时间可靠工作所需要的气密封环境，同时又起到了电磁屏蔽的作用。通过该优选方案，可以实现良好的天线信号收发。但是应当指出，空腔中的真空环境和保护气体并不是必需的，相反，本发明的毫米波雷达组件封装体的空腔中也可以填充空气。
附图说明
下面结合附图参考具体实施例来进一步阐述本发明。
图1示出了根据本发明的毫米波雷达组件封装体的示意图；以及
图2示出了根据本发明的用于制造毫米波雷达组件封装体的方法的流程
图3示出了根据本发明的毫米波雷达组件封装体的示意图；以及
图4a-4i示出了在根据本发明的用于制造毫米波雷达组件封装体的方法的各步骤完成时的封装体的示意图。
具体实施方式
应当指出，各附图中的各组件可能为了图解说明而被夸大地示出，而不一定是比例正确的。在各附图中，给相同或功能相同的组件配备了相同的附图标记。
除非另行规定，在本申请中，量词“一个”、“一”并未排除多个元素的场景。
图1示出了根据本发明的毫米波雷达组件封装体100的示意图。
如图1所示，根据本发明的毫米波雷达组件封装体100包括盒盖101和盒体102。
盒盖101可以由具有低介电常数的材料、例如聚四氟乙烯制成。在盒盖 101的内壁上布置有金属层103，其例如由钛、铜、镍、钨、银、金或其合金制成。通过布置金属层103，可以结合孔道106利于天线112对信号的收发。
在盒盖101与盒体102之间形成有空腔108，空腔108可以为真空，或者可以填充有保护气体。真空或填充有保护气体的空腔108可以提供内部各裸芯片107长时间可靠工作所需要的气密封环境，同时又起到了电磁屏蔽的作用。但是应当指出，空腔108中的真空环境和保护气体并不是必需的，相反，本发明的毫米波雷达组件封装体100的空腔108中也可以填充空气。
盒体102具有在芯片的厚度方向上顺序布置的第一绝缘体104、第二绝缘体105和第三绝缘体110。第一绝缘体104、第二绝缘体105和第三绝缘体110例如可以由相同或不同的绝缘材料、如绝缘树脂制成。第一绝缘体104与盒盖101连接，其中在第一绝缘体104中开设有孔道106，所述孔道106的一端与天线112的位置相对应并且另一端与空腔108连通。通过设置孔道106，可以有利于天线112收发无线信号。孔道106可以通过钻孔、刻蚀、化学腐蚀、光刻等方法来制作。金属层103优选地可以与孔道106正对布置。在此，术语“正对”是指，孔道106的中心与金属层103的中心在封装体100的厚度方向上大致共线。通过这样的正对布置，能够保证最优的天线信号收发。但是在此应当指出，金属层103不必一定与孔道106正对，相反，在其它实施例中，金属层103可以与孔道106在封装体的厚度方向上错开一定距离。
盒体102还具有一个或多个芯片107，所述芯片107以倒装方式布置在第二绝缘体105上并且被第一绝缘体104覆盖。芯片107包括毫米波雷达芯片以及其它功能芯片。毫米波雷达芯片例如具有发射端(Tx)和接收端(Rx)，发射端和接收端与天线112电连接。
盒体102还具有天线112和导电线路113，所述天线112和导电线路113布置在第三绝缘体110中并且穿过第二绝缘体105与芯片107的焊盘109连接，其中导电线路113从第三绝缘体110中露出以用于电接触。
根据本发明的毫米波雷达封装体100至少具有下列优点：(1)根据本发明的毫米波雷达封装体100具有较低的损耗，这是因为根据本发明的毫米波雷达封装体100采用倒装方式布置芯片，从而减小了线路长度，由此降低了损耗；(2)在本发明中，通过将芯片107、天线112和导电线路113埋入到盒体101 的相应绝缘体内、具体而言将天线112布置在第一绝缘体104中、将天线112和导电线路113布置在第二和第三绝缘体105、110中(即重布线层RDL)中，可以降低整个封装体100的厚度；(3)在本发明中，由于将芯片107、天线112和导电线路113埋入到盒体102的相应绝缘体内并且将导电线路113露出(即扇出(Fan Out)封装方式)，可以省去基板，由此进一步降低封装体的厚度。
图2示出了根据本发明的用于制造毫米波雷达组件封装体100的方法的流程。
在步骤202，通过倒装方式将一个或多个芯片107贴装在载体116的临时键合层115上。
在步骤204，通过塑封方式用第一绝缘体104覆盖所述芯片107以形成盒体102并且除去载体116和临时键合材料115以露出芯片107的焊盘109。
在步骤206，在第一绝缘体上涂覆第二绝缘体105，并且除去第二绝缘体105的一部分以露出芯片107的焊盘109。
在步骤208,在第二绝缘体105上布置天线112和导电线路113，并且将天线112和导电线路113与芯片107的焊盘109连接。
在步骤210，在盒体102的第二绝缘体105所在的表面上涂覆第三绝缘体110，并且除去第三绝缘体110的一部分以用于电接触导电线路113。该步骤210可选地包括：在第三绝缘体110的为了电接触导电线路113而被除去的部分中布置焊球114，所述焊球114与导电线路113电连接。
在步骤212，在盒体102的背向第三绝缘体110的表面上形成孔道106，所述孔道106的一端与天线112的位置相对应，并且另一端向外连通。孔道106的深度可以为穿过第一绝缘体104直至第二绝缘体105。
在步骤214，形成盒盖101，其中在盒盖101的内表面上形成金属层103，所属金属层103的位置与孔道106的位置相对应。
最后，在步骤216，将盒盖101与盒体102的背向第三绝缘体110的表面接合，其中在盒盖101与盒体102之间形成空腔108。
图3示出了根据本发明的毫米波雷达组件封装体300的示意图。
如图3所示，根据本发明的毫米波雷达组件封装体300包括盒盖301和盒 体302。
盒盖301可以由具有低介电常数的材料、例如聚四氟乙烯制成。在盒盖301的内壁上布置有金属层303，其例如由钛、铜、镍、钨、银、金或其合金制成。通过布置金属层303，可以结合孔道306利于天线信号的收发。
在盒盖301与盒体302之间形成有空腔308，空腔308可以为真空，或者可以填充有保护气体。真空或填充有保护气体的空腔308可以提供内部各裸芯片307长时间可靠工作所需要的气密封环境，同时又起到了电磁屏蔽的作用。但是应当指出，空腔308中的真空环境和保护气体并不是必需的，相反，本发明的毫米波雷达组件封装体300的空腔308中也可以填充空气。
盒体302具有在芯片的厚度方向上顺序布置的第一绝缘体304、第二绝缘体305和第三绝缘体310。第一绝缘体304、第二绝缘体305和第三绝缘体310例如可以由相同或不同的绝缘材料、如绝缘树脂制成。第一绝缘体304与盒盖301连接，其中在第一绝缘体304中开设有孔道306，所述孔道306的一端与天线312的位置相对应并且另一端与空腔308连通。通过设置孔道306，可以有利于天线312收发无线信号。孔道306可以通过钻孔、刻蚀、化学腐蚀、光刻等方法来制作。金属层303优选地可以与孔道306正对布置。在此，术语“正对”是指，孔道306的中心与金属层303的中心在封装体300的厚度方向上大致共线。通过这样的正对布置，能够保证最优的天线信号收发。但是在此应当指出，金属层303不必一定与孔道306正对，相反，在其它实施例中，金属层303可以与孔道306在封装体的厚度方向上错开一定距离。
盒体302还具有一个或多个芯片307，所述芯片307以倒装方式布置在第二绝缘体305上并且被第一绝缘体304覆盖。芯片307包括毫米波雷达芯片以及其它功能芯片。毫米波雷达芯片例如具有发射端(Tx)和接收端(Rx)，发射端和接收端与天线312电连接。
盒体302还具有天线312和导电线路313，所述天线312和导电线路313布置在第三绝缘体310中并且穿过第二绝缘体305与芯片307的焊盘309连接，其中分别在天线312与焊盘309之间以及在导电线路313与焊盘309之间布置有金属阻挡层311，并且导电线路313从第三绝缘体310中露出以用于电接触。金属阻挡层311的作用是在蚀刻第二绝缘体305以及开设孔道306时充当蚀刻 停止层，因此，金属阻挡层311应当沉积在芯片307的焊盘309上以及第一绝缘体304上应当开设孔道307的位置处，其中金属阻挡层311在这些位置处充当蚀刻停止层，以便实现所期望的蚀刻深度。此外，金属阻挡层311还实现芯片307的焊盘109与天线312和导电线路313之间的电接触。金属阻挡层例如可以具有TiCu或TiWCu，并且可以具有1-10μm厚度。
根据本发明的毫米波雷达封装体300至少具有下列优点：(1)根据本发明的毫米波雷达封装体300具有较低的损耗，这是因为根据本发明的毫米波雷达封装体300采用倒装方式布置芯片，从而减小了线路长度，由此降低了损耗；(2)在本发明中，通过将芯片307、天线312和导电线路313埋入到盒体301的相应绝缘体内、具体而言将天线312布置在第一绝缘体304中、将天线312和导电线路313布置在第二和第三绝缘体305、310中(即重布线层RDL)中，可以降低整个封装体300的厚度；(3)在本发明中，由于将芯片307、天线312和导电线路313埋入到盒体302的相应绝缘体内并且将导电线路313露出(即扇出(Fan Out)封装方式)，可以省去基板，由此进一步降低封装体的厚度。
图4a-4f示出了在根据本发明的用于制造毫米波雷达组件封装体300的方法的各步骤完成时的封装体的示意图。
图4a示出了在该方法的步骤a完成时的封装体300的示意图。在步骤a，通过倒装方式将一个或多个芯片307贴装在载体316的临时键合层315上。
图4b示出了在该方法的步骤b完成时的封装体300的示意图。在步骤b，通过塑封方式用第一绝缘体304覆盖所述芯片307以形成盒体302并且除去载体316和临时键合材料315以露出芯片307的焊盘309。
图4c示出了在该方法的步骤c完成时的封装体300的示意图。在步骤c，在盒体302的焊盘309所在的表面上沉积金属阻挡层311，并且除去多余的金属阻挡层311。金属阻挡层311的作用是在蚀刻第二绝缘体305以及开设孔道306时充当蚀刻停止层，因此，金属阻挡层311应当沉积在芯片307的焊盘309上以及第一绝缘体304上应当开设孔道307的位置处，其中金属阻挡层311在这些位置处充当蚀刻停止层，以便实现所期望的蚀刻深度。金属阻挡层311可以通过溅射、电镀、蚀刻等方法形成。
图4d示出了在该方法的步骤d完成时的封装体300的示意图。在步骤d，在盒体302的阻挡层311所在的表面上涂敷第二绝缘体305，并且除去第二绝缘体305的一部分以露出芯片307的焊盘309。
图4e示出了在该方法的步骤e完成时的封装体300的示意图。在步骤e,在第二绝缘体305上布置天线312和导电线路313，并且将天线312和导电线路313与芯片307的焊盘309连接。在此，天线312和导电线路313通过金属阻挡层311与焊盘309连接。
图4f示出了在该方法的步骤f完成时的封装体300的示意图。在步骤f，在盒体302的第二绝缘体305所在的表面上涂敷第三绝缘体310，并且除去第三绝缘体310的一部分以用于电接触导电线路313。该步骤f可选地包括：在第三绝缘体310的为了电接触导电线路313而被除去的部分中布置焊球314，所述焊球314与导电线路313电连接。
图4g示出了在该方法的步骤g完成时的封装体300的示意图。在步骤g，在盒体302的背向第三绝缘体310的表面上形成孔道306并且除去孔道306的底部的金属阻挡层311，所述孔道306的一端与天线312的位置相对应，并且另一端向外连通。孔道306的深度可以为穿过第一绝缘体304和金属阻挡层311直至第二绝缘体305。
图4h示出了在该方法的步骤h完成时的封装体300的示意图。在步骤h，形成盒盖301，其中在盒盖301的内表面上形成金属层303，所属金属层303的位置与孔道306的位置相对应。
最后，图4i示出了在该方法的步骤i完成时的封装体300的示意图。在步骤i，将盒盖301与盒体302的背向第三绝缘体310的表面接合，其中在盒盖301与盒体302之间形成空腔308。
虽然本发明的一些实施方式已经在本申请文件中予以了描述，但是对本领域技术人员显而易见的是，这些实施方式仅仅是作为示例示出的。本领域技术人员可以想到众多的变型方案、替代方案和改进方案而不超出本发明的范围。所附权利要求书旨在限定本发明的范围，并藉此涵盖这些权利要求本身及其等同变换的范围内的方法和结构。

Claims (14)

  1. 一种毫米波雷达组件封装体，包括：
    盒盖，其具有布置在盒盖的内表面上的金属层，所述金属层与盒体的孔道相对，其中在盒盖与盒体之间形成空腔；以及
    盒体，其具有：
    第一绝缘体，所述第一绝缘体与盒盖连接，其中在第一绝缘体中开设有孔道，所述孔道的一端与天线的位置相对应并且另一端与空腔连通；
    一个或多个芯片，所述芯片以倒装方式布置在第二绝缘体上并且被第一绝缘体覆盖；
    第二绝缘体，其布置在第一绝缘体与第三绝缘体之间；
    第三绝缘体；以及
    天线和导电线路，所述天线和导电线路布置在第三绝缘体中并且穿过第二绝缘体与芯片的焊盘连接，其中导电线路从第三绝缘体中露出以用于电接触。
  2. 一种毫米波雷达组件封装体，包括：
    盒盖，其具有布置在盒盖的内表面上的金属层，所述金属层与盒体的孔道相对，其中在盒盖与盒体之间形成空腔；以及
    盒体，其具有：
    第一绝缘体，所述第一绝缘体与盒盖连接，其中在第一绝缘体中开设有孔道，所述孔道的一端与天线的位置相对应并且另一端与空腔连通；
    一个或多个芯片，所述芯片以倒装方式布置在第二绝缘体上并且被第一绝缘体覆盖；
    第二绝缘体，其布置在第一绝缘体与第三绝缘体之间；
    第三绝缘体；以及
    天线和导电线路，所述天线和导电线路布置在第三绝缘体中并且穿过第二绝缘体与芯片的焊盘连接，其中分别在天线与焊盘之间以及在导电线路与焊盘之间布置有金属阻挡层，并且导电线路从第三绝缘体中露出以用于电接触。
  3. 根据权利要求2所述的毫米波雷达组件封装体，还包括焊球或其它金 属连接器，所述焊球或其它金属连接器布置在第三绝缘体上并且与导电线路电连接。
  4. 根据权利要求2所述的毫米波雷达组件封装体，其中所述芯片包括：
    毫米波雷达芯片，所述毫米波雷达芯片包括接收芯片、雷达发射芯片、和/或雷达收发一体芯片；以及
    下列各项中的一个或多个：驱动芯片、多功能芯片、末级功率放大器、低噪声放大器、限幅器、预选滤波器、射频开关、驱动控制电路、用于各个芯片工作时序的电源调制电路、以及用于电压转换的电源管理电路。
  5. 根据权利要求2所述的毫米波雷达组件封装体，其中盒盖由聚四氟乙烯制成。
  6. 根据权利要求2所述的毫米波雷达组件封装体，其中天线具有钛、铜、镍、铝、银、金或其合金，并且天线的形状为圆形、方形或不规则形状。
  7. 根据权利要求2所述的毫米波雷达组件封装体，其中孔道的尺寸小于天线的尺寸。
  8. 根据权利要求2所述的毫米波雷达组件封装体，其中金属阻挡层具有TiCu或TiWCu，并且具有1-10μm厚度。
  9. 根据权利要求2所述的毫米波雷达组件封装体，其中金属层具有钛、铜、镍、钨、银、金或其合金。
  10. 根据权利要求2所述的毫米波雷达组件封装体，其中空腔为真空，或者在空腔中填充有保护气体。
  11. 根据权利要求2所述的毫米波雷达组件封装体，其中金属层与孔道正对。
  12. 一种用于制造毫米波雷达组件封装体的方法，包括下列步骤：
    a.通过倒装方式将一个或多个芯片贴装在载体的临时键合层上；
    b.通过塑封方式用第一绝缘体覆盖所述芯片以形成盒体并且除去载体和临时键合层以露出芯片的焊盘；
    c.在盒体的焊盘所在的表面上沉积金属阻挡层，并且除去多余的金属阻挡层；
    d.在盒体的金属阻挡层所在的表面上涂敷第二绝缘体，并且除去第二绝缘体的一部分以露出芯片的焊盘；
    e.在第二绝缘体上布置天线和导电线路，并且将天线和导电线路与芯片 的焊盘连接；
    f.在盒体的第二绝缘体所在的表面上涂敷第三绝缘体，并且除去第三绝缘体的一部分以用于电接触导电线路；
    g.在盒体的背向第三绝缘体的表面上形成孔道并且除去孔道的底部的金属阻挡层，所述孔道的一端与天线的位置相对应，并且另一端向外连通；
    h.形成盒盖，其中在盒盖的内表面上形成金属层，所属金属层的位置与孔道的位置相对应；以及
    i.将盒盖与盒体的背向第三绝缘体的表面接合，其中在盒盖与盒体之间形成空腔。
  13. 根据权利要求12所述的方法，还包括步骤：
    在第三绝缘体的为了电接触导电线路而被除去的部分中布置焊球，所述焊球与导电线路电连接。
  14. 根据权利要求12所述的方法，其中步骤i在真空中执行或者在空腔中填充保护气体。
PCT/CN2017/113113 2017-08-18 2017-11-27 雷达组件封装体及其制造方法 WO2019033608A1 (zh)

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Publication number Priority date Publication date Assignee Title
US11278241B2 (en) * 2018-01-16 2022-03-22 Infineon Technologies Ag System and method for vital signal sensing using a millimeter-wave radar sensor
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
CN1937225A (zh) * 2005-09-21 2007-03-28 国际商业机器公司 用于毫米波应用的封装天线与集成电路芯片的装置和方法
US20070164420A1 (en) * 2006-01-19 2007-07-19 Chen Zhi N Apparatus and methods for packaging dielectric resonator antennas with integrated circuit chips
CN103247581A (zh) * 2012-02-14 2013-08-14 国际商业机器公司 芯片封装和装置
CN103329349A (zh) * 2011-01-21 2013-09-25 国际商业机器公司 用于封装应用的叠层天线结构
CN103779319A (zh) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 具有集成天线的半导体封装及其形成方法
CN104916892A (zh) * 2014-03-11 2015-09-16 恩智浦有限公司 传输线互连件
CN105374802A (zh) * 2014-08-07 2016-03-02 英飞凌科技股份有限公司 微波芯片封装器件

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016111884A1 (de) * 2016-06-29 2018-01-04 Infineon Technologies Ag Vorrichtung, System und Verfahren zum automatischen Testen integrierter Antennen
DE102017203832B3 (de) * 2017-03-08 2018-05-03 Vega Grieshaber Kg Gehäuse für einen Hochfrequenzchip

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
CN1937225A (zh) * 2005-09-21 2007-03-28 国际商业机器公司 用于毫米波应用的封装天线与集成电路芯片的装置和方法
US20070164420A1 (en) * 2006-01-19 2007-07-19 Chen Zhi N Apparatus and methods for packaging dielectric resonator antennas with integrated circuit chips
CN103329349A (zh) * 2011-01-21 2013-09-25 国际商业机器公司 用于封装应用的叠层天线结构
CN103247581A (zh) * 2012-02-14 2013-08-14 国际商业机器公司 芯片封装和装置
CN103779319A (zh) * 2012-10-19 2014-05-07 英飞凌科技股份有限公司 具有集成天线的半导体封装及其形成方法
CN104916892A (zh) * 2014-03-11 2015-09-16 恩智浦有限公司 传输线互连件
CN105374802A (zh) * 2014-08-07 2016-03-02 英飞凌科技股份有限公司 微波芯片封装器件

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