CN102479762B - 散热增益型半导体组件 - Google Patents

散热增益型半导体组件 Download PDF

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CN102479762B
CN102479762B CN201110361061.7A CN201110361061A CN102479762B CN 102479762 B CN102479762 B CN 102479762B CN 201110361061 A CN201110361061 A CN 201110361061A CN 102479762 B CN102479762 B CN 102479762B
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projection
layer
vertical direction
extends
flange
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CN102479762A (zh
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林文强
王家忠
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Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
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Abstract

本发明公开了一种半导体组件，其包括半导体元件、散热座、黏着层及增层电路。该散热座包括一凸块、一基座及一凸缘层。该凸块定义出一凹穴。该半导体元件设置于凸块上且位于凹穴内，并电性连接至该增层电路，并与凸块热连结。该凸块自基座延伸进入黏着层的开口，且该基座自凸块朝相反于凹穴的方向垂直延伸，同时该凸缘层在凹穴入口处自凸块侧向延伸。该增层电路包括一介电层及导线，其位于半导体元件及凸缘层上。该导线可提供半导体元件的信号路由。

Description

散热增益型半导体组件
技术领域
本发明是关于一种半导体组件，尤指一种适用于散热增益型半导体组件，其包括半导体元件、散热座、黏着层及增层电路。
背景技术
为了整合移动、通信及计算功能，半导体封装产业面临极大的热、电及成本方面的挑战。例如，半导体元件在高温操作下容易产生效能衰退及使用寿命缩短的问题，甚至可能立即产生故障。虽然芯片级设计可持续降低操作偏压，有利于降低功率，但若在有限空间中整合更多功能时，此潜在解决方案往往无法符合需求。此外，当将半导体元件密集地封装在一起时，通常会衍生电磁干扰(EMI)或元件间干扰等不理想问题。据此，当元件进行高频率传输或接收时，上述问题会对元件信号完整性造成不好的影响。因此，目前亟需发展一种可提供足够散热效果、提高信号完整性、确保高可靠度并维持低制作成本的半导体组件。
为适应各种需求，目前已广泛发展出多种封装技术，例如，塑封球栅阵列电子封装(Plastic Ball Grid Array，PBGA)、方形扁平无引脚封装(Quad-Flat No-lead，QFN)、晶圆级封装(Wafer Level Package，WLP)及扩散型晶圆级封装(Fan-out Wafer Level Package，FOWLP)等。塑封球栅阵列电子封装(PBGA)是将一芯片及一多层连线衬底包裹于塑料外壳中，并通过锡球接置于印刷电路板(PCB)上。此层压衬底包括一通常含有玻璃纤维的介电层。芯片所释出的热需经由塑料外壳及介电层传至焊料球，进而再传至印刷电路板。然而，塑料外壳及介电层一般具有低导热性，因此PBGA的散热效果不好。
方形扁平无引脚封装(QFN)是将芯片设置在一焊接于印刷电路板的铜质上。芯片释出的热可经过铜质晶粒座而传至PCB。然而，打线I/O焊垫及导线架中介层的布线能力有限，因此QFN封装不适于高效能、高输入/输出(I/O)元件。
晶圆级封装(WLP)或晶圆级芯片尺寸封装(Wafer-Level Chip-ScalePackaging，WL-CSP)是指半导体芯片仍为晶圆形式的封装技术。由于晶圆级封装的尺寸与芯片本身相同，因此该封装形式非常适于可携式方面的应用。晶圆级封装的典型特征在于芯片表面上的增层电路，以将周边的接触垫转化成更宽更大面积阵列的组件用端子。增层电路是直接形成于芯片表面上，且细微连接线有利于更大的布线密度，因此可以提高信号完整度。然而，半导体芯片的硅区域会严重局限晶圆级封装的连接电路，因此晶圆级封装不适于高引脚数元件。
Yokogawa的美国专利案号3,903,590公开了一种组件，其是将半导体元件稳固地嵌埋于金属衬底中，以提供一支撑平台。在此方法中，介电层及导线覆盖于嵌埋芯片及金属衬底上，以电性连接半导体芯片的接触电极。热会由芯片传经该金属衬底，而该金属衬底也可以对扩散型联线电路提供机械支撑力。虽然此法可提供支撑平台并解决热问题，但在100℃至200℃下施加约370kg/cm2压力以将芯片压入金属块中的作业非常费工，且容易导致芯片受损。此外，由于芯片容易侧向位移，难以精准对位于金属衬底中，且此法未使用固定嵌埋芯片用的接合材料，因此芯片与散热块间容易产生空隙及打线不均的问题。据此，该组件会有合格率损失(yield loss)偏高、可靠度低及成本过高的问题。
Eichelberger等人的美国专利案号5,111,278公开了一种半导体芯片设置于衬底平坦表面上的组件。在制作穿透封装材至接触垫以连接这些芯片的盲孔及内联线前，其会先于芯片正面及侧边覆盖上一层以上的封装/介电层。该衬底可包括玻璃、陶瓷、塑料、硅及复合衬底，而封装材可包括热塑及热固性材料。芯片释出的热需经过封装外壳及衬底方能散至外界或PCB。由于塑料外壳及塑料材料的导热性一般偏低，因此该组件散热效果差。此外，在进行层压前，半导体芯片放置于平坦表面上，因此黏晶粒时发生的错位及增层工艺中层压导致芯片破裂的问题都会提高合格率损失度。
Fillion等人的美国专利案号5,353,498、Ma等人的美国专利案号6,154,366及Ding等人的美国专利案号6,701,614都公开了一种使用封装材以提供额外区域的组件，其是以该封装材来包裹用于制作集成电路模块的待设置半导体芯片。其中，此方法是以接触垫面向支撑膜的方式将芯片放置于支撑膜上。据此，将成形材料加至芯片周围后，该些接触垫会与封装材形成共平面。具有盲孔的介电层可对准接触垫，而延伸穿过盲孔的导电体则位于衬底上。由于成形材料一般为低导热体，因此封埋芯片所产生的热将会累积于成形化合物中。即使可使用机械研磨装置磨去封装材的背侧，以显露芯片进而降低热阻，但移除硬化成形化合物的研磨工艺非常耗时，可能在量产时造成高额成本。此外，由于磨除封装材背侧后会使芯片与封装材间的界面显露，因此界面处的水气渗入、空隙及裂痕产生问题都可能对可靠度造成严重影响。
Cole等人的美国专利案号5,073,814、Gorczyca等人的美国专利案5,161,093、Mowatt等人的美国专利案号5,432,677及Cole等人的美国专利案号5,745,984公开了一种组件，其是在形成连接芯片接触垫的电路前，先将半导体芯片容置于衬底表面上的凹陷区域。由于芯片顶面与衬底表面为共平面，因此可以避免层压导致的错位或芯片破裂现象。然而，塑料衬底(如环氧或聚酰亚胺)的导热性低，散热效果有限，而介电层(如填充有陶瓷或碳化硅的环氧材料)虽具有高导热性，但却有黏着力低及量产时成本过高的缺点。
Ito等人的美国专利案号7,929,313公开一种制备方法，其是在开口内表面形成金属层，可保护嵌埋的半导体芯片免于电磁干扰。与其它形成开口的方法一样，树脂开孔形成不一致的现象将导致该方法面临制备产量差的问题。此外，由于金属是通过电镀工艺沉积于开口中，因此其厚度有限，对封装的热效能没什么改善效果。
Towel等人的美国专利案号6,555,906及Ou等人的美国专利案6,750,397号公开一种将半导体芯片容置于散热座(如金属块)开口中的组件。由于金属块中的开口是经由刻蚀、微加工或磨除部分材料而形成，因此其主要缺点包括合格率偏低及成本偏高。此外，金属块下凹深度控制不一致的现象也造成量产时产量及合格率偏低的问题。
有鉴于现有高功率及高效能半导体元件封装种种发展情形及限制，目前仍需发展一种符合成本效益、产品可靠、适于生产、多功能、提供良好信号完整性、具有优异散热性的半导体组件。
发明内容
本发明提供一种半导体组件，其包括一半导体元件、一散热座、一黏着层及一增层电路。该散热座包括一凸块、一基座及一凸缘层，其中(i)该凸块邻接基座及凸缘层，且与凸缘层一体成形，该凸块自基座朝第一垂直方向延伸，并自凸缘层朝与该第一垂直方向相反的第二垂直方向延伸；(ii)该基座自凸块朝第二垂直方向延伸，并自凸块朝垂直于这些垂直方向的侧面方向侧伸而出；(iii)该凸缘层自凸块侧向延伸，且与基座保持距离；且(iv)该凸块具有面朝第一垂直方向的凹穴，而该凹穴在第二垂直方向上是由该凸块覆盖，该凸块分隔该凹穴与该基座，且该凹穴于凸缘层处设有一入口。
该散热座可由任何导热性材料制成。优选为，该散热座可由金属制成。举例说明，该散热座基本上可由铜、铝或铜/镍/铝合金组成。该散热座也可以由一内部铜、铝或铜/镍/铝合金核心及被覆接点组成，其中这些被覆接点可由金、银及/或镍组成。无论采用任一组成方式，该散热座都可提供散热作用，将该半导体元件的热能扩散至下一层组件。
该黏着层包括一开口，且凸块延伸进入该开口。该黏着层接触凸块、基座及凸缘层，且位于基座与凸缘层之间，该黏着层也自凸块侧向延伸至组件的外围边缘。该黏着层可侧向覆盖、环绕且同形被覆凸块侧壁。据此，该黏着层在邻接凸缘层处可具有第一厚度(朝垂直方向)，而在邻接凸块处则具有第二厚度(朝侧面方向)，且第二厚度不同于第一厚度。
具有接触垫的半导体元件可设置于凸块上，并延伸进入凸块的该凹穴。
该增层电路可包括第一介电层及第一导线。具有第一盲孔的第一介电层设置于半导体元件及凸缘层上(也就是，自半导体元件及凸缘层朝第一垂直方向延伸)，且可延伸至组件的外围边缘。据此，凸块及凸缘层位于黏着层及第一介电层间，并分隔黏着层及第一介电层。第一盲孔设置邻接并对准半导体元件的接触垫，且可选择性邻接并对准凸缘层。第一导线设置于第一介电层上(也就是，自第一介电层朝第一垂直方向延伸，并于第一介电层上侧向延伸)，并朝第二垂直方向进入第一盲孔而延伸至接触垫，以提供接触垫的电性连接及信号路由，并选择性延伸该凸缘层，以电性连接凸缘层。
若需其它信号路由，增层电路也可以包括额外的介电层、盲孔及导线层。例如，该增层电路可还包括一第二介电层、第二盲孔及第二导线。具有第二盲孔的第二介电层设置于第一介电层及第一导线上(也就是，自第一介电层及第一导线朝第一垂直方向延伸)，且可延伸至组件的外围边缘。第二盲孔设置邻接且对准第一导线。第二导线设置于第二介电层上(也就是，自第二介电层朝第一垂直方向延伸，并于第二介电层上侧向延伸)，并朝第二垂直方向进入第二盲孔而延伸至第一导线，以电性连接第一导线。
根据本发明另一方式，该半导体组件可还包括一具有一通孔的衬底。该凸块延伸进入黏着层的开口及衬底的通孔，并与衬底保持距离。该黏着层接触凸块、基座、凸缘层及衬底，并位于凸块与衬底之间、凸缘层与衬底之间以及基座与凸缘层之间，该黏着层也自凸块侧向延伸至组件的外围边缘。该衬底可延伸至组件的外围边缘，且可由有机材料(如环氧、玻璃-环氧及聚亚酰胺)制成。该衬底也可以由导热性材料(如氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(SiN)、硅(Si)等)制成。或者，该衬底可为单层结构或多层结构，如层压电路板或多层陶瓷板。此外，该衬底可与一导电层压合，且该通孔可延伸穿过该衬底及导电层。
半导体元件可设置于凸块上，并与凸块重叠但不与衬底重叠，且通过位于该凹穴内的固晶材料热连结至凸块。例如，该半导体元件可位于该凹穴内，而该增层电路则可延伸于该凹穴的内外。此外，第一介电层可延伸进入半导体元件与凸块间的间隙。或者，该固晶材料可填满半导体元件与凸块间的间隙，而第一介电层不延伸进入该间隙。半导体元件可为封装或未封装的半导体芯片。举例说明，半导体元件可为包含半导体芯片的栅格阵列(land grid array，LGA)封装或晶圆级封装(WLP)。或者，半导体元件可为半导体芯片。
该凸块可与凸缘层一体成形。例如，凸块与凸缘层可为单一金属体，或在界面处包含单一金属体，其中该单一金属体可为铜。此外，该凸块与该黏着层可于基座处呈共平面。该凸块可包含一邻接基座的第一弯折角与一邻接凸缘层的第二弯折角。该凸块也可以具有冲压而成的特有不规则厚度。此外，该凸块在凸缘层处的直径或尺寸可大于该凸块在基座处的直径或尺寸。例如，该凸块可呈平顶锥柱形或金字塔形，其直径或尺寸自基座沿着第一垂直方向朝凸缘层处递增。据此，由于黏着层朝第二垂直方向延伸进入凸块与衬底间或凸块与基座间的缺口，因此邻接凸块处的黏着层厚度呈递增趋势。该凸块也可以为直径固定的圆柱形。据此，黏着层在凸块与衬底间或凸块与基座间的缺口处具有固定厚度。该凸块也可以为该半导体元件提供一凹形晶粒座。
凸块凹穴入口处的直径或尺寸可大于该凹穴底板处的直径或尺寸。例如，该凹穴可呈平顶锥柱形或金字塔形，其直径或尺寸自其底板沿着第一垂直方向朝其入口处递增。或者，该凹穴也可以为一直径固定的圆柱形。该凹穴的入口及底板也可以具有圆形、正方形或矩形的周缘。该凹穴也可以具有与凸块相符的形状，并延伸进入该开口及该通孔，同时沿这些垂直及侧面方向延伸跨越该凸块的大部分。
该基座可具有均匀的厚度，并与衬底保持距离。例如，该基座可自凸块侧向延伸自黏着层，但未延伸至衬底。该基座可在邻接凸块处具有第一厚度，并在邻接衬底处具有第二厚度。此外，该基座也可以具有面向第二垂直方向的平坦表面。该基座邻接黏着层且与衬底保持距离的部分可具有该第一厚度，而在邻接黏着层与衬底间角形界面处则可具有该第二厚度。该基座也可以接触黏着层与衬底，在第二垂直方向覆盖凸缘层，并侧向延伸超过凸缘层，且支撑黏着层并延伸至组件的外围边缘。该基座在侧向平面上的表面积可大于凸块与凸缘层在侧向平面上的结合表面积。
该凸缘层位于增层电路与黏着层间，并分隔增层电路与黏着层。该凸缘层也可以具有圆形、正方形或矩形的周缘。此外，该凸缘层可与组件的外围边缘保持距离或延伸至组件的外围边缘。
该组件可为第一级或第二级单晶或多晶装置。例如，该组件可为包含单一芯片或多枚芯片的第一级封装体。或者，该组件可为包含单一封装体或多个封装体的第二级模块，其中每一封装体可包含单一芯片或多枚芯片。
本发明具有多项优点。该散热座可提供优异的散热效果，并使热能不流经该黏着层。因此，该黏着层及衬底可为低成本介电材且不易脱层。凸块与凸缘层可一体成形，以对半导体元件提供优异的电磁屏蔽作用并阻隔水气，进而提高电性效能及环境可靠度。机械形成的凸块凹穴可提供定义明确的空间，以放置半导体元件。因此，可避免层压过程中的半导体元件偏移及破裂问题，进而提高制备合格率并降低成本。该基座可包含连结于衬底的该金属层的一选定部分，以提高热效能。该基座可为该衬底提供机械性支撑，防止其弯曲变形。该黏着层可位于凸块与衬底之间、基座与衬底之间以及凸缘层与衬底之间，在散热座与衬底之间提供坚固的机械性连结。该增层电路可通过被覆金属，以电性连接半导体元件，其无需使用打线或焊接，因此可以提高可靠度。该增层电路可提供具有简单电路图案的信号路由或具有复杂电路图案的灵活多层信号路由。
本发明的上述及其它特征与优点将于下文中通过各种优选实施例进一步加以说明。
附图说明
图1A及1B为本发明一实施例的凸块与凸缘层剖视图。
图1C及1D分别为图1B的俯视图及仰视图。
图2A及2B为本发明一实施例的黏着层剖视图。
图2C及2D分别为图2B的俯视图及仰视图。
图3A及3B为本发明一实施例的衬底与导电层压合结构剖视图。
图3C及3D分别为图3B的俯视图及仰视图。
图4A至4E为本发明一实施例的导热板制作方法剖视图。
图5A至5J为本发明一实施例的半导体组件制作方法剖视图，其中该组件包括导热板、半导体芯片及增层电路。
图6为本发明另一实施例的半导体组件剖视图，其中该组件包括一导热板，而第一介电层与凹穴保持距离。
图7为本发明再一实施例的半导体组件剖视图，其中该组件包括一导热板，而第一导线与凸缘层保持距离。
图8为本发明又一实施例的半导体组件剖视图，其中该组件包括一导热板，而凸缘层与组件外围边缘保持距离。
图9为本发明一实施例的半导体组件剖视图，其导热板中不包含衬底。
图10为本发明另一实施例的半导体组件剖视图，其导热板不含衬底，且第一介电层与凹穴保持距离。
图11为本发明再一实施例的半导体组件剖视图，其导热板不含衬底，且第一导线与凸缘层保持距离。
图12为本发明又一实施例的半导体组件剖视图，其导热板不含衬底，且凸缘层与组件外围边缘保持距离。
【主要元件符号说明】
10                 金属板          12，14 表面
16                 凸块            18     凸缘层
20                 凹穴            22，24 弯折角
26                 渐缩侧壁        28     底板
30                 黏着层          32     开口
34                 衬底            36     导电层
40                 通孔            42     缺口
50                 散热座          60     被覆层
64                 基座            100    半导体组件
101，102，103，104 导热板          110    半导体芯片
111                顶面            112    底面
113                固晶材料        114    接触垫
201                增层电路        211    第一介电层
221                第一盲孔        241    第一导线
261                第二介电层      281    第二盲孔
291                第二导线        301    防焊层
311                开孔            341    端子焊垫
401                锡球            D1，D2 距离
T1                 第一厚度        T2     第二厚度
具体实施方式
参考随附附图，本发明可通过下述优选实施例的详细叙述更加清楚明了。
《实施例1》
图1A及1B为本发明一实施例的凸块与凸缘层制作方法剖视图，而图1C及1D分别为图1B的俯视图及仰视图。
图1A为金属板10的剖视图，金属板10包含相对的主要表面12及14。图示的金属板10是一厚度为100微米的铜板。铜具有导热性高、可挠性好及低成本等优点。金属板10可由多种金属制成，如铜、铝、铁镍合金42、铁、镍、银、金、其混合物及其合金。
图1B、1C及1D分别为金属板10形成凸块16、凸缘层18及凹穴20后的剖视图、俯视图及仰视图。凸块16及凹穴20是由金属板10以机械方式冲压而成。因此，凸块16为金属板10受冲压的部分，而凸缘层18则为金属板10未受冲压的部分。
凸块16邻接凸缘层18，并与凸缘层18一体成形，且自凸缘层18朝向下方向延伸。凸块16包含弯折角22及24、渐缩侧壁26与底板28。弯折角22及24是因冲压作业而弯折。弯折角22邻接凸缘层18与渐缩侧壁26，而弯折角24则邻接渐缩侧壁26与底板28。渐缩侧壁26朝向上方向往外延伸，而底板28则沿着垂直于向上及向下方向的侧面方向(如左、右)延伸。因此，凸块16呈平顶金字塔形(类似一平截头体)，其直径自凸缘层18处朝底板28向下递减，也就是自底板28处朝凸缘层18向上递增。凸块16的高度(相对于凸缘层18)为300微米，在凸缘层18处的尺寸为10.5毫米×8.5毫米，在底板28处的尺寸则为10.25毫米×8.25毫米。此外，凸块16因冲压作业而具有不规则的厚度。例如，因冲压而拉长的渐缩侧壁26较底板28为薄。为便于图示，凸块16在图中具有均一厚度。
呈平坦状的凸缘层18沿侧面方向自凸块16侧伸而出，其厚度为100微米。
凹穴20面朝向上方向，且延伸进入凸块16，并由凸块16从下方覆盖。凹穴20于凸缘层18处设有一入口。此外，凹穴20的形状与凸块16相符。因此，凹穴20也呈平顶金字塔形(类似一平截头体)，其直径自其位于凸缘层18的入口处朝底板28向下递减，也就是自底板28处朝其位于凸缘层18的入口向上递增。此外，凹穴20沿垂直及侧面方向延伸跨越凸块16的大部分，且凹穴20的深度为300微米。
图2A及2B图为本发明一实施例的黏着层制作方法剖视图，而图2C及2D分别为图2B的俯视图及仰视图。
图2A为黏着层30的剖视图，其中黏着层30为乙阶(B-stage)未固化环氧树脂的胶片，其为未经固化及图案化的片体，厚150微米。
黏着层30可为多种有机或无机电性绝缘体制成的各种介电膜或胶片。例如，黏着层30起初可为一胶片，其中树脂形式的热固性环氧树脂掺入一加强材料后部分固化至中期。所述环氧树脂可为FR-4，但其它环氧树脂(如多官能与双马来酰亚胺-三氮杂苯(BT)树脂等)也适用。在特定应用中，也适用氰酸酯、聚酰亚胺及聚四氟乙烯(PTFE)。该加强材料可为电子级玻璃(E-glass)，也可以为其它加强材料，如高强度玻璃(S-glass)、低诱电率玻璃(D-glass)、石英、克维拉纤维(kevlar aramid)及纸等。该加强材料也可为织物、不织布或无方向性微纤维。可将诸如硅(研粉熔融石英)等填充物加入胶片中，以提升导热性、热冲击阻抗力与热膨胀匹配性。可利用市售预浸材，如美国威斯康星州奥克莱W.L.Gore & Associates的SPEEDBOARD C胶片即为一例。
图2B、2C及2D分别为具有开口32的黏着层30剖视图、俯视图及仰视图。开口32为贯穿黏着层30且尺寸为10.55毫米×8.55毫米的窗口。开口32是以机械方式击穿该胶片而形成，但也可以以其它技术制作，如激光切割等。
图3A及3B为本发明一实施例的衬底制作方法剖视图，而图3C及3D则分别为图3B的俯视图及仰视图。
图3A是一层压结构的剖视图，其包含衬底34及导电层36。举例说明，衬底34可为厚度150微米的玻璃-环氧材料，而与衬底34接触、压合且延伸于衬底34上方的导电层36可为未经图案化且厚度30微米的铜板。
图3B、3C及3D分别为具有通孔40的层压结构(包括衬底34及导电层36)剖视图、俯视图及仰视图。通孔40为一窗口，其贯穿衬底34及导电层36且尺寸为10.55毫米×8.55毫米。通孔40是以机械方式击穿衬底34与导电层36而形成，但也可以以其它技术制作，如激光切割等。开口32与通孔40具有相同尺寸。此外，开口32与通孔40可以相同的冲头在同一冲床上通过相同方式形成。
衬底34在此绘示为一单层介电结构，但衬底34也可以为一电性互连体，如多层印刷电路板或多层陶瓷板。同样地，衬底34可另包含额外的内嵌电路层。
图4A至4E为本发明一实施例的导热板制作方法剖视图，如图4E所示，该导热板包含凸块16、凸缘层18、黏着层30、衬底34及导电层36。
图4A及4B中的结构呈凹穴向下的倒置状态，以便利用重力将黏着层30、衬底34及导电层36设置于凸缘层18上，而图4C至4E中的结构依旧维持凹穴向下。之后，图5A至5J中的结构则再次翻转至如图1A至1D所示的凹穴向上状态。简而言之，凹穴20在图4A至4E中朝下，而在图5A至5J中则朝上。尽管如此，该结构体的相对方位并未改变。无论该结构体是否倒置、旋转或倾斜，凹穴20始终面朝第一垂直方向，并在第二垂直方向上由凸块16覆盖。同样地，无论该结构体是否倒置、旋转或倾斜，凸块16都是朝第一垂直方向延伸至衬底34外，并自凸缘层18朝第二垂直方向延伸。因此，第一与第二垂直方向相对于该结构体而定向，彼此始终相反，且恒垂直于前述的侧面方向。
图4A为黏着层30设置于凸缘层18上的结构剖视图。黏着层30下降至凸缘层18上，使凸块16向上插入并贯穿开口32，最终则使黏着层30接触并定位于凸缘层18。优选为，凸块16插入且贯穿开口32后对准开口32且位于开口32内的中央位置而不接触黏着层30。
图4B为衬底34及导电层36设置于黏着层上的结构剖视图。将压合有导电层36的衬底34下降至黏着层30上，使凸块16向上插入通孔40，最终则使衬底34接触并定位于黏着层30。
凸块16在插入(但并未贯穿)通孔40后对准通孔40且位于通孔40内的中央位置而不接触衬底34。因此，凸块16与衬底34之间具有一位于通孔40内的缺口42。缺口42侧向环绕凸块16，同时被衬底34侧向包围。此外，开口32与通孔40相互对齐且具有相同尺寸。
此时，压合有导电层36的衬底34安置于黏着层30上并与之接触，且延伸于黏着层30上方。凸块16延伸通过开口32后进入通孔40。凸块16比导电层36的顶面低30微米，且通过通孔40朝向上方向外露。黏着层30接触凸缘层18与衬底34且介于该两者之间。黏着层30接触衬底34但与导电层36保持距离。在此阶段，黏着层30仍为乙阶(B-stage)未固化环氧树脂的胶片，而缺口42中则为空气。
图4C为黏着层30流入缺口42中的结构剖视图。黏着层30经由施加热及压力而流入缺口42中。在此图中，迫使黏着层30流入缺口42的方法是对导电层36施以向下压力及/或对凸缘层18施以向上压力，也就是将凸缘层18与衬底34相对压合，借以对黏着层30施压；在此同时也对黏着层30加热。受热的黏着层30可在压力下任意成形。因此，位于凸缘层18与衬底34间的黏着层30受到挤压后，改变其原始形状并向上流入缺口42。凸缘层18与衬底34持续朝彼此压合，直到黏着层30填满缺口42为止。此外，黏着层30仍位于凸缘层18与衬底34之间，且持续填满凸缘层18与衬底34间缩小的间隙。
举例说明，可将凸缘层18及导电层36设置于一压合机之上、下压台(图未示)之间。此外，可将一上挡板及上缓冲纸(图未示)夹置于导电层36与上压台之间，并将一下挡板及下缓冲纸(图未示)夹置于凸缘层18与下压台之间。以此构成的迭合体由上到下依次为上压台、上挡板、上缓冲纸、衬底34、导电层36、黏着层30、凸缘层18、下缓冲纸、下挡板及下压台。此外，可利用从下压台向上延伸并穿过凸缘层18对位孔(图未示)的工具接脚(图未示)，将此迭合体定位于下压台上。
而后，将上、下压台加热并相向推进，借此对黏着层30加热并施压。挡板可将压台的热分散，使热均匀施加于凸缘层18与衬底34乃至于黏着层30。缓冲纸则将压台的压力分散，使压力均匀施加于凸缘层18与衬底34乃至于黏着层30。起初，衬底34接触并向下压合至黏着层30上。随着压台持续动作与持续加热，凸缘层18与衬底34间的黏着层30受到挤压并开始熔化，因而向上流入缺口42，并在通过衬底34后抵达导电层36。例如，未固化环氧树脂遇热熔化后，被压力挤入缺口42中，但加强材料及填充物仍留在凸缘层18与衬底34之间。黏着层30在通孔40内上升的速度大于凸块16，终至填满缺口42。黏着层30也上升至稍高于通孔40的位置，并在压台停止动作前，溢流至凸块16顶面及导电层36顶面。若胶片厚度略大于实际所需厚度便可能发生上述状况。如此一来，黏着层30便在凸块16顶面及导电层36顶面形成一覆盖薄层。压台在触及凸块16后停止动作，但仍持续对黏着层30加热。
黏着层30在缺口42内向上流动的方向如图中向上粗箭号所示，凸块16与凸缘层18相对于衬底34的向上移动如向上细箭号所示，而衬底34相对于凸块16与凸缘层18的向下移动则如向下细箭号所示。
图4D为黏着层30已固化的结构剖视图。
举例说明，压台停止移动后仍持续夹合凸块16与凸缘层18并供热，借此将已熔化而未固化的乙阶(B-stage)环氧树脂转换为丙阶(C-stage)固化或硬化的环氧树脂。因此，环氧树脂是以类似现有多层压合的方式固化。环氧树脂固化后，压台分离，以便将结构体从压合机中取出。
固化的黏着层30可在凸块16与衬底34之间以及凸缘层18与衬底34之间提供牢固的机械性连结。黏着层30可承受一般操作压力而不致变形损毁，遇过大压力时则仅暂时扭曲。此外，黏着层30可吸收凸块16与衬底34之间以及凸缘层18与衬底34之间的热膨胀不匹配。
在此阶段，凸块16与导电层36大致共平面，而黏着层30与导电层36则延伸至面朝向上方向的顶面。例如，凸缘层18与衬底34间的黏着层30厚120微米，比其初始厚度150微米减少30微米；也就是凸块16在通孔40中升高30微米，而衬底34则相对于凸块16下降30微米。凸块16的高度300微米基本上等同于导电层36(30微米)、衬底34(150微米)与下方黏着层30(120微米)的结合高度。此外，凸块16仍位于开口32与通孔40内的中央位置并与衬底34保持距离，而黏着层30则填满凸缘层18与衬底34间的空间并填满缺口42。黏着层30在缺口42内延伸跨越衬底34。换言之，缺口42中的黏着层30朝向上方向及向下方向延伸并跨越缺口42外侧壁的衬底34厚度。黏着层30也包含缺口42上方的薄顶部分，其接触凸块16的顶面与导电层36的顶面，并在凸块16上方延伸10微米。
图4E为研磨移除凸块16、黏着层30及导电层36顶部后的结构剖视图。例如，利用旋转钻石砂轮及蒸馏水处理结构体的顶部。起初，钻石砂轮仅对黏着层30进行研磨。持续研磨时，黏着层30则因受磨表面下移而变薄。最后，钻石砂轮将接触凸块16与导电层36(不一定同时接触)，因而开始研磨凸块16与导电层36。持续研磨后，凸块16、黏着层30及导电层36均因受磨表面下移而变薄。研磨持续至去除所需厚度为止。之后，以蒸馏水冲洗结构体去除污物。
上述研磨步骤将黏着层30的顶部磨去20微米，将凸块16的顶部磨去10微米，并将导电层36的顶部磨去10微米。厚度减少对凸块16或黏着层30均无明显影响，但导电层36的厚度却从30微米大幅缩减至20微米。在研磨后，凸块16、黏着层30及导电层36会于衬底34上方面朝向上方向的平滑拼接侧顶面上呈共平面。
在此阶段中，如图4E所示，导热板101包括黏着层30、衬底34、导电层36及散热座50。此时该散热座50包括凸块16及凸缘层18。凸块16在弯折角22处与凸缘层18邻接，并自凸缘层18朝向上方向延伸，且与凸缘层18一体成形。凸块16进入开口32及通孔40，并位于开口32与通孔40内的中央位置。此外，凸块16的顶部与黏着层30的邻接部分呈共平面。凸块16与衬底34保持距离，并呈尺寸沿向下延伸方向递增的平顶金字塔形。
凹穴20面朝向上方向，并延伸进入凸块16、开口32及通孔40，且始终位于凸块16、开口32及通孔40内的中央位置。此外，凸块16在向上方向覆盖凹穴20。凹穴20具有与凸块16相符的形状，且沿垂直及侧面方向延伸跨越凸块16的大部分，并维持平顶金字塔形，其尺寸自位于凸缘层18处的入口向上递减。
凸缘层18自凸块16侧向延伸，同时延伸于黏着层30、衬底34、开口32与通孔40下方，并与黏着层30接触，但与衬底34保持距离。
黏着层30在缺口42内与凸块16及衬底34接触，并位于凸块16与衬底34之间，同时填满凸块16与衬底34间的空间。此外，黏着层30在缺口42外则与衬底34及凸缘层18接触。黏着层30沿侧面方向覆盖且包围凸块16的渐缩侧壁26，并自凸块16侧向延伸至组件外围边缘并固化。据此，黏着层30在邻接凸缘层18处具有第一厚度T1，而在邻接凸块16处具有第二厚度T2，其中第一厚度T1与第二厚度T2不同。也就是，凸缘层18与衬底34间垂直方向上的距离D1，不同于凸块16与衬底34间侧面方向上的距离D2。此外，当黏着层30延伸离开凸缘层18而进入凸块16与衬底34间的缺口42时，由于凸块16朝凸缘层18延伸时的尺寸呈递增状态，因此黏着层30在邻接凸块16处的厚度也呈现递增趋势。导热板101可通过单一凸块或多个凸块来容纳多个半导体元件，而非仅可容纳单一半导体元件。因此，可将多个半导体元件设置于单一凸块上，或将半导体元件分别设置于不同凸块上。
若欲在导热板101上形成多个凸块以容纳多个半导体元件，则可在金属板10上冲压出额外的凸块16，并调整黏着层30以包含更多开口32，同时调整衬底34及导电层36以包含更多通孔40。
图5A至5J为本发明一实施例的半导体组件制作方法剖视图，其中该半导体组件包括导热板、半导体元件及增层电路。
如图5J所示，半导体组件100包括导热板101、半导体芯片110、固晶材料113、增层电路201、防焊层301及锡球401。导热板101包括黏着层30、衬底34及散热座50。散热座50包括凸块16、凸缘层18及衬底64。半导体芯片110包括顶面111、底面112及接触垫114。顶面111为包含接触垫114的作用表面，而底面112为热接触表面。增层电路201包括第一介电层211、第一导线241、第二介电层261及第二导线291。
图5A为图4E反转后的导热板101剖视图。
图5B为导热板101通过固晶材料113将半导体芯片110设置于凸块16上的剖视图。将顶面111(即作用表面)含有接触垫114的半导体芯片110下降至凹穴20中，并留置于固晶材料113上与之接触。尤其，凸块16会从下方覆盖半导体芯片110，并提供用于容置半导体芯片110的凹形晶粒座。固晶材料113会与凸块16及半导体芯片110接触，并夹置于凸块16与半导体芯片110之间。
固晶材料113原为具有高导热性的含银环氧树脂膏，并以网版印刷的方式选择性印刷于凸块16的凹穴20内，然后利用一抓取头及一自动化图案辨识系统，以步进重复的方式将半导体芯片110放置于该环氧树脂银膏上。随后，加热该环氧树脂银膏，使其在相对低温(如190℃)下硬化形成固化的固晶材料113。半导体芯片110的厚度为275微米，固晶材料113的厚度为20微米，因此，半导体芯片110与下方固晶材料113的结合高度为295微米，此高度较凹穴20的深度(300微米)少5微米。半导体芯片110的长度为10毫米、宽度为8毫米。
接着，在半导体芯片110及导热板101上形成增层电路，其步骤如下所述。
图5C为具有第一介电层211的结构剖视图。第一介电层211(如环氧树脂、玻璃-环氧、聚酰亚胺及其类似材料)是设置于半导体芯片顶面111(即作用表面)、接触垫114、固晶材料113、凸块16及凸缘层18上。第一介电层211延伸进入凹穴20并填满凹穴20中的剩余空间，使在凹穴20与凸块16、半导体芯片110及固晶材料113接触，并与凹穴20内夹置于凸块16与半导体芯片110之间。第一介电层211也于凹穴20外与凸缘层18接触，并与黏着层30保持距离。可通过各种技术来制作第一介电层211，其包括压合、辊轮涂布、旋转涂布及喷涂沉积法。在沉积前，可对第一介电层211进行等离子体刻蚀，或使用附着力促进剂(图未示)涂布第一介电层211，以提高黏着力。在此，第一介电层211可具有约50微米的厚度。
图5D为第一介电层211形成有第一盲孔221的结构剖视图。第一盲孔221穿过第一介电层211，且对准并显露接触垫114及凸缘层18的选定部位。该些第一盲孔221可通过各种技术形成，其包括激光钻孔、等离子体刻蚀及微加工工艺。可使用脉冲激光，以提高激光钻孔效能。或者，也可以使用激光扫描光束搭配金属屏蔽。在此，第一盲孔221具有约50微米的直径。
参见图5E，将第一导线241形成于第一介电层211上，其中第一导线241自第一介电层211向上延伸，并于第一介电层211上侧向延伸，同时向下延伸进入第一盲孔221，以与半导体芯片110的接触垫114及凸缘层18形成电性接触。可通过各种技术沉积第一导线240，其包括电解电镀、无电电镀、溅射及其组合。
举例说明，可先将结构体浸入一活化剂溶液中，因而使黏着层30及第一介电层211可与无电镀铜产生催化剂反应，接着以无电电镀方式形成薄铜层，以作为晶种层，然后再以电镀方式将具有预定厚度的第二铜层镀于晶种层上，以沉积形成第一导线241(为第一导电层)。或者，在沉积电镀铜层于晶种层上前，可利用溅射方式，在第一介电层211上及第一盲孔221上内成作为晶种层的薄膜(如钛/铜)。一旦达到预定厚度，再对第一导电层(电镀铜层与晶种层的结合体)进行图案化，以形成第一导线241。
又如图5E所示，凸块16、黏着层30及导电层36上还形成有被覆层60。该被覆层60沉积于凸块16、黏着层30及导电层36的侧向底面上并与之接触，且从下方覆盖此三者。为便于图示，凸块16、导电层36及被覆层60均以单层显示。由于铜为同质被覆，凸块16与被覆层60间的界线及导电层36与被覆层60间的界线(均以虚线绘示)可能不易察觉甚至无法察觉。然而，黏着层30与被覆层60间的界线则清楚可见。
为便于图标，第一导线241在剖视图中绘示为一连续电路迹线。第一导线241可提供X与Y方向的水平信号路由，并可通过第一盲孔221以提供垂直信号路由(由上至下)。此外，第一导线241可电性连接半导体芯片110及凸缘层18。
被覆层60是未经图案化的铜层，并视为基座64的一部分。基座64邻接凸块16，并自凸块16下方及侧向延伸，同时热连结至凸块16。此外，基座64从下方覆盖凸块16及凸缘层18。此外，基座64邻接凸块16处具有被覆层60厚度，而邻接衬底34处则具有被覆层60与导电层36的结合厚度。
在此阶段中，如图5E所示，导热板101包括黏着层30、衬底34及散热座50。其中，散热座50包括凸块16、凸缘层18及基座64。导热板101及半导体芯片110上的增层电路包括第一介电层211及第一导线241。
凸块16在弯折角22处邻接凸缘层18，并在弯折角24及底板28处邻接基座64。凸块16自基座64朝向上方向延伸，自凸缘层18朝向下方向延伸，并与凸缘层18一体成形。凸块16延伸进入开口32及通孔40后，仍位于开口32及通孔40内的中央位置。凸块16的底部与黏着层30其接触基座64的相邻部分共平面。凸块16也接触黏着层30，并与衬底34保持距离，同时维持平顶金字塔形，其尺寸自基座64处朝凸缘层18向上递增。
基座64自凸块16侧向延伸，并侧向延伸超过开口32与通孔40，且从下方覆盖凸块16、开口32及通孔40。基座64接触黏着层30与衬底34，并向下延伸超过黏着层30及衬底34。基座64支撑黏着层30及衬底34，并延伸至导热板101的外围边缘。基座64邻接凸块16处具有第一厚度，邻接衬底34处则具有大于第一厚度的第二厚度，基座64尚具有面朝向下方向的平坦表面。
黏着层30在缺口42内接触且介于凸块16与衬底34之间，并填满凸块16与衬底34间的空间。黏着层30在缺口42外则接触衬底34与凸缘层18，同时也接触基座64。黏着层30延伸于凸块16与凸缘层18之间以及凸块16与基座64之间，同时位于凸缘层18与基座64之间以及凸缘层18与衬底34之间。黏着层30也从凸块16侧向延伸至组件的外围边缘。此时黏着层30已固化。黏着层30沿侧面方向覆盖且包围凸块16的渐缩侧壁26，且于向上方向覆盖基座64位于凸块16周缘外的部分，同时也于向上方向覆盖衬底34且于向下方向覆盖凸缘层18。黏着层30邻接凸缘层18处具有第一厚度，而邻接凸块16处则具有第二厚度，其中第一厚度与第二厚度不同。
若需要的话，可再新增额外的连线层。
散热座50可将设置于凸块16上的半导体元件110所产生的热能散出。该半导体元件110所产生的热能流入凸块16，并经由凸块16进入基座64。热能再由基座64沿向下散出，例如扩散至下方的散热装置。
图5F为形成第二介电层261的结构剖视图，其中第二介电层261设置于第一导线241及第一介电层211上。第二介电层261与第一介电层211一样，可通过各种技术沉积，其包括膜压合、旋转涂布、辊轮涂布及喷涂沉积法。
图5G为第二介电层261形成有第二盲孔281的结构剖视图。第二盲孔281穿透第二介电层261，并对准且显露第一导线241。第二盲孔281可通过各种技术形成，其包括激光钻孔、等离子体刻蚀及微加工工艺。
图5H为形成第二导线291在第二介电层261上的结构剖视图，其中第二导线291自第二介电层261向上延伸，并在第二介电层261上侧向延伸，且向下延伸进入第二盲孔281，以与第一导线241电性接触，进而电性连接半导体芯片110与凸缘层18。据此，已完成包含第一介电层211、第一导线241、第二介电层261及第二导线291的增层电路201。
图5I为防焊层301设置于第二介电层261及第二导线291上的结构剖视图。防焊层301包括显露第二导线291选定部位的防焊层开孔311，以定义出端子焊垫341。防焊层开孔311可通过各种技术形成，其包括微加工工艺、激光钻孔或及离子体刻蚀。端子焊垫341可用于形成导电连接件(如焊料凸块、锡球、接脚及其类似物)，以与外部元件或印刷电路版导通。
图5J为形成有多个锡球401的结构剖视图，其中锡球401设置于端子焊垫341上。可通过各种技术形成锡球401，其包括：通过网印法涂上锡膏后再进行回火工艺或通过现有电镀技术。
可再增加额外的连线层，直到端子焊垫341位于适当位置。形成介电层211，261、盲孔221，281及导线241，291的各种方法都可从文献中找到。
《实施例2》
图6为本发明另一实施例的半导体组件剖视图，其导热板同样具有衬底，但第一介电层211与凹穴20保持距离。
本实施例的半导体组件制作方法与实施例1所述大致相同，只是不同处在于，本实施例的固晶材料113已填满凹穴20剩余空间。因此，固晶材料113已填满凸块16与半导体芯片110间之间隙，而第一介电层211设置于半导体芯片顶面111(即作用表面)上，并与接触垫114、固晶材料113及凸缘层18接触，但不接触凸块16且未延伸进入凹穴20。为求简明，凡导热板101及增层电路201之相关说明适用于此实施例者均并入此处，相同之说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
《实施例3》
图7为本发明再一实施例的半导体组件剖视图，其导热板同样具有衬底，但第一导线241与凸缘层18保持距离。
本实施例的半导体组件制作方法与实施例1所述大致相同，只是不同处在于，本实施例的第一盲孔221未显露凸缘层18，而第一导线241未延伸至凸缘层18，因此未在凸缘层18上形成电性连接。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
《实施例4》
图8为本发明又一实施例的半导体组件剖视图，其导热板102同样具有衬底，但凸缘层18与组件外围边缘保持距离。
在本实施例中，部分凸缘层18已被移除，而凸缘层18自凸块16侧向延伸但未延伸至组件外围边缘。此外，第一盲孔221未显露凸缘层18，因此未在凸缘层18上形成电性连接。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
导热板102的制作方法与实施例1中的导热板101制法大致相同，只是不同处在于，本实施例在形成第一介电层211前先移除部份凸缘层18，而所形成的第一盲孔221仅显露接触垫114但未显露凸缘层18。据此，本实施例的第一介电层211设置于半导体顶面111(即作用表面)、接触垫114、固晶材料113、凸块16、凸缘层18及黏着层30上，并与黏着层30接触。
《实施例5》
图9为本发明一实施例的半导体组件剖视图，其导热板103中不包含衬底。
本实施例是使用厚导电层36，且未使用衬底。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
本实施例的导电层36比实施例1中的导电层36厚。例如，导电层36的厚度为130微米(而非30微米)，如此一来便可防止导电层36弯曲或晃动，而基座64也因此增厚。导热板103则未使用衬底。据此，基座64在邻接凸块16处具有第一厚度，而邻接黏着层30处则具有大于第一厚度的第二厚度。此外，如实施例1所述，黏着层30在邻接凸缘层18处可具有第一厚度，而邻接凸块16处则可具有不同于第一厚度的第二厚度。也就是，凸缘层18与导电层36间垂直方向上的距离，可不同于凸块16与导电层36(视为基座64的一部分)间侧面方向上的距离。另外，如实施例1所述，当黏着层30向下延伸进入凸块16与导电层36间的缺口时，由于凸块16向上延伸时的尺寸呈递增状态，因此黏着层30在邻接凸块16处的厚度也呈现递增趋势。
导热板103的制作方式与导热板101类似，但必须对导电层36进行适当调整。例如，先将黏着层30设置于凸缘层18上，再将导电层36单独设置于黏着层30上，接着对黏着层30加热及加压，使黏着层30流动并固化，最后再以研磨方式使凸块16、黏着层30及导电层36的侧向表面成为平面。据此，本实施例的黏着层30接触凸块16、基座64及凸缘层18，并侧向覆盖、包围且同形被覆凸块16的渐缩侧壁26。
《实施例6》
图10为本发明另一实施例的半导体组件剖视图，其导热板不含衬底，且第一介电层211未延伸进入凹穴20。
本实施例的半导体组件制作方法与实施例5所述大致相同，只是不同处在于，本实施例的固晶材料113已填满凸块16与半导体芯片110间的间隙，因此第一介电层211设置于半导体芯片顶面111(即作用表面)上，并与接触垫114、固晶材料113及凸缘层18接触，但不接触凸块16且未延伸进入凹穴20。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
《实施例7》
图11为本发明再一实施例的半导体组件剖视图，其导热板不含衬底，且第一导线241与凸缘层18保持距离。
本实施例的半导体组件制作方法与实施例5所述大致相同，只是不同处在于，本实施例的第一盲孔221未显露凸缘层18，而第一导线241未延伸至凸缘层18，因此未在凸缘层18上形成电性连接。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
《实施例8》
图12为本发明又一实施例的半导体组件剖视图，其导热板104不含衬底，且凸缘层18与组件外围边缘保持距离。
在本实施例中，部分凸缘层18已被移除，因此凸缘层18自凸块16侧向延伸但未延伸至组件外围边缘。此外，第一盲孔221未显露凸缘层18，因此未在凸缘层18上形成电性连接。为求简明，凡导热板101及增层电路201的相关说明适用于此实施例者均并入此处，相同的说明不予重复。同样地，本实施例导热板及增层电路的元件与导热板101及增层电路201的元件相仿的元件，均采对应的元件符号。
导热板104的制作方法与实施例5中的导热板103制法大致相同，只是不同处在于，本实施例在形成第一介电层211前先移除部份凸缘层18，而所形成的第一盲孔221仅显露接触垫114但未显露凸缘层18。据此，本实施例的第一介电层211设置于半导体顶面111(即作用表面)、接触垫114、固晶材料113、凸块16、凸缘层18及黏着层30上，且与凸缘层18及黏着层30接触。
上述的半导体组件与导热板仅为说明范例，本发明尚可通过其它多种实施例实现。此外，上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其它实施例混合搭配使用。例如，衬底可包括陶瓷材料或环氧类层压体，且可嵌埋有单层导线或多层导线。导热板可包含多个凸块，且该些凸块排成一阵列以供多个半导体元件使用。此外，增层电路为配合额外的半导体元件，可包含更多导线。
本申请的半导体元件可独自使用一散热座，或与其它半导体元件共享一散热座。例如，可将单一半导体元件设置于一散热座上，或将多个半导体元件设置于一散热座上。举例而言，可将四枚排列成2×2阵列的小型芯片黏附于凸块，而增层电路可包括额外的导线以连接更多的接触垫。相较每一芯片设置一微小凸块，此作法还具经济效益。
本申请的半导体元件可为已封装或未封装芯片。此外，该半导体元件可为裸芯片、栅格阵列封装(LGA)或方形扁平无引脚封装(QFN)等。可利用多种连结媒介将半导体元件机械性连结、电性连结及热连结至导热板，包括利用焊接及使用导电及/或导热黏着剂等方式达成。
本申请的散热座可将半导体元件所产生的热能迅速、有效且均匀散发至下一层组件而不需使热流通过黏着层、衬底或导热板的他处。如此一来便可使用导热性较低的黏着层，进而大幅降低成本。散热座可包含一体成形的凸块与凸缘层，以及与该凸块为冶金连结及热连结的基座，借此提高可靠度并降低成本。此外，凸块可依半导体元件量身订做，而基座则可依下一层组件量身订做，借此加强自半导体元件至下一层组件的热连结。例如，凸块的底板可为正方形或矩形，与半导体元件热接点的形状相同或相似。在上述任一设计中，散热座均可采用多种不同的导热金属结构。
散热座可与半导体元件电性连结或电性隔离。例如，第一导线延伸进入接触垫及凸缘层上方的第一盲孔，使可将半导体元件电性连接至凸缘层及凸块。而后，散热座可进一步电性接地，借以将半导体元件电性接地并提供电磁屏蔽作用。
基座可为该组件提供重要的散热沟槽。基座的背部可包含向下突伸的鳍片。举例说明，可利用钻板机切削基座的外露侧向表面以形成侧向沟槽，而此等侧向沟槽即形成鳍片。在此例中，基座的厚度可为500微米，前述沟槽的深度可为300微米，也就是鳍片的高度可为300微米。这些鳍片可增加基座的表面积，若这些鳍片曝露于空气中而非设置于一散热装置上，则可提升基座经由热对流的导热性。
基座可在黏着层固化后，以多种沉积技术制成，包括以电镀、无电电镀、蒸镀及溅射等技术形成单层或多层结构。基座可采用与凸块相同或不同的金属材质。此外，基座可跨越通孔并延伸至衬底，或坐落于通孔的周缘内。因此，基座可接触衬底或与衬底保持距离。在上述任一情况下，基座均邻接凸块，并自凸块朝背向凹穴的方向垂直延伸。
本申请的黏着层可在散热座与衬底之间提供坚固的机械性连结。例如，黏着层可自凸块侧向延伸并越过导线，最后到达组件的外围边缘。黏着层可填满散热座与衬底间的空间，且为一具有结合线均匀分布的无孔洞结构。黏着层也可以吸收散热座与衬底之间因热膨胀所产生的不匹配现象。黏着层的材料可与介电层相同或不同。此外，黏着层可为低成本的介电材，其无需具备高导热性。此外，本申请的黏着层不易脱层。
另外，可调整黏着层的厚度，使黏着层实质填满所述缺口，并使几乎所有黏着剂在固化及/或研磨后均位于结构体内。例如，可通过试误法来决定理想的胶片厚度。
衬底可为导热板提供机械性支撑。例如，衬底可防止导热板在金属研磨、芯片设置及增层电路制作的过程中弯曲变形。衬底可选用低成本材料，其无需具备高导热性。据此，衬底可由现有有机材料(如环氧、玻璃-环氧、聚酰亚胺等)制成。此外，也可以使用导热材料(如氧化铝(A12O3)、氮化铝(A1N)、氮化硅(SiN)、硅(Si)等)做为衬底材料。在此，衬底可为单层结构或多层结构，如层压电路板或多层陶瓷板。据此，衬底可包括额外的嵌埋式电路层。
可先将导电层设置于衬底上，再在导电层及衬底中形成通孔，接着将导电层及衬底设置于黏着层上，以使导电层在向上方向显露，而衬底则与导电层及黏着层接触，并介于两者之间，以分隔导电层及黏着层。此外，凸块延伸进入通孔，并通过通孔而朝向上方向显露。在此例中，该导电层的厚度可为10至50微米，例如30微米，此厚度一方面够厚，足以提供可靠的信号传导，一方面则够薄，有利于降低重量及成本。此外，该衬底恒为导热板的一部分。
导电层可单独设置于黏着层上。例如，可先在导电层上形成通孔，然后将该导电层设置于黏着层上，使该导电层接触该黏着层并朝向上方向外露，在此同时，凸块则延伸进入该通孔，并通过该通孔朝向上方向外露。在此例中，该导电层的厚度可为100至200微米，例如125微米，此厚度一方面够厚，因此搬运时不致弯曲晃动，一方面则够薄，因此不需过度刻蚀即可形成图案。
也可以将导电层与一载体同时设置于黏着层上。例如，可先利用一薄膜将导电层黏附于一诸如双定向聚对苯二甲酸乙二酯胶膜(Mylar)的载体，然后仅在导电层上形成通孔(即，不在载体上形成通孔)，接着将导电层及载体设置于黏着层上，使载体覆盖导电层且朝向上方向外露，并使薄膜接触且介于载体与导电层之间，至于导电层则接触且介于薄膜与黏着层之间，在此同时，凸块则对准该通孔，并由载体从上方覆盖。待黏着层固化后，可利用紫外光分解该薄膜，以便将载体从导电层上剥除，从而使导电层朝向上方向外露，之后便可对导电层进行研磨及图案化，以形成基座。在此例中，导电层的厚度可为10至50微米，例如30微米，此厚度一方面够厚，足以提供可靠的信号传导，一方面则够薄，可降低重量及成本；至于载体的厚度可为300至500微米，此厚度一方面够厚，因此搬运时不致弯曲晃动，一方面又够薄，有助于减少重量及成本。该载体仅为一暂时固定物，并非永久属于导热板的一部分。
增层电路可作为信号层、功率层或接地层，其端视其相应半导体元件焊垫的目的而定。导线也可以包含各种导电金属，例如铜、金、镍、银、钯、锡、其混合物及其合金。理想的组成既取决于外部连结媒介的性质，也取决于设计及可靠度方面的考虑。此外，本领域的普通技术人员应可了解，在本申请半导体组件中所用的铜可为纯铜，但通常以铜为主的合金，如铜-锆(99.9％铜)、铜-银-磷-镁(99.7％铜)及铜-锡-铁-磷(99.7％铜)，借以提高如抗张强度与延展性等机械性能。
在一般情况下，最好设有所述的衬底、被覆层及防焊层，但于某些实施例中则可省略它们。例如，若需使用厚导电层，则可省去衬底，以降低成本。
本申请导热板的作业格式可为单一或多个导热板，端视制造设计而定。例如，可个别制作单一导热板。或者，可利用单一金属板、单一黏着层、单一衬底及单一被覆层同时批次制造多个导热板，而后再行分离。同样地，针对同一批次中的各导热板，也可以利用单一金属板、单一黏着层、单一衬底及单一被覆层同时批次制造多组分别供单一半导体元件使用的散热座与导线。
例如，可在一金属板上冲压出多个凸块；而后将具有对应这些凸块的开口的未固化黏着层设置于凸缘层上，使每一凸块均延伸贯穿其对应开口；然后将一衬底(其具有对应这些凸块的通孔)设置于黏着层上，使每一凸块均延伸贯穿其对应开口并进入对应通孔；而后利用压台将凸缘层与该衬底彼此靠合，迫使黏着层进入这些通孔内介于这些凸块与衬底间的缺口；然后固化黏着层，继而研磨这些凸块、黏着层及导电层以形成一侧向表面。
本申请半导体组件的作业格式可为单一组件或多个组件，其取决于制造设计。例如，可单独制造单一组件，或者，可同时批次制造多个组件，之后再将各导热板一一分离。同样地，也可以将多个半导体元件电性连结、热连结及机械性连结至批次量产中的每一导热板。
可通过单一步骤或多道步骤使各导热板彼此分离。例如，可将多个导热板批次制成一平板，接着将多个半导体元件设置于该平板上，然后再将该平板所构成的多个半导体组件一一分离。或者，可将多个导热板批次制成一平板，而后将该平板所构成的多个导热板分切为多个导热板条，接着将多个半导体元件分别设置于这些导热板条上，最后再将各导热板条所构成的多个半导体组件分离为个体。此外，在分割导热板时可利用机械切割、激光切割、分劈或其它适用技术。
在本文中，「邻接」一词意思是指元件是一体成形(形成单一个体)或相互接触(彼此无间隔或未隔开)。例如，凸块邻接基座与凸缘层，但并未邻接衬底。
「重叠」一词意思是指位于上方并延伸于一下方元件的周缘内。「重叠」包含延伸于该周缘之内、外或坐落于该周缘内。例如，在凹穴朝上的状态下，本申请的半导体元件是重叠于凸块，此乃因一假想垂直线可同时贯穿该半导体元件与该凸块，不论半导体元件与凸块之间是否存有另一同样被该假想垂直线贯穿的元件(如固晶材料)，且也不论是否有另一假想垂直线仅贯穿凸块而未贯穿半导体元件(也就是位于半导体元件的周缘外)。同样地，凸块是重叠于基座，凸缘层是重叠于黏着层，且基座被凸块重叠。此外，「重叠」与「位于上方」同义，「被重叠」则与「位于下方」同义。
「接触」一词意思是指直接接触。例如，衬底接触基座但并未接触凸块。
「覆盖」一词意思是指于垂直及/或侧面方向上完全覆盖。例如，在凹穴朝上的状态下，若基座侧向延伸超出通孔外且接触衬底，则该基座是从下方覆盖凸块，但该凸块并未从上方覆盖该基座。
「层」字包含图案化及未图案化的层体。例如，当层压结构体包括导电层且衬底设置于黏着层上时，导电层可为衬底上一空白未图案化的平板；而当半导体元件设置于散热座上之后，第一导电层可为第一介电层上具有间隔导线的电路图案。此外，「层」可包含多个迭合层。
「开口」、「通孔」与「穿孔」等词同指贯穿孔洞。例如，凹穴朝下的状态下，凸块插入黏着层的开口后，其是朝向上方向从黏着层中露出。同样地，凸块插入衬底的通孔后，其是朝向上方向从衬底中露出。
「插入」一词意思是指元件间的相对移动。例如，「将凸块插入通孔中」包含：凸缘层固定不动而由衬底朝凸缘层移动；衬底固定不动而由凸缘层朝衬底移动；以及凸缘层与衬底两者彼此靠合。又例如，「将凸块插入(或延伸至)通孔内」包含：凸块贯穿(穿入并穿出)通孔；以及凸块插入但未贯穿(穿入但未穿出)通孔。
「彼此靠合」一术语意指元件间的相对移动。例如，「凸缘层与衬底彼此靠合」包含：凸缘层固定不动而由衬底朝凸缘层移动；衬底固定不动而由凸缘层朝衬底移动；以及凸缘层与衬底相互靠近。
「对准」一词意思是指元件间的相对位置。例如，当黏着层已设置于凸缘层上、衬底已设置于黏着层上、凸块已插入并对准开口且通孔已对准开口时，无论凸块是插入通孔或位于通孔下方且与其保持距离，凸块均已对准通孔。
「设置于」一术语包含与单一或多个支撑元件间的接触与非接触。例如，一半导体元件设置于凸块上，不论此半导体元件实际接触该凸块或与该凸块以一固晶材料相隔。
「黏着层于缺口内…」一术语意思是指位于缺口中的黏着层。例如，「黏着层在缺口内延伸跨越衬底」意思是指缺口内的黏着层延伸跨越衬底。同样地，「黏着层在缺口内接触且介于凸块与衬底之间」意思是指缺口中的黏着层接触且介于缺口内侧壁的凸块与缺口外侧壁的衬底之间。
「基座自凸块侧向延伸」一术语意思是指基座在邻接凸块处侧向延伸而出。例如，在凹穴朝上的状态下，基座自凸块侧向延伸并因而接触黏着层，此与基座是否侧向延伸至凸块外、侧向延伸至凸缘层或从下方覆盖凸块无关。同样地，若基座与凸块在凸块底板处占据相同的空间范围，则基座并未侧向延伸超过凸块。
「上方」一词意思是指向上延伸，且包含邻接与非邻接元件以及重叠与非重叠元件。例如，在凹穴朝上的状态下，凸块延伸于基座上方，同时邻接、重叠于基座并自基座突伸而出。
「下方」一词意思是指向下延伸，且包含邻接与非邻接元件以及重叠与非重叠元件。例如，在凹穴朝上的状态下，基座延伸于凸块下方，邻接凸块，被凸块重叠，并自凸块向下突伸而出。同样地，凸块即使并未邻接衬底或被衬底重叠，其仍可延伸于衬底下方。
「第一垂直方向」及「第二垂直方向」并非取决于半导体组件(或导热板)的定向，凡本领域的普通技术人员士即可轻易了解其实际所指的方向。例如，凸块朝第一垂直方向垂直延伸至基座外，并朝第二垂直方向垂直延伸至凸缘层外，此与组件是否倒置及/或组件是否设置于一散热装置上无关。同样地，凸缘层沿一侧向平面自凸块「侧向」伸出，此与组件是否倒置、旋转或倾斜无关。因此，该第一及第二垂直方向彼此相对且垂直于侧面方向，此外，侧向对齐的元件在垂直于第一与第二垂直方向的侧向平面上彼此共平面。此外，当凹穴向上时，第一垂直方向为向上方向，第二垂直方向为向下方向；当凹穴向下时，第一垂直方向为向下方向，第二垂直方向为向上方向。
本发明的半导体组件具有多项优点。该组件的可靠度高、价格合理且极适合量产。该组件尤其适用于易产生高热且需优异散热效果方可有效及可靠运作的高功率半导体元件、大型半导体芯片以及多个半导体元件(例如以阵列方式排列的多枚小型半导体芯片)。
本申请的制作方法具有高度适用性，且以独特、进步的方式结合运用各种成熟的电性连结、热连结及机械性连结技术。此外，本申请的制作方法不需昂贵工具即可实施。因此，相较于传统封装技术，此制作方法可大幅提升产量、合格率、效能与成本效益。此外，本申请的组件极适合于铜芯片及无铅的环保要求。
在此所述的实施例是为例示之用，其中该些实施例可能会简化或省略本技术领域已熟知的元件或步骤，以免模糊本发明的特点。同样地，为使附图清晰，附图也可以能省略重复或非必要的元件及元件符号。
本领域的普通技术人员针对本文所述的实施例当可轻易想到各种变化及修改的方式。例如，前述的材料、尺寸、形状、大小、步骤的内容与步骤的顺序都仅为范例。本领域普通技术人员可在不悖离如随附权利要求所定义的本发明精神与范畴的条件下，进行变化、调整与等同变换。

Claims (20)

1.一种散热增益型半导体组件，其特征在于，包括：
一散热座，其包括一凸块、一基座及一凸缘层，其中：
（i）该凸块邻接该基座与该凸缘层，且与该凸缘层一体成形，该凸块自该基座朝第一垂直方向延伸，并自该凸缘层朝与该第一垂直方向相反的第二垂直方向延伸，其中，该凸块包含一邻接该基座的第一弯折角与一邻接该凸缘层的第二弯折角；
（ii）该基座自该凸块朝该第二垂直方向延伸，并在该第二垂直方向上覆盖该凸块，且自该凸块朝垂直于该第一及第二垂直方向的侧面方向侧向延伸，
（iii）该凸缘层自该凸块侧向延伸，且与该基座保持距离，且（iv）该凸块具有一面向该第一垂直方向的凹穴，该凹穴在该第二垂直方向上由该凸块覆盖，该凸块也分隔该凹穴与该基座，且该凹穴在该凸缘层处设有一入口；
一衬底，其包括一通孔；
一黏着层，其包括一开口，其中该凸块延伸进入该开口及该通孔，且该黏着层接触该凸块、该基座、该凸缘层及该衬底，同时该黏着层位于该凸块与该衬底之间、该凸缘层与该衬底之间以及该基座与该凸缘层之间，并自该凸块侧向延伸至该组件的外围边缘，其中，该凸块与该黏着层在该基座处共平面；
一半导体元件，其包括接触垫且设置于该凸块上，并延伸进入该凹穴，其中，该半导体元件通过设置于该凹穴内的一固晶材料连结至该凸块；
一第一介电层，其自该半导体元件及该凸缘层朝该第一垂直方向延伸，并包括对准该些接触垫的第一盲孔；以及
第一导线，其自该第一介电层朝该第一垂直方向延伸，并在该第一介电层上侧向延伸，同时朝该第二垂直方向穿过该些第一盲孔而延伸至该些接触垫，以电性连接该半导体元件；
其中，所述基座在邻接该凸块处具有第一厚度，而在邻接该衬底处则具有大于该第一厚度的第二厚度，且具有面向该第二垂直方向的平坦表面。
2.根据权利要求1所述的散热增益型半导体组件，其特征在于，该凹穴朝这些垂直方向及这些侧面方向延伸跨越该凸块的大部分。
3.根据权利要求1所述的散热增益型半导体组件，其特征在于，该凸块具有一冲压而成的特有不规则厚度。
4.根据权利要求1所述的散热增益型半导体组件，其特征在于，该凸块与该凸缘层接触该黏着层及该第一介电层，并介于该黏着层与该第一介电层之间，以分隔该黏着层与该第一介电层。
5.根据权利要求1所述的散热增益型半导体组件，其特征在于，该黏着层在邻接该凸缘层处具有第一厚度，而在邻接该凸块处具有不同于该第一厚度的第二厚度。
6.根据权利要求1所述的散热增益型半导体组件，其特征在于，该第一介电层还延伸进入该凹穴。
7.根据权利要求1所述的散热增益型半导体组件，其特征在于，该些第一盲孔对准该凸缘层及该些接触垫，且该些第一导线超该第二垂直方向穿过该些第一盲孔而延伸至该凸缘层及该些接触垫，以电性连接该凸缘层及该些接触垫。
8.根据权利要求1所述的散热增益型半导体组件，其特征在于，该基座、该衬底及该第一介电层延伸至该组件的外围边缘。
9.根据权利要求8所述的散热增益型半导体组件，其特征在于，该凸缘层延伸至该组件的外围边缘。
10.根据权利要求1所述的散热增益型半导体组件，其特征在于，还包括：
一第二介电层，其自该第一介电层及该些第一导线朝该第一垂直方向延伸，且包括对准该些第一导线的第二盲孔；以及
第二导线，其自该第二介电层朝该第一垂直方向延伸，并在该第二介电层上侧向延伸，同时朝该第二垂直方向延伸穿过该些第二盲孔，以电性连接该些第一导线。
11.一种散热增益型半导体组件，其特征在于，包括：
一散热座，其包括一凸块、一基座及一凸缘层，其中：
（i）该凸块邻接该基座与该凸缘层，且与该凸缘层一体成形，该凸块自该基座朝第一垂直方向延伸，并自该凸缘层朝与该第一垂直方向相反的第二垂直方向延伸，其中，该凸块包含一邻接该基座的第一弯折角与一邻接该凸缘层的第二弯折角；
（ii）该基座自该凸块朝该第二垂直方向延伸，并在该第二垂直方向上覆盖该凸块，且自该凸块朝垂直于该第一及第二垂直方向的侧面方向侧向延伸，
（iii）该凸缘层自该凸块侧向延伸，且与该基座保持距离，且（iv）该凸块具有一面向该第一垂直方向的凹穴，该凹穴在该第二垂直方向上由该凸块覆盖，该凸块也分隔该凹穴与该基座，且该凹穴在该凸缘层处设有一入口；
一黏着层，其包括一开口，其中该凸块延伸进入该开口，且该黏着层接触该凸块、该基座及该凸缘层，并侧向覆盖、包围且同形被覆该凸块的一侧壁，同时该黏着层自该凸块侧向延伸至该组件的外围边缘，其中，该凸块与该黏着层在该基座处共平面；
一半导体元件，其包括接触垫且设置于该凸块上，并延伸进入该凹穴，其中，该半导体元件通过设置于该凹穴内的一固晶材料连结至该凸块；
一第一介电层，其自该半导体元件及该凸缘层朝该第一垂直方向延伸，并包括对准该些接触垫的第一盲孔；以及
第一导线，其自该第一介电层朝该第一垂直方向延伸，并在该第一介电层上侧向延伸，同时朝该第二垂直方向穿过该些第一盲孔而延伸至该些接触垫，以电性连接该半导体元件；
其中，所述基座在邻接该凸块处具有第一厚度，而在邻接衬底处则具有大于该第一厚度的第二厚度，且具有面向该第二垂直方向的平坦表面。
12.根据权利要求11所述的散热增益型半导体组件，其特征在于，该凹穴朝这些垂直方向及这些侧面方向延伸跨越该凸块的大部分。
13.根据权利要求11所述的散热增益型半导体组件，其特征在于，该凸块具有一冲压而成的特有不规则厚度。
14.根据权利要求11所述的散热增益型半导体组件，其特征在于，该凸块与该凸缘层接触该黏着层及该第一介电层，并介于该黏着层与该第一介电层之间，以分隔该黏着层与该第一介电层。
15.根据权利要求11所述的散热增益型半导体组件，其特征在于，该黏着层在邻接该凸缘层处具有第一厚度，而在邻接该凸块处具有不同于该第一厚度的第二厚度。
16.根据权利要求11所述的散热增益型半导体组件，其特征在于，该第一介电层还延伸进入该凹穴。
17.根据权利要求11所述的散热增益型半导体组件，其特征在于，该些第一盲孔对准该凸缘层及该些接触垫，且该些第一导线朝该第二垂直方向穿过该些第一盲孔而延伸至该凸缘层及该些接触垫，以电性连接该凸缘层及该些接触垫。
18.根据权利要求11所述的散热增益型半导体组件，其特征在于，该基座及该第一介电层延伸至该组件的外围边缘。
19.根据权利要求18所述的散热增益型半导体组件，其特征在于，该凸缘层延伸至该组件的外围边缘。
20.根据权利要求11所述的散热增益型半导体组件，其特征在于，还包括：
一第二介电层，其自该第一介电层及该些第一导线朝该第一垂直方向延伸，且包括对准该些第一导线的第二盲孔；以及
第二导线，其自该第二介电层朝该第一垂直方向延伸，并在该第二介电层上侧向延伸，同时朝该第二垂直方向延伸穿过该些第二盲孔，以电性连接该些第一导线。
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