CN112466833A - 内埋元件封装结构及其制造方法 - Google Patents

内埋元件封装结构及其制造方法 Download PDF

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CN112466833A
CN112466833A CN201911100304.4A CN201911100304A CN112466833A CN 112466833 A CN112466833 A CN 112466833A CN 201911100304 A CN201911100304 A CN 201911100304A CN 112466833 A CN112466833 A CN 112466833A
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semiconductor chip
dielectric
dielectric structure
thickness
circuit
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CN201911100304.4A
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陈建泛
廖玉茹
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112466833A publication Critical patent/CN112466833A/zh
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Abstract

一种内埋元件封装结构及其制造方法。内埋元件封装结构包括一介电结构、一半导体芯片以及一图案化导电层。半导体芯片内埋于介电结构中，介电结构包覆半导体芯片且具有一第一厚度，半导体芯片具有一第二厚度，第一厚度大于第二厚度，且第一厚度与第二厚度的比值介于1.1～28.4之间。图案化导电层覆盖介电结构的一上表面并延伸于介电结构的一第一开孔中，第一开孔露出半导体芯片的一电性接垫，图案化导电层与半导体芯片的电性接垫电性连接。

Description

内埋元件封装结构及其制造方法
技术领域
本发明是有关于一种元件封装结构及其制造方法，且特别是有关于一种内埋元件封装结构及其制造方法。
背景技术
在系统级封装结构中，将半导体芯片埋入封装基板中的内埋元件技术(Semiconductor Embedded in SUBstrate，简称SESUB)，因为具有降低封装基板产品受到噪声干扰及产品尺寸减小的优点，近年来已成为本领域制造商的研发重点。为了提高生产的良率，内埋元件必须固定在介电结构内，以利于后续制作的图案化导电层能与内埋元件电性连接。
然而，目前覆盖内埋元件的介电结构为树脂片，树脂片的厚度最多仅有80微米，因而无法提供更厚的介电结构。为了确保芯片被树脂完全覆盖，现今的做法是将芯片磨薄，但当芯片磨薄之后，芯片会有翘曲(warpage)问题，造成后续制程的困难。
发明内容
本发明是有关于一种内埋元件封装结构及其制造方法，以封胶材料取代传统的树脂片，以提高介电结构的厚度及/或不减少半导体芯片的厚度，以防止芯片翘曲问题。此外，在后续开孔制程中，对封胶材料进行干式喷砂，以显露出半导体芯片的电性接垫。
根据本发明的一方面，提出一种内埋元件封装结构，包括一介电结构、一半导体芯片以及一图案化导电层。半导体芯片内埋于介电结构中，介电结构包覆半导体芯片且具有一第一厚度，半导体芯片具有一第二厚度，第一厚度大于第二厚度，且第一厚度与第二厚度的比值介于1.1～28.4之间。图案化导电层覆盖介电结构的一上表面并延伸于介电结构的一第一开孔中，第一开孔露出半导体芯片的一电性接垫，图案化导电层与半导体芯片的电性接垫电性连接。
根据本发明的一方面，提出一种内埋元件封装结构，包括一介电结构、一半导体芯片以及一图案化导电层。介电结构为一热固型封胶材料。半导体芯片内埋于介电结构中，介电结构包覆半导体芯片。图案化导电层覆盖介电结构的一上表面并延伸于介电结构的一第一开孔中，第一开孔露出半导体芯片的一电性接垫，图案化导电层与半导体芯片的电性接垫电性连接，其中第一开孔以喷砂形成。
根据本发明的一方面，提出一种内埋元件封装结构的制造方法，包括下列步骤。提供一半导体芯片于一载体上。提供一介电结构于载体上以包覆半导体芯片，介电结构以一模具热固成型。对介电结构进行干式喷砂，形成一第一开孔露出半导体芯片的一电性接垫。形成一图案化导电层于介电结构的一上表面并延伸于第一开孔中，图案化导电层与半导体芯片的电性接垫电性连接。
附图说明
为让本发明的上述目的、特征和优点能更明显易懂，以下结合附图对本发明的具体实施方式作详细说明，其中：
图1A至1D绘示依照本发明一实施例的内埋元件封装结构的制造方法的示意图。
图2至图6绘示依照本发明不同实施例的内埋元件封装结构的示意图。
图7A至7I绘示依照本发明一实施例的内埋元件封装结构的制造方法的示意图。
图8A至8L绘示依照本发明另一实施例的内埋元件封装结构的制造方法的示意图。
图9A至9L绘示依照本发明又一实施例的内埋元件封装结构的制造方法的示意图。
图10A至10L绘示依照本发明又一实施例的内埋元件封装结构的制造方法的示意图。
图中元件标号说明：
100：内埋元件封装结构
102：载体
104：离形膜
106：图案化耐喷砂光阻
110：介电结构
111：第一开孔
112：上表面
113：第二开孔
114：下表面
115：盲孔
116、118：焊罩层
120：半导体芯片
121：电性接垫
122：背面
124：散热片
125：芯片粘贴膜
126：电路层
130：图案化导电层
131：种子层
132：电镀铜层
133：接合垫
134：导电柱
140：第一线路结构
141：上介电层
142：上导电层
143：开口
144：种子层
145：电镀铜层
146：接合垫
150：第二线路结构
151：下介电层
152：下导电层
153：焊球
154：接合垫
160：无源元件
170：特殊应用集成电路芯片
172：封胶
173：侧面
H1：第一厚度
H2、H2’：第二厚度
具体实施方式
以下提出实施例进行详细说明，实施例仅用以作为范例说明，并非用以限缩本发明欲保护的范围。以下是以相同/类似的符号表示相同/类似的元件做说明。以下实施例中所提到的方向用语，例如：上、下、左、右、前或后等，仅是参考所附附图的方向。因此，使用的方向用语是用来说明并非用来限制本发明。
依照本发明的一实施例，提出一种内埋元件封装结构及其制造方法。请参照图1A至1D，其绘示依照本发明一实施例的内埋元件封装结构100的制造方法的示意图。首先，形成一介电结构110以包覆半导体芯片120。接着，对介电结构110进行干式喷砂，形成一第一开孔111露出半导体芯片120的电性接垫121。接着，形成一图案化导电层130于介电结构110的一上表面112并延伸于第一开孔111中，且图案化导电层130与半导体芯片120的电性接垫121电性连接。在图1D中，此制造方法更可对半导体芯片120的背面122进行研磨，以使半导体芯片120的厚度减少。
请参照图1A，介电结构110具有一第一厚度H1，半导体芯片120具有一第二厚度H2。第一厚度H1大于第二厚度H2，且第一厚度H1与第二厚度H2的比值介于1.1～28.4之间。在一实施例中，第一厚度H1例如介于110-1420微米之间，第二厚度H2例如介于100-50微米之间或更高。第一厚度H1与第二厚度H2之间的差值例如介于10-1370微米之间。
本实施例的介电结构110是以封胶材料(epoxy molding compound,EMC)取代传统的树脂片，传统的树脂片与封胶的主成份都是环氧树脂及填充物，但填充物的成份及重量百分比不同，因此特性也会不同。传统的树脂片的填充物的重量百分比只有60～85wt％，而封胶的填充物的重量百分比大于85wt％(例如87wt％)。有关封胶的特性请参照表1及表2的说明。
在一实施例中，由于封胶材料的厚度(介于110-1420微米之间)远大于树脂片的厚度限制(小于80微米)，因此可提高介电结构110的厚度及电绝缘性。此外，封胶材料例如为一热固型环氧树脂，其放置于一模具中并热固成型以包覆半导体芯片120，不限定为片状，亦可为液态状或融熔状。待封胶材料脱模之后，可在高热环境中，对封胶材料进行后烘烤(post-mold cure)制程，可使封胶材料完全固化，且固化后的封胶材料可防止半导体芯片120翘曲。相对于传统做法需将半导体芯片以树脂片固定在载板上，再以另一树脂片包覆半导体芯片，本实施例只需进行封胶制程，且介电结构110的厚度可根据封装结构100的整体厚度大幅增加，以克服传统树脂片的厚度限制的问题。
请参照图1B，对介电结构110进行干式喷砂，以形成多数个第一开孔111，每一第一开孔111露出相对应的电性接垫121。介电结构110的厚度越高，相对需要更多喷砂数才能形成预定的开孔深度。此外，电性接垫121的尺寸较佳小于60微米，因此喷砂制程形成的第一开孔111的孔径较佳小于40微米。另外，干式喷砂之后，还可针对介电结构110的孔壁进行精细化表面处理，以避免产生颗粒化粗糙表面。在一实施例中，可选择颗粒尺寸小的填充物(例如SiO2)并加入介电结构110中，填充物的颗粒尺寸例如介于5～15微米之间，较佳介于5～10微米之间，对于后续喷砂制程显露的填充物而言，不会因颗粒太大而导致孔壁表面粗糙度过大而影响后续无电电镀的种子层与封胶材料的结合性。
请参照图1C，图案化导电层130例如包括一无电电镀的种子层131以及一电镀铜层132，电镀铜层132可覆盖在无电电镀的种子层131上，并经由局部蚀刻电镀铜层132及种子层131而形成图案化导电层130。请参照图1C，介电结构110的下表面114可切齐半导体芯片120的背面122，且介电结构110可露出半导体芯片120的背面122。
请参照图1D，对半导体芯片120的背面122及部分介电结构110进行研磨，以减少半导体芯片120及介电结构110的厚度，例如半导体芯片120的第二厚度H2’减少为第二厚度H2的2/3或更少，使研磨后的半导体芯片120的第二厚度H2’介于50～100微米之间。
请参照图2至图6，其分别绘示依照本发明不同实施例的内埋元件封装结构的示意图。图2至图6中各实施例皆以图1C之内埋元件封装结构100为主要架构，后续再根据不同需求增加其他次要结构。请参照图2，此封装结构更可包括一第一线路结构140，其设置于介电结构110的上表面112，例如是覆铜基板(copper clad laminate)制成。第一线路结构140可包括一介电层141，此介电层141例如由积层膜(ABF,Ajinomoto build-up film)、预浸渍复合纤维、聚酰亚胺或聚丙烯制成。有关图2的封装结构的制作方法，请参照图8A至8L，稍后再说明。
请参照图3A及图3B，此封装结构更可包括第一线路结构140以及第二线路结构150，第一线路结构140与第二线路结构150分别覆盖介电结构110的上表面112及相对的下表面114，例如是覆铜基板制成。第一线路结构140及第二线路结构150可分别包括一介电层141、151，此二介电层141、151例如由积层膜(ABF)、预浸渍复合纤维、聚酰亚胺或聚丙烯制成。有关图3A及图3B的封装结构的制作方法，请参照图9A至9L及图10A至10L，稍后再说明。
请参照图3A及图3B，此封装结构更可包括贯穿介电结构110的至少一导电柱134。导电柱134电性连接第一线路结构140及第二线路结构150。上述形成导电柱134的方法包括喷砂，且导电柱134可与第一线路结构及第二线路结构的制程一起形成。
请参照图4A至4B，此封装结构更可包括二焊罩层116、118，其分别覆盖介电结构110的上表面112及下表面114，且半导体芯片120的背面122露出于焊罩层118。在图4B中，封装结构更可包括一线路结构150，其设置于介电结构110的下方，且介电结构110下方的焊罩层116用以形成焊罩开口显露出接合垫154，以供焊球153电性连接接合垫154。
请参照图4C，其与图4B的封装结构相似，差异在于：此封装结构更可包括一散热片124，设置于介电结构110的上方并与半导体芯片120的背面122热接触。散热片124用以吸收半导体芯片120的废热，以降低半导体芯片120的温度。
请参照图5A及图5B，其与图3A及图3B的封装结构相似，差异在于：此封装结构更可包括二焊罩层116、118，其分别覆盖第一线路结构140及第二线路结构150的上方及下方，且封装结构100的介电结构110下方的焊罩层118用以形成焊罩开口显露出接合垫154，以供焊球153电性连接接合垫154。此外，在图5B中，半导体芯片120更可包括一芯片粘贴膜125(dieattach film)以及一电路层126内埋于芯片粘贴膜125中。电路层126预先形成于芯片粘贴膜125中，并显露于介电结构110的表面。后续再形成一第一线路结构140于介电结构110上，以使电路层126与其上方的第一线路结构140电性连接。
请参照图6，其与图5B的封装结构相似，差异在于：此封装结构更可包括一无源元件160以及一特殊应用集成电路(ASIC)芯片170，设置于第一线路结构140上方并与第一线路结构140或芯片粘贴膜125中的电路层126电性连接。在一实施例中，无源元件160例如为电容、电感或电阻等，ASIC芯片170可与半导体芯片120配合或独自运作，以提高芯片的整体效能。此外，此封装结构更包括一封胶172，包覆无源元件160以及特殊应用集成电路芯片170，且封胶172的侧面173例如切齐封装结构100的侧面。请参照表1，封胶172的主成份为环氧树脂及填充物，填充物的重量百分比为87wt％或89wt％，平均尺寸14或17微米，筛网尺寸55或75微米。请参照表2，介电结构110的主成份为环氧树脂及填充物，不同在于：填充物的重量百分比为89wt％，平均尺寸5微米，筛网尺寸25微米。
请参照图7A至7I，其绘示依照本发明一实施例的内埋元件封装结构的制造方法的示意图。首先，在图7A及图7B中，在载体102上形成一离形膜104。将半导体芯片120设置于离形膜104上，以使半导体芯片120暂时设置于载体102上。载体102例如是一刚性基板，例如金属板或塑胶板。离形膜104具有粘性并与半导体芯片120相粘合，以定位半导体芯片120。在图7C中，提供一介电结构110于载体102上以包覆半导体芯片120，介电结构110以一模具热固成型。也就是说，介电结构110为一热固型封胶材料，与传统的树脂片的材质及厚度不同。此外，相对于传统做法，不需将半导体芯片120以树脂片固定在载板上，只需使用可移除的离形膜104，以简化制程及节省成本。在图7D中，形成一图案化耐喷砂光阻106于介电结构110上。在图7E中，对介电结构110的部分上表面112进行干式喷砂，以形成凹陷于介电结构110的第一开孔111，且第一开孔111显露出半导体芯片120的电性接垫121。接着，在图7F及图7G中，形成一图案化导电层130于介电结构110的上表面112并延伸于第一开孔111中，图案化导电层130与半导体芯片120的电性接垫121电性连接。图案化导电层130例如包括一无电电镀的种子层131以及一电镀铜层132，电镀铜层132可覆盖在无电电镀的种子层131上，并经由局部蚀刻电镀铜层132及种子层131而形成图案化导电层130。在图7H中，移除载体102及离形膜104。在图7I中，形成二焊罩层116、118于介电结构110的上表面112及下表面114，并可显露出半导体芯片120的背面122及图案化导电层130的接合垫133。
请参照图8A至8L，其绘示依照本发明另一实施例的内埋元件封装结构的制造方法的示意图。图8A至8G的步骤已于上述实施例中提及，在此不再赘述。在图8H中，形成一介电层141于介电结构110上，并压合一上导电层142(例如铜箔)在介电层141上，再加热固化介电层141。介电层141例如由积层膜(ABF,Ajinomoto build-up film)、预浸渍复合纤维、聚酰亚胺或聚丙烯制成。在图8I中，形成多个开口143于介电层141中，接着，在图8J中，形成一无电电镀的种子层144于上导电层142的上表面及开口143中，再形成一电镀铜层145于种子层144上，以使上导电层142与图案化导电层130之间电性连接。在图8K中，经由蚀刻上导电层142、种子层144及电镀铜层145，以形成图案化线路，如此，第一线路结构140完成。在图8L中，形成二焊罩层116、118于介电结构110及第一线路结构140的上方及下方，并可显露出半导体芯片120的背面122及第一线路结构140的接合垫146。
请参照图9A至9L，其绘示依照本发明另一实施例的内埋元件封装结构的制造方法的示意图。图9A至9G的步骤已于上述实施例中提及，在此不再赘述。在图9H中，形成一上介电层141及一下介电层151于介电结构110的上方及下方，并压合一上导电层142及一下导电层152(例如铜箔)在上介电层141及下介电层151上，再加热固化上介电层141及下介电层151。在图9I中，形成贯穿介电结构110、上介电层141及下介电层151的至少一第二开孔113。上述形成第二开孔113的方法包括喷砂。在图9J中，形成一无电电镀的种子层144于上导电层142和下导电层152上及第二开孔113中，再形成一电镀铜层145于种子层144上，以使上导电层142与下导电层152之间经由第二开孔113中的导电柱134电性连接。在图9K中，经由蚀刻上导电层142、种子层144、电镀铜层145及下导电层152，以形成图案化线路，如此，第一线路结构140及第二线路结构150完成。在图9L中，形成二焊罩层116、118于第一线路结构140及第二线路结构150的上方及下方，并可显露出第一线路结构140的接合垫146及第二线路结构150的接合垫154。
请参照图10A至10L，其绘示依照本发明又一实施例的内埋元件封装结构的制造方法的示意图。图10A至10G的步骤与图9A至9G的步骤相似，相同之处不再赘述，差异在于，在图10E中，更包括形成贯穿介电结构110的至少一第二开孔113。因此，后续在图10I中，仅形成贯穿第一介电层141及第二介电层151的二盲孔115。上述形成第二开孔113及盲孔115的方式包括喷砂。图10J至10L的步骤与图9J至9L的步骤相似，用以形成第一线路结构140及第二线路结构150于介电结构110的上方及下方，在此不再赘述。
根据本发明上述实施例，由于传统树脂片的厚度最多仅有80微米，因而无法提供更厚的介电结构110以覆盖半导体芯片120。在本实施例中，以封胶材料取代传统的树脂片，以使介电结构110的厚度介于110-1420微米之间。只要半导体芯片120的厚度小于介电结构110的厚度即可，不需将芯片磨薄，因此，可解决因芯片磨薄而翘曲(warpage)的问题。同时，在第五代移动通信技术(5G)上，介电结构110的厚度例如750微米以上，介电结构110与半导体芯片120的厚度比大于2或3，可有效减少电感耦合的干扰，提高封装结构100的电绝缘性，以符合市场的需求。
请参照表1，本实施例图6的封胶172例如以四方扁平封装(QFN)结构所使用的封胶为例，其具有良好的热硬度、吸水性低、粘度低、导热率低及抗弯强度高等，适合用于元件封装结构中。有关封胶172的材料特性及参数如下：
表1
Figure BDA0002269664090000101
Figure BDA0002269664090000111
请参照表2，本实施例的介电结构110以覆晶球格阵列(flip chip ball gridarray,BGA)结构所使用的封胶材料为例，其具有良好的热硬度、吸水性低、粘度低、导热率低，且相对于传统的树脂片的填充物含量较高因而具有更高的抗弯强度，适合用于内埋元件封装结构中。有关介电结构110的封胶材料特性及参数如下：
表2
Figure BDA0002269664090000112
Figure BDA0002269664090000121
在一实施例中，可选择颗粒尺寸小的填充物(例如Al2O3/SiO2)并加入介电结构110中，填充物的颗粒尺寸例如介于5～15微米之间，较佳介于5～10微米之间。填充物的重量百分比例如89％，含量越高，热膨胀系数越高，以使介电结构110与半导体芯片120的热膨胀系数相匹配。此外，填充物的颗粒尺寸越小时，在后续开孔制程中，对封胶材料进行干式喷砂时，不会因颗粒太大而导致孔壁表面粗糙度过大而影响后续无电电镀的种子层与封胶材料的结合性。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的修改和完善，因此本发明的保护范围当以权利要求书所界定的为准。

Claims (22)

1.一种内埋元件封装结构，包括：
一介电结构；
一半导体芯片，内埋于该介电结构中，该介电结构包覆该半导体芯片且具有一第一厚度，该半导体芯片具有一第二厚度，该第一厚度大于该第二厚度，且该第一厚度与该第二厚度的比值介于1.1～28.4之间；以及
一图案化导电层，覆盖该介电结构的一上表面并延伸于该介电结构的一第一开孔中，该第一开孔露出该半导体芯片的一电性接垫，该图案化导电层与该半导体芯片的该电性接垫电性连接。
2.如权利要求1所述的封装结构，其特征在于，该第一厚度介于110-1420微米之间，该第二厚度介于100-50微米之间。
3.如权利要求1所述的封装结构，其特征在于，对该介电结构的部分该上表面进行干式喷砂，以形成凹陷于该介电结构的该第一开孔。
4.如权利要求1所述的封装结构，其特征在于，该介电结构的一下表面切齐该半导体芯片的一背面，且露出该半导体芯片的该背面。
5.如权利要求4所述的封装结构，更包括一散热片，设置于该介电结构的该下表面并与该半导体芯片的该背面热接触。
6.如权利要求1所述的封装结构，更包括一线路结构，设置于该介电结构的该上表面。
7.如权利要求6所述的封装结构，其特征在于，该线路结构包括一介电层，该介电层由积层膜(ABF,Ajinomoto build-up film)、预浸渍复合纤维、聚酰亚胺或聚丙烯制成。
8.如权利要求1所述的封装结构，更包括一第一线路结构以及一第二线路结构，该第一线路结构与该第二线路结构分别覆盖该介电结构的该上表面及相对的一下表面。
9.如权利要求8所述的封装结构，更包括贯穿该介电结构的至少一导电柱，该导电柱电性连接该第一线路结构及该第二线路结构。
10.如权利要求1所述的封装结构，其特征在于，该介电结构为一封胶材料，且该封胶材料包含环氧树脂及填充物，该填充物的重量百分比大于85wt％，且该填充物的尺寸介于5～10微米之间。
11.如权利要求1所述的封装结构，其特征在于，该半导体芯片更包括一芯片粘贴膜(die attach film)以及一电路层内埋于该芯片粘贴膜中。
12.如权利要求6所述的封装结构，更包括一元件，设置于该线路结构上，且该封装结构更包括一封胶包覆该该线路结构上的该元件。
13.一种内埋元件封装结构，包括：
一介电结构，为一热固型封胶材料；
一半导体芯片，内埋于该介电结构中，该介电结构包覆该半导体芯片；以及
一图案化导电层，覆盖该介电结构的一上表面并延伸于该介电结构的一第一开孔中，该第一开孔露出该半导体芯片的一电性接垫，该图案化导电层与该半导体芯片的该电性接垫电性连接，其中该第一开孔以喷砂形成。
14.如权利要求13所述的封装结构，其特征在于，该介电结构具有一第一厚度，该半导体芯片具有一第二厚度，该第一厚度与该第二厚度的比值介于1.1～28.4之间。
15.如权利要求13所述的封装结构，其特征在于，对该介电结构的部分该上表面进行干式喷砂，以形成凹陷于该介电结构的该第一开孔。
16.如权利要求13所述的封装结构，其特征在于，该介电结构的一下表面切齐该半导体芯片的一背面，且露出该半导体芯片的该背面。
17.如权利要求13所述的封装结构，更包括一线路结构，设置于该介电结构的该上表面，且该线路结构包括一介电层，该介电层由积层膜(ABF,Ajinomoto build-up film)、预浸渍复合纤维、聚酰亚胺或聚丙烯制成。
18.如权利要求13所述的封装结构，更包括一第一线路结构以及一第二线路结构，该第一线路结构与该第二线路结构分别覆盖该介电结构的该上表面及相对的一下表面。
19.如权利要求18所述的封装结构，更包括贯穿该介电结构的至少一导电柱，该导电柱电性连接该第一线路结构及该第二线路结构。
20.一种内埋元件封装结构的制造方法，包括：
提供一半导体芯片于一载体上；
提供一介电结构于该载体上以包覆该半导体芯片，该介电结构以一模具热固成型；
对该介电结构进行干式喷砂，形成一第一开孔露出该半导体芯片的一电性接垫；以及
形成一图案化导电层于该介电结构的一上表面并延伸于该第一开孔中，该图案化导电层与该半导体芯片的该电性接垫电性连接。
21.如权利要求20所述的制造方法，更包括对该介电结构进行干式喷砂，形成一第二开孔贯穿该介电结构，并形成一导电柱于该第二开孔中。
22.如权利要求20所述的制造方法，其特征在于，该载体上设有一离形膜，该半导体芯片设置于该离形膜上，于形成该图案化导电层于该介电结构之后，移除该载体及该离形膜。
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