WO2020000179A1 - 芯片封装结构及芯片封装方法 - Google Patents

芯片封装结构及芯片封装方法 Download PDF

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Publication number
WO2020000179A1
WO2020000179A1 PCT/CN2018/092861 CN2018092861W WO2020000179A1 WO 2020000179 A1 WO2020000179 A1 WO 2020000179A1 CN 2018092861 W CN2018092861 W CN 2018092861W WO 2020000179 A1 WO2020000179 A1 WO 2020000179A1
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WIPO (PCT)
Prior art keywords
chip
insulating layer
bare
post
bare chip
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PCT/CN2018/092861
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English (en)
French (fr)
Inventor
申中国
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880095121.5A priority Critical patent/CN112352305B/zh
Priority to PCT/CN2018/092861 priority patent/WO2020000179A1/zh
Publication of WO2020000179A1 publication Critical patent/WO2020000179A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Definitions

  • the present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure and a chip packaging method.
  • Wafer-level chip scale packaging that is, wafer-level chip packaging, is different from the traditional cut-and-seal and test-chip packaging method.
  • WLCSP Wafer-level chip scale packaging
  • the WLCSP packaging method can reduce the size of the chip module, which meets the high density requirements of the chip for the body space.
  • WLCSP package chips include a silicon layer (bare chip), a redistribution layer, a plastic encapsulation layer, and solder balls for electrically connecting the chip to an external circuit.
  • the plastic encapsulation layer usually half-wraps the silicon layer and the redistribution layer.
  • the thermal expansion coefficients of the plastic encapsulation layer, the silicon layer, and the redistribution layer are different. When the chip is working, it will cause the chip to be overstressed in one direction, and then cause the chip to be in one direction Deformation of warped edges may even cause problems such as chip cracking and chipping.
  • an embodiment of the present application provides a chip packaging structure including a chip and a plastic encapsulating material that completely encloses the chip.
  • a conductive post is provided on the chip, and the conductive post passes through the plastic encapsulating material.
  • the first end of the conductive post is The chip is coupled to an internal circuit of the chip, and the second end of the conductive post is used for coupling the chip to an external circuit.
  • the above chip packaging structure fully encapsulates the chip with plastic sealing material, while protecting the chip's various faces, it can also balance the stress between the chip and the plastic sealing material in all directions, thereby avoiding chip cracking caused by excessive stress in one direction of the chip, Problems such as chipping can improve the long-term reliability of the packaged chip structure.
  • the plastic encapsulation material is a one-piece structure, which can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface to cause the chip. Failure, improve the sealing performance of the plastic packaging material to form the plastic packaging structure, and improve the long-term reliability of the chip.
  • an outer surface of the molding material is flush with an end surface of the second end of the conductive post.
  • the chip package structure further includes: a solder ball disposed on the second end of the conductive post.
  • the solder ball is located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder ball is soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.
  • the chip includes:
  • a redistribution layer which is disposed on a surface of the first insulation layer facing away from the bare chip, and fills a first via hole penetrating the first insulation layer, and is coupled to the internal circuit of the bare chip;
  • a second insulating layer covering the first insulating layer and partially covering the redistribution layer, and opening a second via for exposing part of the redistribution layer;
  • a conductor post which fills the second via hole, a first end of the conductor post is electrically connected to an internal circuit of the bare chip, and an end surface of the second end of the conductor post is higher than a surface of the second insulating layer facing away from the bare chip.
  • the surface of the bare chip may include one or more passive devices to enhance the function of the chip.
  • the thickness of the first insulating layer is 20um-120um.
  • an embodiment of the present application further provides a chip packaging method, including:
  • a conductive post is provided on a first surface of the chip, a first end of the conductive post is coupled to an internal circuit of the chip, and a second end of the conductive post is used for the chip to couple an external circuit;
  • the plastic packaging material is cut based on the gap between the chips and the carrier substrate is removed to obtain a plurality of chip packaging structures.
  • the above chip packaging method includes: providing a plurality of chips, a conductive post is provided on a first surface of the chip, a first end of the conductive post is coupled to an internal circuit of the chip, a second end of the conductive post is used for the chip to couple an external circuit, and a conductor The end surface of the second end of the pillar is higher than the first surface.
  • the chip is bonded to the carrier substrate through the second end of the conductor pillar. There is a gap between the conductor pillar and the carrier substrate.
  • the plastic sealing material can fill the space between the conductor pillar and the carrier substrate.
  • the plastic encapsulating material of the fully-encapsulated chip can balance the stress between the chip and the encapsulating material in all directions while protecting the surface of the chip, thereby avoiding the chip caused by excessive stress in one direction of the chip Cracking, chipping and other problems improve the long-term reliability of the packaged chip structure.
  • the plastic encapsulation material on each surface of the fully-wrapped chip can be formed at one time, which can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface to cause the chip to fail, improving the
  • the plastic sealing material forms the sealing property of the plastic sealing structure and improves the long-term reliability of the chip.
  • a solder ball may be formed on the second end of the conductor post, so that the chip couples the external circuit through the solder ball. It can be seen that the solder ball in the chip packaging structure is located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder ball is soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.
  • an implementation manner of providing multiple chips may be:
  • a first via is opened on the first insulating layer, and the first via is used to expose the signal connection end of the bare chip.
  • the signal connection end is used for coupling the bare chip to an external circuit.
  • the signal connection end may be an internal part of the bare chip. Input and / or output of the circuit;
  • the redistribution layer Forming a redistribution layer on a surface of the first insulation layer facing away from the wafer, the redistribution layer filling a first via hole and connecting to the signal connection end;
  • a second via hole is opened on the second insulating layer, and the second via hole is used for partially exposing the redistribution layer;
  • the first insulating layer, the second insulating layer, and the wafer are cut to obtain chips corresponding to the plurality of bare chips on a one-to-one basis.
  • the bare chip further includes a passive element electrically connected to the bare chip, wherein an implementation manner of forming a first insulating layer covering the plurality of bare chips on a surface of the wafer may be: forming a first material The paste is placed on the wafer; the paste is heated and cured to form a first insulating layer.
  • the above method can form a thicker first insulation layer to achieve integration of a passive device into a chip.
  • an embodiment of the present application further provides an integrated circuit device.
  • the integrated circuit device includes a substrate and a chip.
  • the chip is completely wrapped with a plastic sealing material.
  • the chip is provided with a conductive post, and the conductive post passes through the plastic sealing material.
  • the chip is supported on a substrate, a first end of the conductive post is coupled to an internal circuit of the chip, and a second end of the conductive post is coupled to a circuit on the substrate.
  • the plastic encapsulation material completely covers the chip, while protecting the chip's sides, it can also balance the stress between the chip and the plastic encapsulation material in all directions, thereby avoiding chip cracking caused by excessive stress in one direction of the chip , Chipping, etc., to improve the long-term reliability of the packaged chip structure.
  • the plastic sealing material forms an integrated structure, which can avoid the interface between the plastic sealing materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface to cause the chip. Failure, improving the sealing performance of the plastic packaging material forming the plastic packaging structure, and improving the long-term reliability of the chip.
  • the outer surface of the molding material is flush with the end surface of the second end of the conductive post.
  • solder ball is provided on the second end of the conductive post, and the solder ball is used for directly soldering to a circuit on the substrate or soldering through a lead.
  • the solder ball is located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder ball is soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.
  • the chip may include:
  • a redistribution layer which is disposed on a surface of the first insulation layer facing away from the bare chip, and fills a first via hole penetrating the first insulation layer, and is coupled to the internal circuit of the bare chip;
  • a second insulating layer covering the first insulating layer and partially covering the redistribution layer, and opening a second via for exposing a part of the redistribution layer;
  • a conductive post fills the second via, the first end of the conductive post is electrically connected to the internal circuit of the bare chip, and the end surface of the second end of the conductive post is higher than the surface of the second insulating layer facing away from the bare chip.
  • the surface of the bare chip includes one or more passive devices.
  • the thickness of the first insulating layer is 20um-120um.
  • an embodiment of the present application further provides an integrated circuit.
  • the integrated circuit includes a substrate and a chip.
  • the chip is completely wrapped with a plastic sealing material.
  • the chip is provided with a conductive post, the conductive post passes through the plastic sealing material, and the chip supports the chip.
  • a first end of the conductive post is coupled to an internal circuit of the chip, and a second end of the conductive post is coupled to a circuit on the substrate.
  • the plastic encapsulating material completely covers the chip, while protecting the chip's sides, it can also balance the stress between the chip and the plastic encapsulating material in all directions, thereby avoiding chip cracking caused by excessive stress in one direction of the chip, Problems such as chipping can improve the long-term reliability of the packaged chip structure.
  • the plastic encapsulation material forms an integrated structure, which can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, and thus prevent external water vapor from entering the chip through the interface to cause the chip. Failure, improving the sealing performance of the plastic packaging material forming the plastic packaging structure, and improving the long-term reliability of the chip.
  • the outer surface of the molding material is flush with the end surface of the second end of the conductive post.
  • solder ball is provided on the second end of the conductive post, and the solder ball is used for directly soldering to a circuit on the substrate or soldering through a lead.
  • the solder ball is located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder ball is soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.
  • the chip may include:
  • a redistribution layer which is disposed on a surface of the first insulation layer facing away from the bare chip, and fills a first via hole penetrating the first insulation layer, and is coupled to the internal circuit of the bare chip;
  • a second insulating layer covering the first insulating layer and partially covering the redistribution layer, and opening a second via for exposing a part of the redistribution layer;
  • a conductive post fills the second via, the first end of the conductive post is electrically connected to the internal circuit of the bare chip, and the end surface of the second end of the conductive post is higher than the surface of the second insulating layer facing away from the bare chip.
  • the surface of the bare chip includes one or more passive devices.
  • the thickness of the first insulating layer is 20um-120um.
  • FIG. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another chip package structure according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a chip packaging method according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of another chip packaging method according to an embodiment of the present application.
  • 5A-5O are schematic structural diagrams corresponding to each process of a chip packaging method according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an integrated circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an integrated circuit device according to an embodiment of the present application.
  • a printed circuit board (Printed Circuit Board, PCB) is an important electronic component, a support for electronic components, and a carrier for the electrical connection of electronic components. Because it is made using electronic printing, it is called a "printed" circuit board.
  • the electrical connection between the I / O terminal of the chip and the PCB is realized by a surface-level surface mount technology (SMT).
  • SMT surface-level surface mount technology
  • Wafer refers to a silicon wafer used in the manufacture of silicon semiconductor integrated circuits. Because its shape is circular, it is called a wafer. Can be processed into various circuit element structures on silicon wafers, and become IC products with specific electrical functions
  • a die refers to a small piece cut from a wafer, which is a chip. Before the wafer is not packaged, the chip on the wafer or the chip cut from the wafer is called a bare chip.
  • Passive components also called passive components, refer to components that can work when there is a signal without adding power to the circuit. They are mainly resistors, inductors, and capacitors.
  • Integrated passive components integrate discrete passive components inside the substrate, improve the integration of the device system, and reduce the size and weight of the entire product.
  • Semi-wrapped in this application, refers to a part of the surface of the chip that is encapsulated by the plastic encapsulation material, and the parts of the non-conductor pillars in the chip are exposed.
  • the conductor post is the connection end for coupling external circuits on the chip, that is to say, at least one surface of the chip is not encapsulated. cover.
  • a chip includes an upper surface, a lower surface, and four sides.
  • a plastic encapsulating material usually wraps components on the upper surface of a silicon substrate in the chip (such as the chip's internal circuits, redistribution layers, etc.), and the silicon liner
  • the bottom surface of the bottom is usually not protected by a molding compound.
  • Full-wrapped refers to wrapping each surface of the chip, except for the end of the conductor post on the chip that is used to couple external circuits to the chip.
  • the fully-encapsulated chip with the plastic encapsulation material means that the plastic-encapsulated material encloses each part of the chip except the end surface of the conductor post facing away from the chip.
  • WLCSP packaged chips include a silicon layer (bare chip), a redistribution layer, and solder balls for the chip to electrically connect to external circuits.
  • the WLCSP packaging method may bring the following problems:
  • the backside of the chip is an exposed silicon layer. Due to the brittleness of the silicon material, it cannot withstand the pressure imposed by subsequent electrical tests. As a result, the WLCSP packaged chip cannot be tested and used directly at the board level, resulting in the use of the WLCSP package. The product defect rate of chips has increased.
  • the chip in the embodiment of the present application is a chip to be packaged, and may be a memory, a micro-electro-mechanical system (MEMS), a microwave radio frequency chip, an application specific integrated circuit (ASIC), etc. chip. It should be understood that the chips listed here are only illustrative, and this application does not limit this.
  • MEMS micro-electro-mechanical system
  • ASIC application specific integrated circuit
  • the chip packaging structure includes a chip 11 and a plastic encapsulating material 12 that completely surrounds the chip 11.
  • the chip 11 has a first surface and a second surface opposite to each other.
  • the first surface of the chip 11 has a conductive post 111.
  • the first end of the conductive post 111 is coupled to the internal circuit of the chip 11.
  • the second end of the conductive post 111 is An external circuit is coupled to the chip 11.
  • the conductive post 111 passes through the plastic sealing material 12, that is, the end surface of the second end of the conductive post 111 is higher than the first surface, and is exposed outside the plastic sealing material 12. It should be understood that the first end and the second end of the conductive post 111 are opposite ends of the conductive post 111; the external circuit is a circuit other than a chip, and may be a circuit on a substrate.
  • the chip packaging structure completely encapsulates the chip 11 through the plastic sealing material 12, while protecting the various faces of the chip 11, it can also balance the stress between the chip 11 and the plastic sealing material 12 in various directions, thereby avoiding the stress of the chip 11 in a certain direction Problems such as cracking, chipping, etc. of the chip 11 caused by excessive size increase the long-term reliability of the packaged chip structure.
  • the chip 11 may be a pre-packaged chip.
  • the chip 11 includes a bare chip 112, a first insulating layer 113, a redistribution layer 114, a second insulating layer 115, and a conductive pillar 111.
  • the first insulating layer 113 covers the bare chip 114; the redistribution layer 114 is provided on the surface of the first insulating layer 113 facing away from the bare chip 112, and fills the first via hole 116 penetrating the first insulating layer 113 to be coupled to the bare chip.
  • the second insulating layer 115 covers the first insulating layer 113 and partially covers the redistribution layer 114, and a second via hole 117 for exposing part of the redistribution layer 114 is opened; the conductor post 111 fills the second via hole 117
  • the first end of the conductive post 111 is electrically connected to the internal circuit of the bare chip 112, and the end surface of the second end of the conductive post 111 is higher than the surface of the second insulating layer 115 facing away from the bare chip 112.
  • the chip 11 may be a bare chip.
  • a signal connection end of the first surface of the chip 11 is prepared as a conductive post, and an end surface of the conductive post is higher than the first surface of the chip.
  • the first surface of the chip 11 is the surface of the chip 11 including the edged components.
  • the signal connection section may be an output terminal and / or an input terminal of an internal circuit in the chip 11.
  • the plastic packaging material 12 is an integrally formed structure, thereby avoiding the interface between the plastic packaging materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface to cause the chip to fail, and improving the plastic packaging film. And the long-term reliability of the chip.
  • the expansion coefficient of the plastic sealing material 12 is smaller than the expansion coefficient of the first insulating layer 113 and the second insulating layer 115.
  • the chip packaging structure needs to be heated in subsequent processes or the chip works, heat is generated.
  • the chip 11 When heated, it will swell, and the plastic packaging material 12 can exert force on the chip 11 inside it to reduce the expansion degree of the chip 11 evenly, thereby avoiding chip cracking and chipping, and further improving the long-term reliability of the packaged chip structure.
  • the outer surface of the plastic sealing material 12 is flush with the end surface of the conductive post 111, as shown in FIG.
  • the chip package structure further includes a solder ball 13 disposed on the second end of the conductive pillar 111.
  • the solder ball 13 is located outside the plastic sealing material, which does not restrict the free melting and solidification process of the solder alloy when the solder ball 13 is soldered at high temperature, and improves the soldering firmness of the chip and the external circuit. It can be understood that the solder ball 13 is not a necessary component in the embodiment of the present application.
  • the chip packaging structure may be free of the solder ball 13 and directly expose the bare chip 112 or the conductor post 111 of the chip packaging structure, or Surface treatment processes such as Organic Solderability Preservatives (OSP), Electroless Nickel / Immersion Gold (ENIG), and electroless tin plating are used on the conductor post 111 for use.
  • OSP Organic Solderability Preservatives
  • ENIG Electroless Nickel / Immersion Gold
  • electroless tin plating are used on the conductor post 111 for use.
  • the surface of the bare chip 112 includes one or more passive devices to enhance the functions of the chip.
  • the passive device may be an integrated passive component 118 (IPD) and / or an independent passive component. 119.
  • the thickness of the first insulating layer 113 is greater than the thickness of any one of the passive devices.
  • the thickness of the first insulation layer may be 20um-120um.
  • the chip packaging structure may further include a substrate, and the chip wrapped by the packaging material may be disposed on the upper surface of the substrate or may be hung on the lower surface of the substrate, which is not limited in the embodiment of the present application.
  • the substrate may include a circuit, and the solder ball may be connected to the circuit on the substrate through a wire, so as to realize the coupling between the internal circuit of the chip and the circuit on the substrate.
  • a solder ball or a conductor post can also be directly soldered on the substrate.
  • first insulating layer 113 or the second insulating layer 115 may be a planarization layer.
  • the first insulating layer 113 or the second insulating layer 115 may be made of an inorganic insulating material or an organic insulating material.
  • the inorganic insulating material may be silicon dioxide (SiO 2 ), silicon nitride (SiN 4 ), or the like, and the organic insulating material may be a polymer or resin.
  • the first insulating layer 113 or the second insulating layer 115 is a polymer film, such as photosensitive polyimide (PI), polybenzoxazole (PBO), and the like.
  • the material of the molding material 12 can be one or more of epoxy resin (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane and the like.
  • EMC epoxy Molding Compound
  • the molding compound 12 is an epoxy molding compound.
  • FIG. 3 and FIG. 4 are schematic flowcharts of two chip packaging methods provided by the embodiments of the present application. Please also refer to the cross-sectional schematic diagrams of the chip packaging structure obtained in each step corresponding to the chip packaging method shown in FIG. 4 as shown in FIGS. 5A-5O.
  • Step S1 Provide a plurality of chips.
  • the chip has opposite first and second surfaces.
  • a conductive post is provided on the first surface of the chip.
  • the first end of the conductive post is coupled to the internal circuit of the chip.
  • the second terminal is used for coupling external circuits of the chip.
  • An end surface of the second end of the conductive post is higher than the first surface.
  • the chip may be a bare chip.
  • the signal connection end of the first surface of the chip is prepared as a conductive post, and the end surface of the conductive post is higher than the first surface of the chip.
  • the first surface of the chip is the surface including the edged components on the chip.
  • the first surface of the chip may further include an IPD, and passive components may be integrated on the chip during chip preparation.
  • the chip may be a chip after a preliminary packaging process, and the preliminary packaging process (that is, step S1) may include the following steps:
  • Step S11 A wafer 51 is provided, and the wafer 51 includes a plurality of bare chips 511. Please refer to FIG. 5A together.
  • the bare chip 511 may include one or more passive devices to enhance the functions of the chip.
  • the passive device may be an IPD512 or an independent passive component 513 may be connected to the surface of the bare chip 511 during the chip preparation process.
  • Step S12 A first insulating layer 52 covering the plurality of bare chips 511 is formed on the surface of the wafer 51. Please refer to FIG. 5B together.
  • the first insulating layer 52 may be a planarization layer.
  • the first insulating layer 52 may be made of an inorganic insulating material or an organic insulating material.
  • the inorganic insulating material may be silicon dioxide (SiO 2 ), silicon nitride (SiN 4 ), or the like, and the organic insulating material may be a polymer or resin.
  • the first insulating layer 52 is a polymer film, such as photosensitive polyimide (PI), polybenzoxazole (PBO), and the like.
  • the method for forming the planarized first insulating layer 52 may include, but is not limited to, the following manners:
  • the prepared first insulating layer 52 may be thin, and the first insulating layer 52 may be formed by a spin coating method.
  • the spin coating process usually includes three steps of batching, high-speed rotation, and evaporation to form a film.
  • the thickness of the film is controlled by controlling the time, speed, dripping amount, and concentration and viscosity of the solution used.
  • the passive device itself has a large thickness, and the first insulating layer 52 needs to completely cover the passive devices, so that the thickness of the first insulating layer 52 must be greater than that of any passive device. Device thickness.
  • a dry film formed of the first material (such as PI) can be laid on the wafer, and the dry film is melted and flows on the wafer by heating to make the formed polymer film flatten.
  • the solvent in the film is evaporated and evaporated, and the first insulating layer is formed by curing.
  • the preparation method of the first insulating layer can overcome the disadvantage that the thick first insulating layer cannot be prepared by the spin coating method, and is an important process for implementing chip packaging including IPD and passive components.
  • the thickness of the first insulating layer 52 is greater than the thickness of any one of the passive devices.
  • the thickness of the first insulating layer 52 may be 20um-120um.
  • the first insulation layer 52 also includes other preparation methods, which are not limited in the embodiment of the present application.
  • Step S13 A first via 520 is opened on the first insulating layer 52, and the first via 520 is used to expose a signal connection terminal (not shown) of the bare chip 511.
  • the signal connection terminal is used for coupling an internal circuit of the bare chip 511 to an external circuit, and may include an input terminal and / or an output terminal. Please also refer to FIG. 5C.
  • the signal connection terminal may be a pad or an electrode provided on the surface of the wafer 51, and is an input terminal or an output terminal of the bare chip 511 for coupling the bare chip 511 to an external circuit.
  • a first via hole 520 may be formed on the first insulating layer 52 by a photolithography process. For example, a photoresist is coated on the first insulating layer 52, the photoresist is exposed through a photomask, and the photoresist is removed by a developing solution to form a patterned photoresist. In order to etch the first insulating layer 52 with a mask, a first via hole 520 penetrating the first insulating layer 52 is formed at a position blocked by the photomask on the first insulating layer 52.
  • a first via hole 520 may be formed on the first insulating layer 52 through a photomask and a developing process.
  • the first insulating layer 52 is a negative photoresist, and a position corresponding to the input terminal and / or output terminal of the bare chip on the first insulating layer 52 is blocked by a photomask, and other positions on the first insulating layer 52 are exposed, and then The developing solution removes the unexposed photoresist, and forms a first via hole 520 penetrating the first insulating layer 52 at a position blocked by the photomask on the first insulating layer 52.
  • the etching or etching process includes dry etching and wet etching, and is selected according to the characteristics of the material to be etched.
  • first via hole 520 may also include other forming methods, such as a laser drilling method, which is not limited in the embodiment of the present application.
  • Step S14 A redistribution layer 53 is formed on a surface of the first insulating layer 52 facing away from the wafer 51.
  • the redistribution layer 53 fills the first via hole 520 and is connected to the signal connection end. Please also refer to FIG. 5D.
  • the redistribution layer 53 is formed of a conductive material.
  • the conductive material may be a metal, such as copper (Cu), silver (Ag), aluminum (Al), or another metal or metal alloy.
  • the conductive material may also be indium oxide. Tin (ITO), graphite, graphene, and the like are not limited in the examples of the present application.
  • the redistribution layers 53 on the respective bare chips 511 are independent and insulated from each other.
  • step S14 may be: forming a first conductive layer on the first insulating layer 52 through a plating process, and patterning the first conductive layer through a photolithography process to form a redistribution layer 53.
  • Step S15 forming a second insulating layer 54 covering the redistribution layer 53 and the first insulating layer 52. Please also refer to FIG. 5E.
  • the second insulating layer 54 may be a planarization layer.
  • the second insulating layer 54 may be made of an inorganic insulating material or an organic insulating material.
  • the inorganic insulating material may be silicon dioxide (SiO 2 ), silicon nitride (SiN 4 ), or the like, and the organic insulating material may be a polymer or resin.
  • the second insulating layer 54 is a polymer film, such as photosensitive polyimide (PI), polybenzoxazole (PBO), and the like.
  • the thickness of the redistribution layer 53 is small, and the thickness of the second insulating layer 54 covering the redistribution layer 53 is not less than the thickness of the redistribution layer 53.
  • the method for forming the second insulating layer 54 may include, but is not limited to, the following manners:
  • the planarized second insulating layer 54 may be formed on a surface of the first insulating layer 52 and the redistribution layer 52 facing away from the wafer 51 by a spin coating method.
  • the spin coating process usually includes three steps of batching, high-speed rotation, and evaporation to form a film.
  • the thickness of the film is controlled by controlling the time, speed, dripping amount, and concentration and viscosity of the solution used.
  • the second insulating layer 54 may also be formed on the surfaces of the first insulating layer 52 and the redistribution layer 53 facing away from the wafer 51 by a chemical vapor deposition method.
  • the second insulating layer 54 also includes other preparation methods, which are not limited in the embodiment of the present application.
  • the thickness of the second insulating layer 54 may be 5-30um.
  • Step S16 A second via 540 is opened on the second insulating layer 54, and the second via 540 is used to partially expose the redistribution layer 53. Please also refer to FIG. 5F.
  • a second via hole 540 can be formed on the second insulating layer 54 by a photolithography process. Specifically, a photoresist is coated on the second insulating layer 54, the photoresist is exposed through a photomask, and the photoresist is removed by a developing solution to form a patterned photoresist. The adhesive etches the second insulating layer 54 as a mask, and a second via hole 540 penetrating the second insulating layer 54 is formed at a position blocked by the photomask on the second insulating layer 54.
  • a second via hole 540 may be formed on the second insulating layer 54 through a photomask and a developing process. Specifically, if the second insulating layer 54 is a negative photoresist, a position corresponding to a part of the redistribution layer 53 on the second insulating layer 54 is blocked by a photomask, other positions on the second insulating layer 54 are exposed, and then removed by a developer The unexposed photoresist forms a second via hole 540 penetrating the second insulating layer 54 at a position blocked by a photomask on the second insulating layer 54.
  • the second via hole 540 may also include other forming methods, such as a laser drilling method, which is not limited in the embodiment of the present application.
  • Step S17 forming a conductive post 55 filling the second via hole 540, a first end of the conductive post 55 is electrically connected to the internal circuit of the bare chip 511, and an end face of the second end of the conductive post 55 is higher than the second insulating layer 54 The back faces the surface of the bare chip 511. Please also refer to FIG. 5G.
  • the conductive pillar 55 is formed of a conductive material.
  • the conductive material may be a metal, such as copper (Cu), silver (Ag), tin (Sn), aluminum (Al), or other metal or metal alloy. It can be indium tin oxide (ITO), graphite, graphene, and the like, which are not limited in the examples of the present application.
  • An implementation manner of step S17 may be: forming a second conductive layer on the second insulating layer 54 through a coating process, and patterning the second conductive layer through a photolithography process to form a conductive post 55.
  • the diameter of the conductive pillar 55 may be 100-1000um.
  • the conductive post may also be prepared by other methods, such as electroplating, printing, welding, or a combination thereof, which are not limited in the embodiments of the present application.
  • Step S18 Dicing the wafer to obtain chips corresponding to the multiple bare chips one-to-one. Cutting can be performed by mechanical cutting, laser cutting or a combination thereof. Please refer to FIG. 5H and FIG. 5I together.
  • Step S2 The second end of the conductive post 55 is bonded to the carrier substrate 56 to fix the chip on the carrier substrate 56 with a gap between adjacent chips. Please also refer to Figure 5J.
  • a carrier substrate 56 is provided, an adhesive layer 57 is coated on the carrier substrate 56, a chip is inverted, and an end surface of the conductor post 55 is bonded to the carrier substrate 56 through the adhesive layer 57.
  • the obtained multiple chip arrays are arranged and bonded to the carrier substrate 56 at intervals. Please also refer to a cross-sectional view of a chip array structure shown in FIG. 5K.
  • the carrier substrate 56 is used for carrying a plastic sealing material to form a plastic sealing material.
  • the adhesive layer 57 bonds the conductive post 55 and the carrier substrate 56 to fix the chip.
  • Step S3 forming a plastic encapsulation material 58 for the fully-wrapped chip. It should be understood that there is a gap between the conductive post 55 and the carrier substrate 56, and the plastic sealing material 58 may fill the gap between the conductive post 55 and the carrier substrate 56. The conductive post penetrates the plastic sealing material 58, and then completely encapsulates the chip. Please also refer to FIG. 5L.
  • the material of the molding material 58 may be a molding material, and the molding material is epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, or the like.
  • Epoxy Molding Compound EMC uses epoxy resin as the matrix resin, phenolic resin as the curing agent, plus some auxiliary additives, such as fillers, flame retardants, colorants, coupling agents, etc. Under the action of heat and curing agent, the epoxy ring-opening of the epoxy resin chemically reacts with the phenolic resin to produce a cross-linking curing effect to make it a thermosetting plastic.
  • a low-viscosity molding compound is drip-irrigated on the carrier substrate 56 and the second surface of the chip, and the molding compound fills the gap between the first surface of the chip and the carrier substrate 56 and wraps the chip.
  • the molding material is cured by heating to form the molding material 58.
  • the greater the thickness of the plastic packaging material 58 on the chip surface the greater the strength of the plastic packaging material 58 in controlling the warpage and deformation of the chip.
  • the larger the chip size the greater the degree of warpage and deformation. Therefore, by controlling the thickness of the plastic sealing material 58 on the first and second surfaces of the chip, the control of the warpage and deformation of the chip in the chip packaging structure can be controlled; by thickening the plastic sealing material 58 on the first and second surfaces of the chip, , To achieve the packaging of large-size chips (such as 8mm * 8mm chips).
  • the conductor post Since the conductor post is usually prepared by a coating method, its height can be precisely controlled. By controlling the height of the conductor post, the thickness of the plastic packaging material on the first surface of the chip can be accurately controlled to obtain a chip packaged with the plastic packaging material with a specific thickness.
  • Step S4 Cutting the molding material 58 based on the gap before the chip and removing the carrier substrate 56 to obtain a plurality of chip packaging structures. Please also refer to the chip package structure shown in FIGS. 5M-5O.
  • the method further includes: step S31, forming a solder ball 59 on the second end of the conductive post 55, that is, a planting ball, so that the chip is electrically connected through the solder ball 59 Circuit.
  • the solder ball 59 obtained by this method is located outside the plastic sealing material 58, which does not restrict the free melting and solidification process of the solder alloy when the solder ball 59 is soldered at high temperature, and improves the soldering firmness of the chip and the external circuit.
  • surface treatment processes such as Organic Solderability Preservatives (OSP), Electroless Nickel / Immersion Gold (ENIG), and electroless tin plating may be performed on the conductive pillar 111.
  • OSP Organic Solderability Preservatives
  • ENIG Electroless Nickel / Immersion Gold
  • electroless tin plating may be performed on the conductive pillar 111.
  • the carrier substrate 56 may be removed first and then cut, or the carrier substrate 56 may be cut and removed first. In the embodiment of the present application, the carrier substrate 56 is first removed and the ball is planted and then cut.
  • FIG. 5M When the adhesive layer 57 and the carrier substrate 56 are removed, a chip package structure as shown in FIG. 5M is obtained; when a solder ball 59 is formed on the end surface of the conductor post 55, a chip package structure as shown in FIG. 5N is obtained; After cutting the plastic encapsulation material 58 with a gap, the chip package structure shown in FIG. 5O is obtained.
  • the chip packaging method provided in the embodiment of the present application includes a plurality of chips.
  • a conductive post is provided on a first surface of the chip.
  • a first end of the conductive post is coupled to an internal circuit of the chip, and a second end of the conductive post is used.
  • the end face of the second end of the conductor post is higher than the first surface, and the chip is bonded to the carrier substrate through the second end of the conductor post.
  • the plastic sealing material can fill the conductor
  • the gap between the pillar and the carrier substrate so as to fully encapsulate the chip, while the plastic packaging material of the chip completely protects the surface of the chip, it can also balance the stress between the chip and the plastic packaging material in all directions, thereby avoiding the chip in a certain direction Cracking and chipping of the chip caused by excessive stress improve the long-term reliability of the packaged chip structure.
  • the one-time molding of the plastic encapsulation material of the fully-wrapped chip can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, thereby preventing the external water vapor from entering the chip through the interface to cause the chip to fail, improving the plastic encapsulation material Form the sealing performance of the plastic package structure, and improve the long-term reliability of the chip.
  • the molding material formed after the molding material is cured has strong mechanical strength, it can withstand the test pressure.
  • the chip packaging structure obtained by the chip packaging method does not contain process glue. , Can avoid the impact of process glue on the chip, and further improve the long-term reliability of the packaged chip structure.
  • FIG. 6 is a schematic structural diagram of an integrated circuit according to an embodiment of the present application.
  • the integrated circuit includes: a substrate 61 and a chip 62.
  • the chip 62 is fully wrapped with a plastic sealing material 63, and the chip 62 is provided with a conductor.
  • Post 621, the conductor post 621 passes through the molding material 63, and the chip 62 is supported on the substrate 61.
  • the first end of the conductor post 621 is coupled to the internal circuit of the chip 62, and the second end of the conductor post 621 is coupled to the substrate 61. Circuit.
  • the chip 62 may be disposed on the upper surface of the substrate 61 (see FIG. 6), or may be hung on the lower surface of the substrate 61, which is not limited in the embodiment of the present application. It can be understood that a circuit is provided on the substrate 61, and other chips can also be integrated to enhance the function of the integrated circuit.
  • the chip packaging structure formed by the plastic packaging material 63 and the chip 62 may be any one of the chip packaging structures described above. For details, refer to the related descriptions in the embodiments of the chip packaging structure shown in FIG. 1 and FIG. 2, which are not described in this application.
  • the chip 62 shown in FIG. 6 is a preliminary packaged chip, and the chip 62 includes a conductor post 621, a bare chip 622, a first insulation layer 623, a redistribution layer 624, and a second insulation layer 625.
  • the conductor post 621 of the chip 62 or the solder ball on the conductor post 621 can be directly soldered to the circuit of the substrate 61 or connected by a wire stitching process to achieve the coupling between the internal circuit in the chip 62 and the circuit on the substrate 61.
  • the integrated circuit may be integrated with a central processing unit (CPU), memory, and the like.
  • CPU central processing unit
  • memory and the like.
  • FIG. 7 is a schematic structural diagram of an integrated circuit device according to an embodiment of the present application.
  • the integrated circuit device includes an integrated circuit 71.
  • the integrated circuit 71 may be the integrated circuit shown in FIG.
  • the related description in the integrated circuit described in 6 is not repeated in the embodiment of the present application.
  • the integrated circuit 71 may be integrated with a CPU, a memory, and the like.
  • the integrated circuit device may further include a power management module 72 for supplying power to the integrated circuit 71.
  • the integrated circuit device may further include a communication module 73, an input module 74, and / or an output module 75, and the like.
  • the communication module 73 is used to realize the communication connection between the integrated circuit device and other devices or the Internet;
  • the input module 74 is used to enable the user to input information into the integrated circuit device, which may include a touch panel, a keyboard, a camera, etc .;
  • an output module 75 It is used to realize that the integrated circuit device outputs information to the user, and may include a display panel and the like.
  • the power management module 72, the communication module 73, the input module 74, and / or the output module 75 are not necessary components of an integrated circuit device; the power management module 72, the communication module 73, the input module 74, and / or the output module 75 may also be It is integrated in the integrated circuit 71 or separately provided and coupled to the integrated circuit 71, which is not limited in the embodiment of the present application.
  • the integrated circuit device may be an electronic device including an integrated circuit 71, such as a smartphone, a tablet, a personal digital assistant, an e-book, a computer, a server, a smart bracelet, a virtual reality (VR) device, and an enhanced Reality (Augmented Reality, AR for short) equipment, digital TV, set-top boxes, etc.
  • an integrated circuit 71 such as a smartphone, a tablet, a personal digital assistant, an e-book, a computer, a server, a smart bracelet, a virtual reality (VR) device, and an enhanced Reality (Augmented Reality, AR for short) equipment, digital TV, set-top boxes, etc.
  • VR virtual reality
  • AR enhanced Reality
  • the size of the sequence numbers of the above processes does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not deal with the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • chip packaging method may be executed by a robot or a numerical control processing method, and the device software or process for executing the chip packaging method may be executed by executing computer program code stored in a memory. Chip packaging method.

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Abstract

本申请提供了一种芯片封装结构及芯片封装方法，该芯片封装结构包括芯片11以及全包裹该芯片的塑封材料12。其中，芯片11上设有导体柱111，该导体柱111穿过塑封材料该导体柱111的第一端被耦合至芯片11的内部电路，导体柱111的第二端用于芯片11耦合外电路。可见，该芯片封装结构通过塑封材料12全包裹芯片11，在对芯片11各个面保护的同时还可以平衡各个方向上芯片11与塑封材料12之间的应力，进而避免芯片11在某一方向上应力过大导致的芯片11的开裂、崩边等问题，提高封装芯片结构的长期可靠性。

Description

芯片封装结构及芯片封装方法 技术领域
本申请涉及芯片封装技术领域，尤其涉及一种芯片封装结构及芯片封装方法。
背景技术
晶圆级芯片规模封装(Wafer Level Chip Scale Packaging，简称WLCSP)，即晶圆级芯片封装方式，不同于传统的先切割再封测芯片封装方式，WLCSP是先在整片晶圆上进行封装和测试，然后再切割成一个个的IC颗粒，因此封装后的体积等同于IC裸晶的原尺寸。WLCSP封装方式，可缩小芯片模块尺寸，符合芯片对于机体空间的高密度需求。
通常WLCSP封装芯片包括硅层(裸芯片)、重布线层、塑封层以及用于芯片电连接外电路的焊球。其中，塑封层通常半包裹硅层和重布线层，塑封层、硅层、重布线层的热膨胀系数不同，当芯片工作时，会导致芯片在某一方向上应力过大，进而导致芯片向一个方向翘边变形，甚至引起导致的芯片的开裂、崩边等问题。
发明内容
第一方面，本申请实施例提供了一种芯片封装结构，包括：芯片和全包裹该芯片的塑封材料，芯片上设有导体柱，该导体柱穿过塑封材料，导体柱的第一端被耦合至所述芯片的内部电路，导体柱的第二端用于该芯片耦合外电路。
上述芯片封装结构通过塑封材料全包裹芯片，在对芯片各个面保护的同时还可以平衡各个方向上芯片与塑封材料之间的应力，进而避免芯片在某一方向上应力过大导致的芯片的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
在第一方面的一种实现中，该塑封材料为一体成型结构，可避免出现现有技术中多次形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高该塑封材料形成塑封结构的密封性，以及提高芯片的长期可靠性。
在第一方面的一种实现中，该塑封材料的外表面与导体柱的第二端的端面齐平。
进一步地，该芯片封装结构还包括：设置于导体柱的第二端上的焊球。该芯片封装结构中焊球位于塑封材料外，不会限制焊球在高温焊接时焊料合金的自由融熔和凝固过程，提高芯片与外电路的焊接的牢固性。
在第一方面的一种实现中，芯片包括：
裸芯片；
第一绝缘层，该第一绝缘层覆盖裸芯片；
重布线层，该重布线层设于第一绝缘层背对裸芯片的表面，且填充贯穿第一绝缘层的第一过孔，耦合至裸芯片的内部电路；
第二绝缘层，该第二绝缘层覆盖第一绝缘层以及部分覆盖重布线层，且开设用于显露部分重布线层的第二过孔；
导体柱，该导体柱填充第二过孔，该导体柱的第一端电连接至裸芯片的内部电路，导 体柱的第二端的端面高于第二绝缘层背对裸芯片的表面。
进一步地，该裸芯片的表面可以包括一个或多个无源器件，以增强芯片的功能。
进一步地，所述第一绝缘层的厚度为20um-120um。
第二方面，本申请实施例还提供了一种芯片封装方法，包括：
提供多个芯片，该芯片的第一表面上设有导体柱，该导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端用于该芯片耦合外电路；
将导体柱的第二端粘结在承载基板上，以在承载基板上固定芯片，相邻的芯片之间具有间隙；
形成全包裹该芯片的塑封材料；
基于芯片之间的间隙切割塑封材料并去除承载基板，以得到多个芯片封装结构。
上述芯片封装方法包括：提供多个芯片，该芯片第一表面上设有导体柱，导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端用于芯片耦合外电路，导体柱的第二端的端面高于第一表面，将芯片通过导体柱的第二端粘结在承载基板上，导体柱与承载基板之间存在空隙，塑封材料可以填充导体柱和承载基板之间的空隙，进而全包裹芯片，全包裹芯片的塑封材料在对芯片各个表面保护的同时还可以平衡各个方向上芯片与塑封材料之间的应力，进而避免芯片在某一方向上应力过大导致的芯片的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
而且，全包裹芯片各个表面的塑封材料一次成型，可避免出现现有技术中多次形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高该塑封材料形成塑封结构的密封性，以及提高芯片的长期可靠性。
在第一方面的一种实现中，在去除所述承载基板之后，可以在导体柱的第二端上形成焊球，以便芯片通过焊球耦合外电路。可见，该芯片封装结构中焊球位于塑封材料外，不会限制焊球在高温焊接时焊料合金的自由熔融和凝固过程，提高芯片与外电路的焊接的牢固性。
在第一方面的第一种实现中，提供多个芯片的一种实施方式可以是：
提供一晶圆，该晶圆包括多个裸芯片；
在晶圆的表面形成覆盖该多个裸芯片的第一绝缘层；
在第一绝缘层上开设第一过孔，该第一过孔用于暴露裸芯片的信号连接端，该信号连接端用于裸芯片耦合至外电路，该信号连接端可以是裸芯片中内部电路的输入端和/或输出端；
在第一绝缘层背对所述晶圆的表面上形成重布线层，该重布线层填充第一过孔并连接至所述信号连接端；
形成覆盖重布线层和第一绝缘层的第二绝缘层；
在第二绝缘层上开设第二过孔，该第二过孔用于部分暴露重布线层；
形成填充第二过孔的导体柱，该导体柱的第一端电连接至裸芯片的内部电路，该导体柱的第二端的端面高于所述第二绝缘层的背对裸芯片的表面；
切割第一绝缘层、第二绝缘层以及晶圆，得到与该多个裸芯片一一对应的芯片。
进一步地，裸芯片上还包括与裸芯片电连接的被动元件，其中，在晶圆的表面形成覆盖所述多个裸芯片的第一绝缘层的一种实现方式可以是：将第一材料组成的膏状体放置在晶圆上；加热该膏状体，固化形成第一绝缘层。
上述方法可以形成较厚第一绝缘层，实现无源器件集成到芯片中。
第三方面，本申请实施例还提供了一种集成电路设备，该集成电路设备包括：基板和芯片，该芯片被塑封材料全包裹，该芯片上设有导体柱，导体柱穿过塑封材料，芯片支撑于基板上，该导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端被耦合至基板上的电路。
上述集成电路设备中，塑封材料全包裹芯片，在对芯片各个面保护的同时还可以平衡各个方向上芯片与塑封材料之间的应力，进而避免芯片在某一方向上应力过大导致的芯片的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
在第三方面的一种实现中，塑封材料形成一体成型结构，可避免出现现有技术中多次形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高该塑封材料形成塑封结构的密封性，以及提高芯片的长期可靠性。
在第三方面的又一种实现中，塑封材料的外表面与导体柱第二端的端面齐平。
进一步地，导体柱的第二端上设有焊球，该焊球用于与基板上的电路直接焊接或通过引线焊接。该芯片封装结构中焊球位于塑封材料外，不会限制焊球在高温焊接时焊料合金的自由融熔和凝固过程，提高芯片与外电路的焊接的牢固性。
在第三方面的又一种实现中，该芯片可以包括：
裸芯片；
第一绝缘层，该第一绝缘层覆盖裸芯片；
重布线层，该重布线层设于第一绝缘层背对裸芯片的表面，且填充贯穿第一绝缘层的第一过孔，耦合至裸芯片的内部电路；
第二绝缘层，该第二绝缘层覆盖第一绝缘层以及部分覆盖重布线层，且开设用于显露部分所述重布线层的第二过孔；
导体柱，导体柱填充第二过孔，该导体柱的第一端电连接至裸芯片的内部电路，导体柱的第二端的端面高于第二绝缘层背对裸芯片的表面。
进一步地，裸芯片的表面包括一个或多个无源器件。
进一步地，第一绝缘层的厚度为20um-120um。
第四方面，本申请实施例还提供了一种集成电路，该集成电路包括：基板和芯片，该芯片被塑封材料全包裹，该芯片上设有导体柱，导体柱穿过塑封材料，芯片支撑于基板上，该导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端被耦合至基板上的电路。
上述集成电路中，塑封材料全包裹芯片，在对芯片各个面保护的同时还可以平衡各个方向上芯片与塑封材料之间的应力，进而避免芯片在某一方向上应力过大导致的芯片的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
在第四方面的一种实现中，塑封材料形成一体成型结构，可避免出现现有技术中多次 形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高该塑封材料形成塑封结构的密封性，以及提高芯片的长期可靠性。
在第四方面的又一种实现中，塑封材料的外表面与导体柱第二端的端面齐平。
进一步地，导体柱的第二端上设有焊球，该焊球用于与基板上的电路直接焊接或通过引线焊接。该芯片封装结构中焊球位于塑封材料外，不会限制焊球在高温焊接时焊料合金的自由融熔和凝固过程，提高芯片与外电路的焊接的牢固性。
在第四方面的又一种实现中，该芯片可以包括：
裸芯片；
第一绝缘层，该第一绝缘层覆盖裸芯片；
重布线层，该重布线层设于第一绝缘层背对裸芯片的表面，且填充贯穿第一绝缘层的第一过孔，耦合至裸芯片的内部电路；
第二绝缘层，该第二绝缘层覆盖第一绝缘层以及部分覆盖重布线层，且开设用于显露部分所述重布线层的第二过孔；
导体柱，导体柱填充第二过孔，该导体柱的第一端电连接至裸芯片的内部电路，导体柱的第二端的端面高于第二绝缘层背对裸芯片的表面。
进一步地，裸芯片的表面包括一个或多个无源器件。
进一步地，第一绝缘层的厚度为20um-120um。
附图说明
图1为本申请实施例提供的一种芯片封装结构的结构示意图；
图2为本申请实施例提供的另一种芯片封装结构的结构示意图；
图3为本申请实施例提供的一种芯片封装方法的流程示意图；
图4为本申请实施例提供的另一种芯片封装方法的流程示意图；
图5A-5O为本申请实施例提供的一种芯片封装方法的各流程对应的结构示意图；
图6为本申请实施例提供的一种集成电路的结构示意图；
图7为本申请实施例提供的一种集成电路设备的结构示意图。
具体实施方式
为便于理解，首先对一些概念和背景进行简单介绍。
印制电路板(Printed Circuit Board，PCB)，是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的载体。由于它是采用电子印刷术制作的，故被称为“印刷”电路板。通过板级表面组装技术(surface mount technology，SMT)实现芯片的I/O端与PCB的电气连接。
晶圆(wafer)，指硅半导体集成电路制作所用的硅晶圆，由于其形状为圆形，故称为晶圆。在硅晶圆上可加工制作成各种电路元件结构，而成为有特定电性功能的IC产品
晶片(die)，指晶圆切割下来的一个小块，为一个芯片。在晶圆未封装前，晶圆上的芯片或晶圆切割得到的芯片称为裸芯片。
无源元件，也称被动元件(passive components)，指在电路中不需要加电源即可在有信号时工作的元件，主要是电阻类、电感类和电容类的元件。
集成无源元件(Integrated Passive Devices，IPD)将分立的无源元件集成在衬底的内部，提高器件系统集成度，以减小整个产品的尺寸和重量。
半包裹，本申请中指塑封材料包裹芯片的部分表面，裸露芯片中非导体柱的部件，该导体柱为芯片上用于耦合外电路的连接端，也就是说芯片的至少一个表面未被塑封材料覆盖。通常芯片包括上表面、下表面以及四个侧面，例如，现有技术中，塑封材料通常包裹芯片中硅衬底上表面的部件(如，芯片的内部电路、重布线层等)，而硅衬底的下表面通常无塑封材料保护。
全包裹，本申请中指包裹芯片的各个表面，但芯片上用于耦合外电路的导体柱背对芯片的端面除外。在本申请实施例中，塑封材料全包裹芯片即为塑封材料包裹芯片上除导体柱背对芯片的端面之外的各个部分。
通常WLCSP封装芯片包括硅层(裸芯片)、重布线层以及用于芯片电连接外电路的焊球。该WLCSP的封装方式可能带来如下问题：
(1)在芯片切割过程中可能会出现硅层部分开裂、崩边的质量问题。
(2)芯片封装后芯片的背面是裸露的硅层，由于硅材料的脆性，不能承受后续电测试施加的压力，使得WLCSP封装芯片不能做测试而直接在板级使用，导致使用了该WLCSP封装芯片的产品次品率上升。
(3)由于硅层、重布线层、塑封材料的膨胀系数不同，导致在WLCSP封装芯片在板级高温制程过程中出现“爆米花”问题，影响长期可靠性差。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述。
本申请实施例中芯片为待封装芯片，可以是存储器(Memory)、微机电系统(Micro-Electro-Mechanical System，简称MEMS)、微波射频芯片、专用集成电路(Application Specific Integrated Circuit，简称ASIC)等芯片。应理解，这里所列举的芯片仅为示例性说明，本申请对此不作限定。
如图1所示芯片封装结构的示意图，该芯片封装结构包括芯片11和全包裹该芯片11的塑封材料12。其中，芯片11具有相对的第一表面和第二表面，芯片11的第一表面具有导体柱111，该导体柱111第一端被耦合至芯片11的内部电路，导体柱111的第二端用于芯片11耦合外电路。该导体柱111穿过塑封材料12，即导体柱111的第二端的端面高于第一表面，并显露于塑封材料12外。应理解，导体柱111的第一端和第二端为导体柱111相对的两端；外电路为芯片之外的电路，可以是基板上的电路。
可见，该芯片封装结构通过塑封材料12全包裹芯片11，在对芯片11各个面保护的同时还可以平衡各个方向上芯片11与塑封材料12之间的应力，进而避免芯片11在某一方向上应力过大导致的芯片11的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
如图2所示的芯片封装结构，芯片11可以是初步封装的芯片，该芯片11包括裸芯片112、第一绝缘层113、重布线层114、第二绝缘层115以及导体柱111。其中，第一绝缘层 113覆盖裸芯片114；重布线层114设于第一绝缘层113背对裸芯片112的表面，且填充贯穿第一绝缘层113的第一过孔116，耦合至裸芯片11的内部电路；第二绝缘层115覆盖第一绝缘层113以及部分覆盖重布线层114，且开设用于显露部分重布线层114的第二过孔117；导体柱111填充第二过孔117，导体柱111的第一端电连接至裸芯片112的内部电路，导体柱111的第二端的端面高于第二绝缘层115背对裸芯片112的表面。
可选地，芯片11可以就是裸芯片，该芯片11在制备时，芯片11第一表面的信号连接端被制备成导体柱，该导体柱的端面高于芯片的第一表面。通常芯片11的第一表面为芯片11上包括有缘元件的表面。信号连接段可以是芯片11中内部电路的输出端和/或输入端。
可选地，塑封材料12为一体成型结构，进而避免出现现有技术中多次形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高塑封膜的密封性，以及提高芯片的长期可靠性。
可选地，塑封材料12的膨胀系数小于第一绝缘层113的膨胀系数和第二绝缘层115的膨胀系数，当芯片封装结构在后续的工序需要加热时或芯片工作时会产生热，芯片11受热会产生膨胀，塑封材料12能够对其内部的芯片11产生作用力，均衡降低芯片11的膨胀程度，进而避免芯片的开裂、崩边，进一步地提高封装芯片结构的长期可靠性。
可选地，塑封材料12的外表面与导体柱111的端面齐平，如图1所示。
可选地，该芯片封装结构还包括设置于导体柱111的第二端上的焊球13。该芯片封装结构中焊球13位于塑封材料外，不会限制焊球13在高温焊接时焊料合金的自由熔融和凝固过程，提高芯片与外电路的焊接的牢固性。可以理解，焊球13不是本申请实施例中必须的部件，根据芯片具体使用场景的不同，该芯片封装结构可以无焊球13，而直接裸露裸芯片112或芯片封装结构的导体柱111，或者在导体柱111上进行有机保焊膜(Organic Solderability Preservatives，OSP)、化学镍金(Electroless Nickel/Immersion Gold，ENIG)、化学镀锡等表面处理工艺后使用。
本申请一实施例中，裸芯片112的表面包括一个或多个无源器件，以增强芯片的功能其中，该无源器件可以是集成无源元件118(IPD)和/或独立的无源元件119。
可以理解，当裸芯片112的表面包括一个或多个无源器件时，第一绝缘层113的厚度大于该任意一个无源器件的厚度。可选地，该第一绝缘层的厚度可以是20um-120um。
可选地，该芯片封装结构还可以包括基板，被封装材料包裹的芯片可以设置于基板的上表面，也可挂在基板的下表面，本申请实施例以不作限定。基板上可以包括电路，焊球可以通过引线连接至基板上电路，实现芯片内部电路与基板上电路的耦合。可选地，焊球或导体柱也可以直接焊接在基板上。
需要说明的是，第一绝缘层113或第二绝缘层115可以是平坦化层。第一绝缘层113或第二绝缘层115可以由无机绝缘材料或有机绝缘材料构成。其中，无机绝缘材料可以是二氧化硅(SiO 2)、氮化硅(SiN 4)等，有机绝缘材料可以是高分子聚合物或树脂等。通常，第一绝缘层113或第二绝缘层115为聚合物薄膜，如光敏性的聚酰亚胺(polyimide，PI)、聚苯并恶唑(ploybenzoxazole，PBO)等。
塑封材料12的材质可以环氧树脂(Epoxy Molding Compound，EMC)、聚乙烯、聚丙烯、聚烯烃、聚酰胺、聚亚氨酯等中的一种或多种的组合。例如塑封材料12为环氧树脂模塑料。
请参阅图3-图4，图3、图4是本申请实施例提供的两种芯片封装方法的流程示意图。请一并参阅图5A-5O所示的对应于图4所示的芯片封装方法的中各个步骤所得到的芯片封装结构的截面示意图。
步骤S1：提供多个芯片，该芯片具有相对的第一表面和第二表面，芯片的第一表面上设有导体柱，该导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端用于该芯片耦合外电路。导体柱的第二端的端面高于第一表面。
本申请一实施例中，芯片可以是裸芯片，该芯片在制备时，芯片第一表面的信号连接端被制备成导体柱，该导体柱的端面高于芯片的第一表面。通常芯片的第一表面为芯片上包括有缘元件的表面。
可选地，该芯片的第一表面还可以包括IPD，无源元件可以在芯片制备时被集成在芯片上。
本申请一实施例中，芯片可以是经过初步封装过程后的芯片，该初步封装的过程(即步骤S1)可以包括以下步骤：
步骤S11：提供一晶圆51，该晶圆51包括多个裸芯片511。请一并参阅图5A。
本发明一实施例中，该裸芯片511上可以包括一个或多个无源器件，以增强芯片的功能。无源器件可以是IPD512或者独立的无源元件513可以在芯片制备过程中，连接在裸芯片511的表面上。
步骤S12：在晶圆51的表面上形成覆盖该多个裸芯片511的第一绝缘层52。请一并参阅图5B。
可选地，第一绝缘层52可以是平坦化层。第一绝缘层52可以由无机绝缘材料或有机绝缘材料构成。其中，无机绝缘材料可以是二氧化硅(SiO 2)、氮化硅(SiN 4)等，有机绝缘材料可以是高分子聚合物或树脂等。通常，第一绝缘层52为聚合物薄膜，如光敏性的聚酰亚胺(polyimide，PI)、聚苯并恶唑(ploybenzoxazole，PBO)等。
其中，形成该平坦化的第一绝缘层52的方法可以包括但不限于以下方式：
对于不包含无源器件512的裸芯片511来说，制备的第一绝缘层52可以较薄，可以通过旋涂法(spin coating)来形成第一绝缘层52。旋涂工艺通常包括配料，高速旋转，挥发成膜三个步骤，通过控制匀胶的时间，转速，滴液量以及所用溶液的浓度、粘度来控制成膜的厚度。
对于设置了无源器件的裸芯片511上时，由于无源器件本身存在较大的厚度，第一绝缘层52需要完全覆盖无源器件，使得第一绝缘层52的厚度必须大于任意一个无源器件的厚度。此时，可以将第一材料(如PI)形成的干薄(dry film)平铺在晶圆上，通过加热，使得干膜熔融并在晶圆上流动以使形成的聚合物薄膜趋于平坦化以及挥发干膜内溶剂，固化形成第一绝缘层。该第一绝缘层的制备方式可以克服旋涂法不能制备较厚的第一绝缘层的缺点，是实现对包括IPD和被动元件的芯片封装中的重要一道工序。
可选地，当晶圆1上包括无源器件时，第一绝缘层52的厚度大于该任意一个无源器件的厚度，可选地，第一绝缘层52的厚度可以是20um-120um。
可以理解，第一绝缘层52还包括其他制备方式，本申请实施例不作限定。
步骤S13：在第一绝缘层52上开设第一过孔520，该第一过孔520用于暴露裸芯片511的信号连接端(图中未示出)。其中，信号连接端用于裸芯片511的内部电路耦合至外电路，可以包括输入端和/或输出端。请一并参阅图5C。
其中，信号连接端可以是设于晶圆51表面上的焊盘或电极等，为裸芯片511的输入端或输出端，用于裸芯片511耦合至外电路。
若第一绝缘层52为无机绝缘材料时，可以通过光刻工艺在第一绝缘层52上形成第一过孔520。例如，在第一绝缘层52上涂布光刻胶，通过光罩部分曝光光刻胶，再通过显影液部分去除光刻胶，形成图案化的光刻胶，进而以图案化的光刻胶为掩膜刻蚀第一绝缘层52，在第一绝缘层52上光罩遮挡的位置形成贯穿第一绝缘层52的第一过孔520。
若第一绝缘层52为光刻胶时，可以通过光罩和显影工艺在第一绝缘层52上形成第一过孔520。例如，第一绝缘层52为负光刻胶，通过光罩遮挡第一绝缘层52上与裸芯片的输入端和/或输出端对应的位置，曝光第一绝缘层52上其他位置，进而通过显影液去除未被曝光的光刻胶，形在第一绝缘层52上光罩遮挡的位置形成贯穿第一绝缘层52的第一过孔520。
其中，刻蚀或刻蚀工艺包括干刻和湿刻，以被刻蚀材料的特性来选择。
可以理解，第一过孔520还可以包括其他的形成方式，例如激光钻孔的方式等，本申请实施例不作限定。
步骤S14：在第一绝缘层52背离晶圆51的表面上形成重布线层53，该重布线层53填充第一过孔520并连接至信号连接端。请一并参阅图5D。
其中，重布线层53由导电材料形成，该导电材料可以是金属，如铜(Cu)、银(Ag)、铝(Al)或其他金属或金属的合金等，该导电材料还可以是氧化铟锡(ITO)、石墨、石墨烯等，本申请实施例不作限定。而且，各个裸芯片511上的重布线层53之间是相互独立的、绝缘的。
步骤S14的一种实现方式可以是：通过镀膜工艺在第一绝缘层52上形成第一导电层，在通过光刻工艺图案化该第一导电层，形成重布线层53。
步骤S15：形成覆盖重布线层53和第一绝缘层52的第二绝缘层54。请一并参阅图5E。
可选地，第二绝缘层54可以是平坦化层。第二绝缘层54可以由无机绝缘材料或有机绝缘材料构成。其中，无机绝缘材料可以是二氧化硅(SiO 2)、氮化硅(SiN 4)等，有机绝缘材料可以是高分子聚合物或树脂等。通常，第二绝缘层54为聚合物薄膜，如光敏性的聚酰亚胺(polyimide，PI)、聚苯并恶唑(ploybenzoxazole，PBO)等。
通常重布线层53厚度较小，覆盖该重布线层53的第二绝缘层54的厚度不小于重布线层53的厚度。形成第二绝缘层54的方法可以包括但不限于以下方式：
可以通过旋涂法(spin coating)来在第一绝缘层52和重布线层52的背离晶圆51的表面形成平坦化的第二绝缘层54。旋涂工艺通常包括配料，高速旋转，挥发成膜三个步骤，通过控制匀胶的时间，转速，滴液量以及所用溶液的浓度、粘度来控制成膜的厚度。
也可以通过化学气相沉积法在第一绝缘层52和重布线层53的背离晶圆51的表面形成第二绝缘层54。
可以理解，第二绝缘层54还包括其他制备方式，本申请实施例不作限定。
可选地，第二绝缘层54的厚度可以是5-30um。
步骤S16：在第二绝缘层54上开设第二过孔540，该第二过孔540用于部分暴露重布线层53。请一并参阅图5F。
同第一过孔520的形成方法，若第二绝缘层54为无机绝缘材料时，可以通过光刻工艺在第二绝缘层54上形成第二过孔540。具体的，在第二绝缘层54上涂布光刻胶，通过光罩部分曝光光刻胶，再通过显影液部分去除光刻胶，形成图案化的光刻胶，进而以图案化的光刻胶为掩膜刻蚀第二绝缘层54，在第二绝缘层54上光罩遮挡的位置形成贯穿第二绝缘层54的第二过孔540。
若第二绝缘层54为光刻胶时，可以通过光罩和显影工艺在第二绝缘层54上形成第二过孔540。具体的，若第二绝缘层54为负光刻胶，通过光罩遮挡第二绝缘层54上与部分重布线层53对应的位置，曝光第二绝缘层54上其他位置，进而通过显影液去除未被曝光的光刻胶，形在第二绝缘层54上光罩遮挡的位置形成贯穿第二绝缘层54的第二过孔540。
可以理解，第二过孔540还可以包括其他的形成方式，例如激光钻孔的方式等，本申请实施例不作限定。
步骤S17：形成填充第二过孔540的导体柱55，该导体柱55的第一端电连接至裸芯片511的内部电路，该导体柱55的第二端的端面高于第二绝缘层54上背对裸芯片511的表面。请一并参阅图5G。
其中，导体柱55由导电材料形成，该导电材料可以是金属，如铜(Cu)、银(Ag)、锡(Sn)、铝(Al)或其他金属或金属的合金等，该导电材料还可以是氧化铟锡(ITO)、石墨、石墨烯等，本申请实施例不作限定。
步骤S17的一种实现方式可以是：通过镀膜工艺在第二绝缘层54上形成第二导电层，在通过光刻工艺图案化该第二导电层，形成导体柱55。导电柱55的直径可以为100-1000um。
导体柱还可以是其他制备方法，比如电镀法、印刷，焊接或其组合，本申请实施例不作限定。
步骤S18：切割晶圆，得到与多个裸芯片一一对应的芯片。切割可以采用机械切割、激光切割或其结合等方式。请一并参阅图5H和图5I。
步骤S2：将导体柱55的第二端粘结在承载基板56上，以在承载基板56上固定芯片，相邻的芯片之间具有间隙。请一并参阅图5J。
具体的，提供一承载基板56，在该承载基板56上涂布胶层57，将一芯片倒置，将导体柱55的端面通过胶层57粘结在承载基板56上。同理，将得到的多个芯片阵列排布，间隔粘结在承载基板56。请一并参阅图5K所示的一种芯片阵列结构的截面图。
其中，承载基板56用于承载塑封材料，以形成塑封材料。胶层57粘结导体柱55与承载基板56，以固定芯片。
步骤S3：形成全包裹芯片的塑封材料58。应理解，导体柱55与承载基板56之间存在空隙，塑封材料58可以填充导体柱55和承载基板56之间的空隙，导体柱贯穿塑封材料58，进而全包裹芯片。请一并参阅图5L。
其中，塑封材料58的材料可以是塑封材料，该塑封材料为环氧树脂、聚乙烯、聚丙烯、聚烯烃、聚酰胺、聚亚氨酯等。例如环氧树脂模塑料(Epoxy Molding Compound，EMC)。 EMC是以环氧树脂为基体树脂，以酚醛树脂为固化剂，再加上一些辅助添加剂，如填充剂、阻燃剂、着色剂、偶联剂等。在热和固化剂的作用下环氧树脂的环氧基开环与酚醛树脂发生化学反应，产生交联固化作用使之成为热固性塑料。
具体的，将低粘度的塑封材料滴灌在承载基板56和芯片的第二表面，塑封材料填充芯片的第一表面与承载基板56之间的空隙，并包裹芯片，当塑封材料的厚度达到预设厚度之后，对塑封材料进行加热固化，形成塑封材料58。
应理解，芯片表面上塑封材料58的厚度越后，塑封材料58控制芯片的翘曲变形的力度越大。芯片的尺寸越大，其翘曲变形的程度越大。因而，可以通过控制芯片第一表面和第二表面上塑封材料58的厚度来控制对芯片封装结构中芯片的翘曲变形的控制力度；通过加厚芯片第一表面和第二表面上塑封材料58，实现对大尺寸芯片(例如8mm*8mm芯片)的封装。
由于导体柱通常采用镀膜的方法制备，其高度可以精确控制。通过控制对导体柱高度，可以精确控制芯片的第一表面上塑封材料的厚度，以得到特定厚度的塑封材料封装的芯片。
步骤S4：基于芯片之前的间隙切割塑封材料58并去除承载基板56，以得到多个芯片封装结构。请一并参阅图5M-5O所示的芯片封装结构。
可选地，步骤S3、S4或除承载基板56之后，该方法还包括：步骤S31，在导体柱55的第二端上形成焊球59，即植球，以便芯片通过焊球59电连接外电路。通过该方法得到的焊球59位于塑封材料58外，不会限制焊球59在高温焊接时焊料合金的自由熔融和凝固过程，提高芯片与外电路的焊接的牢固性。
可选地，S4之后，还可以在在导体柱111上进行有机保焊膜(Organic Solderability Preservatives，OSP)、化学镍金(Electroless Nickel/Immersion Gold，ENIG)、化学镀锡等表面处理工艺。
可以先去除承载基板56再切割，也可以先切割在去除承载基板56，本申请实施例以先去除承载基板56、植球再切割为例来说明。
当去除胶层57和承载基板56后，得到如图5M所示的芯片封装结构；当导体柱55的端面形成焊球59后，得到如图5N所示的芯片封装结构；当基于芯片之间的间隙切割塑封材料58后得到如图5O所示的芯片封装结构。
可见，本申请实施例提供的芯片封装方法，通过提供多个芯片，该芯片第一表面上设有导体柱，导体柱的第一端被耦合至芯片的内部电路，导体柱的第二端用于芯片耦合外电路，导体柱的第二端的端面高于第一表面，将芯片通过导体柱的第二端粘结在承载基板上，导体柱与承载基板之间存在空隙，塑封材料可以填充导体柱和承载基板之间的空隙，进而全包裹芯片，全包裹芯片的塑封材料在对芯片各个表面保护的同时还可以平衡各个方向上芯片与塑封材料之间的应力，进而避免芯片在某一方向上应力过大导致的芯片的开裂、崩边等问题，提高封装芯片结构的长期可靠性。
而且，全包裹芯片的塑封材料一次成型，可避免出现现有技术中多次形成的塑封材料之间的分界面，进而防止外界水蒸气通过分界面进入到芯片引起芯片的失效，提高该塑封材料形成塑封结构的密封性，以及提高芯片的长期可靠性。
进一步地，由于塑封材料固化后形成的塑封材料具有较强的机械强度，可以承受测试 的压力。
进一步地，现有技术中芯片封装结构大量采用过程胶，得到的芯片封装结构中部分过程胶永久性存在。由于半导体材料、塑封材料、胶材料热膨胀系数的不同，芯片在温度变化的环境中，胶材料会引起芯片产生应力，进而引起芯片的变形，该芯片封装方法得到的芯片封装结构内部不包含过程胶，可避免过程胶对芯片的影响，进一步提高封装芯片结构的长期可靠性。
上述芯片封装结构或芯片封装方法制备形成的芯片，进一步地可以应用于集成电路中。请参阅图6，图6是本申请实施例提供的一种集成电路的结构示意图，该集成电路包括：基板61和芯片62，该芯片62被塑封材料63全包裹，该芯片62上设有导体柱621，导体柱621穿过塑封材料63，芯片62支撑于基板61上，该导体柱621的第一端被耦合至芯片62的内部电路，导体柱621的第二端被耦合至基板61上的电路。
可选地，芯片62可以设置于基板61的上表面(如图6)，也可挂在基板61的下表面，本申请实施例以不作限定。可以理解，基板61上设有电路，还可以集成有其他芯片，以增强集成电路的功能。
其中，塑封材料63与芯片62形成的芯片封装结构可以是上述芯片封装结构中任意一种芯片封装结构，可参见上述图1、图2芯片封装结构实施例中相关描述，本申请不再赘述。例如，如图6所示的芯片62为初步封装的芯片，该芯片62包括导体柱621、裸芯片622、第一绝缘层623、重布线层624以及第二绝缘层625。关于导体柱621、裸芯片622、第一绝缘层623、重布线层624以及第二绝缘层625的位置关系可分别参见上述图1中导体柱111、裸芯片112、第一绝缘层113、重布线层114以及第二绝缘层115相关描述，本申请实施例不再赘述。
通常，芯片62的导体柱621或者导体柱621上焊球可以与基板61的电路直接焊接或者通过引线缝合工艺进行连接，以实现芯片62中内部电路与基板61上电路的耦合。
在一种具体实现中，集成电路可以集成有中央处理器(central processing unit，CPU)、存储器等。
上述芯片封装结构、芯片封装方法制备形成的芯片或集成电路，进一步地可以应用于集成电路设备中。请参阅图7，图7是本申请实施例提供的一种集成电路设备的结构示意图，该集成电路设备包括集成电路71，该集成电路71可以是图6所示的集成电路，具体可参见图6所述的集成电路中相关描述，本申请实施例不再赘述。
在一种具体实现中，集成电路71可以集成有CPU、存储器等。可选地，该集成电路设备还可以包括电源管理模块72，用于对集成电路71进行供电。可选地，该集成电路设备还可以包括通信模块73、输入模块74和/或输出模块75等。其中，通信模块73用于实现集成电路设备与其他设备或互联网的通信连接；输入模块74用于实现用户将信息输入到集成电路设备，可以包括，触控面板、键盘、摄像头等；输出模块75用于实现集成电路设备向用户输出信息，可以包括显示面板等。应理解，电源管理模块72、通信模块73、输入模块74和/或输出模块75不是集成电路设备必须的组成部件；电源管理模块72、通信模块73、输入模块74和/或输出模块75也可以集成在集成电路71中，或单独设置，耦合至集 成电路71，本申请实施例不做限定。
本申请实施例中集成电路设备可以是包括集成电路71的电子设备，如智能手机、平板电脑、个人数字助理、电子书、计算机、服务器、智能手环、虚拟现实(VirtualReality，VR)设备、增强现实(Augmented Reality，简称AR)设备、数字电视、机顶盒等。应理解，这里所列举的电子设备仅为示例性说明，本申请对此不作限定。
以上不同实施例之间可以交叉引用。例如当一个实施例对某一方面的技术细节做了简略描述，可进一步参考其他实施例的介绍。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，上述列举的芯片封装方法的各实施例，可以通过机器人或者数控加工方式来执行，用于执行芯片封装方法的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述芯片封装方法。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种芯片封装结构，其特征在于，包括：芯片和全包裹所述芯片的塑封材料，所述芯片上设有导体柱，所述导体柱穿过所述塑封材料，所述导体柱的第一端被耦合至所述芯片的内部电路，所述导体柱的第二端用于所述芯片耦合外电路。
  2. 如权利要求1所述的芯片封装结构，其特征在于，所述塑封材料形成一体成型结构。
  3. 如权利要求1或2所述的芯片封装结构，其特征在于，所述塑封材料的外表面与所述导体柱的第二端的端面齐平。
  4. 如权利要求3所述的芯片封装结构，其特征在于，所述芯片封装结构还包括：设置于所述导体柱的第二端上的焊球。
  5. 如权利要求1-4任意一项权利要求所述的芯片封装结构，其特征在于，所述芯片包括：
    裸芯片；
    第一绝缘层，所述第一绝缘层覆盖所述裸芯片；
    重布线层，所述重布线层设于所述第一绝缘层背对所述裸芯片的表面，且填充贯穿所述第一绝缘层的第一过孔，耦合至所述裸芯片的内部电路；
    第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层以及部分覆盖所述重布线层，且开设用于显露部分所述重布线层的第二过孔；
    导体柱，所述导体柱填充所述第二过孔，所述导体柱的第一端耦合至所述裸芯片的内部电路，且所述导体柱的第二端的端面高于所述第二绝缘层背对所述裸芯片的表面。
  6. 如权利要求5所述的芯片封装结构，其特征在于，所述裸芯片的表面包括一个或多个无源器件。
  7. 如权利要求6所述的芯片封装结构，其特征在于，所述第一绝缘层的厚度为20um-120um。
  8. 一种集成电路设备，包括基板和芯片，所述芯片被塑封材料全包裹，所述芯片上设有导体柱，所述导体柱穿过所述塑封材料，所述芯片支撑于所述基板上，所述导体柱的第一端被耦合至所述芯片的内部电路，所述导体柱的第二端被耦合至所述基板上的电路。
  9. 如权利要求8所述的集成电路设备，其特征在于，所述塑封材料形成一体成型结构。
  10. 如权利要求8或9所述的集成电路设备，其特征在于，所述塑封材料的外表面与 所述导体柱的第二端的端面齐平。
  11. 如权利要求8-10任意一项权利要求所述的集成电路设备，其特征在于，所述导体柱的第二端上设有焊球，所述焊球用于与所述基板上的电路直接焊接或通过引线焊接。
  12. 如权利要求8-11任意一项权利要求所述的集成电路设备，其特征在于，所述芯片包括：
    裸芯片；
    第一绝缘层，所述第一绝缘层覆盖所述裸芯片；
    重布线层，所述重布线层设于所述第一绝缘层背对所述裸芯片的表面，且填充贯穿所述第一绝缘层的第一过孔，耦合至接所述裸芯片的内部电路；
    第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层以及部分覆盖所述重布线层，且开设用于显露部分所述重布线层的第二过孔；
    导体柱，所述导体柱填充所述第二过孔，所述导体柱的第一端耦合至裸芯片的内部电路，所述导体柱的第二端的端面高于所述第二绝缘层背对所述裸芯片的表面。
  13. 如权利要求12所述的集成电路设备，其特征在于，所述裸芯片的表面包括一个或多个无源器件。
  14. 如权利要求13所述的集成电路设备，其特征在于，所述第一绝缘层的厚度为20um-120um。
  15. 一种芯片封装方法，其特征在于，包括：
    提供多个芯片，所述芯片的第一表面上设有导体柱，所述导体柱的第一端被耦合至所述芯片的内部电路，所述导体柱的第二端用于所述芯片耦合外电路；
    将所述导体柱的第二端粘结在承载基板上，以在所述承载基板上固定所述芯片，相邻的所述芯片之间具有间隙；
    形成全包裹所述芯片的塑封材料；
    基于所述间隙切割所述塑封材料并去除所述承载基板，以得到多个芯片封装结构。
  16. 如权利要求15所述的方法，其特征在于，所述去除所述承载基板之后，所述方法还包括：在所述导体柱的第二端上形成焊球，以便所述芯片通过所述焊球耦合所述外电路。
  17. 如权利要求15或16所述的方法，其特征在于，所述提供多个芯片包括：
    提供一晶圆，所述晶圆包括多个裸芯片；
    在所述晶圆的表面形成覆盖所述多个裸芯片的第一绝缘层；
    在所述第一绝缘层上开设第一过孔，所述第一过孔用于暴露所述裸芯片的信号连接端，所述信号连接端用于所述裸芯片耦合至外电路；
    在所述第一绝缘层背对所述晶圆的表面上形成重布线层，所述重布线层填充所述第一过孔并连接至述信号连接端；
    形成覆盖所述重布线层和所述第一绝缘层的第二绝缘层；
    在所述第二绝缘层上开设第二过孔，所述第二过孔用于部分暴露所述重布线层；
    形成填充所述第二过孔的导体柱，所述导体柱的第一端电连接至所述裸芯片的内部电路，所述导体柱的第二端的端面高于所述第二绝缘层背对所述裸芯片的表面；
    切割所述第一绝缘层、所述第二绝缘层以及所述晶圆，得到与所述多个裸芯片一一对应的芯片。
  18. 如权利要求17任意一项权利要求所述的方法，其特征在于，所述裸芯片上还包括与所述裸芯片电连接的被动元件，所述在所述晶圆的表面形成覆盖所述多个裸芯片的第一绝缘层包括：
    将第一材料组成的干膜放置在所述晶圆上；
    加热所述干膜，固化形成第一绝缘层。
PCT/CN2018/092861 2018-06-26 2018-06-26 芯片封装结构及芯片封装方法 WO2020000179A1 (zh)

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