TW201603216A - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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TW201603216A
TW201603216A TW103123900A TW103123900A TW201603216A TW 201603216 A TW201603216 A TW 201603216A TW 103123900 A TW103123900 A TW 103123900A TW 103123900 A TW103123900 A TW 103123900A TW 201603216 A TW201603216 A TW 201603216A
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package structure
encapsulant
dielectric layer
conductive
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TWI567888B (zh
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陳彥亨
詹慕萱
紀傑元
林畯棠
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矽品精密工業股份有限公司
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Priority to TW103123900A priority Critical patent/TWI567888B/zh
Priority to CN201410421447.6A priority patent/CN105304583B/zh
Priority to US14/736,436 priority patent/US9515040B2/en
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Abstract

一種封裝結構及其製法，該封裝結構係包括電子元件、封裝膠體、複數導電元件與線路重佈層，該電子元件係具有相對之作用面與非作用面，該封裝膠體係包覆該電子元件，且具有外露該作用面的第一表面及相對該第一表面之第二表面，該導電元件係貫穿該封裝膠體之第一表面與第二表面，該導電元件係為金屬球，該線路重佈層係形成於該第一表面與作用面上，且電性連接於該些電子元件與導電元件，本發明不需進行雷射製程以形成電性連接用之開口，藉此簡化製程而能有效降低成本，提升產品可靠度。

Description

封裝結構及其製法
本發明係有關一種半導體封裝結構及其製法，尤指一種可減少製程之半導體封裝結構及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置在功能上性能、功率及速度等需求，以及在型態上微型化與半導體裝置整合等需求，遂發展出堆疊式封裝結構(Package on package，POP)之技術。
第1A至1B圖係為習知用於堆疊式封裝結構之封裝結構之製法的剖視示意圖。
如第1A圖所示，提供一具有複數電性接觸墊101與導電盲孔102之承載件10，將具有複數電極墊110之電子元件11以其電極墊110電性連接於該導電盲孔102，形成封裝膠體12以包覆該電子元件11及該些電性接觸墊101，進行研磨製程使該電子元件11之表面外露於該封裝膠體12。
如第1B圖所示，以雷射製程形成供該些電性接觸墊101外露之開口121，後續將於該開口121中填充導電元件(未圖示)，供後續堆疊之另一封裝件電性連接該電性接觸墊101，以完成一堆疊式封裝結構。
惟，由於上述習知之封裝結構的該些電性接觸墊101被包覆於無法透光之封裝膠體12內，而無法確認該些電性接觸墊101之位置，致使無法或精確形成該開口121，而產生該開口121之位置誤差現象。
此外，以雷射製程形成該開口121，不僅造成於該開口121附近產生殘渣，又由於一般開口121數量很多(I/O數量多)且雷射僅能逐一形成該開口121，雷射製程時間長，且雷射設備昂貴，所以藉由雷射燒灼方式形成該開口121之製法的成本較高，並需以清洗製程去除殘渣才可接著形成導電盲孔，遂而導致製程增加，而使製造成本隨之提高，再者，由於清洗製程後使該開口121側壁凹凸不平，而於外接導電元件時容易於該開口121處產生剝離(peeling)現象，導致封裝結構之可靠度降低。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種封裝結構，係包括：電子元件，係具有相對之作用面與非作用面，且該作用面具有複數電極墊；封裝膠體，係包覆該電子元件，且具有外露該作用面的第一表面及相對該第一表 面之第二表面；複數導電元件，係貫穿該封裝膠體之第一表面與第二表面，該導電元件係為金屬球；以及線路重佈層，係形成於該第一表面與作用面上，且電性連接於該些電極墊與導電元件。
本發明復提供一種封裝結構之製法，係包括：於該第一承載板之一表面上依序形成金屬層與具有複數開孔的介電層，該開孔係外露該金屬層，並將具有相對之作用面與非作用面之電子元件以該作用面接置於該介電層上，且該作用面具有複數電極墊，並於該介電層的開孔中的金屬層上接置複數導電元件，該導電元件係為金屬球；於該介電層上形成封裝膠體，以包覆該電子元件與導電元件，該封裝膠體具有外露該作用面的第一表面及相對該第一表面之第二表面；移除該第一承載板；以及將該金屬層圖案化為第一線路，並於該介電層上形成第二線路，該第二線路電性連接於該些電極墊與第一線路。
由上可知，藉由先接置複數導電元件、再形成封裝膠體，並外露該導電元件於封裝膠體之相對兩表面，而不需以雷射製程逐一形成複數封裝膠體開口及無需於該封裝膠體開口中形成導電元件，且無需進行雷射後之開口清洗製程，並無需具備雷射設備，故本發明之製法能減少製程步驟，且縮短製程時間，並降低製造成本。再者，還能避免因雷射所形成之側壁凹凸不平的該開口而產生導電元件剝離(peeling)之問題，進而提升封裝結構之可靠度及良率。
10‧‧‧承載件
101‧‧‧電性接觸墊
102,270‧‧‧導電盲孔
11‧‧‧電子元件
12,25‧‧‧封裝膠體
121,281‧‧‧開口
110,2401‧‧‧電極墊
2,3‧‧‧封裝結構
2’‧‧‧封裝件
20‧‧‧第一承載板
20’‧‧‧黏著層
21‧‧‧金屬層
22‧‧‧介電層
221‧‧‧開孔
220‧‧‧孔隙
222‧‧‧盲孔
23‧‧‧第一導電元件
24‧‧‧電子元件
240‧‧‧作用面
241‧‧‧非作用面
25a‧‧‧第一表面
25b‧‧‧第二表面
26‧‧‧第二承載板
260‧‧‧離形層
21a‧‧‧第一線路
27‧‧‧第二線路
28‧‧‧絕緣保護層
29‧‧‧第二導電元件
4‧‧‧線路重佈層
第1A至1B圖係為習知用於堆疊式封裝結構之封裝結構之製法的剖視示意圖；第2A至2J圖係為本發明之封裝結構之製法之剖視示意圖，其中，第2C’圖係第2C圖之另一實施態樣，第2F’圖係第2F圖之另一實施態樣，第2I’圖係第2I圖之另一實施態樣；以及第3圖係為本發明之堆疊式封裝結構之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。又，本說明書中所記載之“上”係可包含該物件上或其上方之意。
第2A至2J圖係為本發明之封裝結構2之製法之剖視 示意圖，其中，第2C’圖係第2C圖之另一實施態樣，第2F’圖係第2F圖之另一實施態樣，第2I’圖係第2I圖之另一實施態樣。
如第2A圖所示，提供一第一承載板20，並於該第一承載板20之一表面上形成金屬層21，該第一承載板20之表面可視需要具有用以連接該金屬層21的黏著層20’，形成該黏著層20’之材質可為耐熱膠。
於本實施例中，形成該金屬層21之材質係為銅。
如第2B圖所示，以圖案化製程形成具有複數供該金屬層21外露的開孔221之介電層22。
如第2C圖所示，於該開孔221中的金屬層21上設置複數第一導電元件23，使該些第一導電元件23電性連接於該金屬層21，舉例而言，該第一導電元件23係為事先預製好之金屬球(例如銲球)，且加熱該第一導電元件23以接合至該金屬層21之表面，該第一導電元件23與開孔221之間係存在有孔隙220，或者，該第一導電元件23係填滿該開孔221，如第2C’圖所示。
如第2D圖所示，設置電子元件24於該介電層22上。
於本實施例中，該電子元件24係為主動元件、被動元件或其組合者，且該主動元件係例如晶片，而該被動元件係例如電阻、電容及電感。
再者，該電子元件24具有相對之作用面240與非作用面241，該作用面240具有複數電極墊2401，其中，該電子元件24以該作用面240設置於該介電層22上。
如第2E圖所示，於該介電層22上形成封裝膠體25，以包覆該些第一導電元件23及該電子元件24，該封裝膠體25具有外露該作用面240的第一表面25a及相對該第一表面25a之第二表面25b。
於本實施例中，形成該封裝膠體25係以模封(molding)方式製作，但形成方式可依需求選擇不同方式，並不限於上述。
再者，形成該封裝膠體25之材質可為乾膜型(Dry Film Type)環氧樹脂(Epoxy)、流體狀環氧樹脂、或有機材質，如ABF(Ajinomoto Build-up Film)樹脂，但不限於上述。
如第2F圖所示，從該第二表面25b側以研磨製程移除部分厚度之該封裝膠體25，以令該些第一導電元件23與該電子元件24之非作用面241外露於該封裝膠體25之第二表面25b，且該非作用面241係可與該封裝膠體25之第二表面25b齊平。
於另一實施例中，如第2F’圖所示，於移除部分厚度之該封裝膠體25之後，該電子元件24之非作用面241未外露於該封裝膠體25之第二表面25b。
如第2G圖所示，延續自第2F圖，設置具有離形層260之第二承載板26於該封裝膠體25之第二表面25b上，並移除該第一承載板20，以外露該金屬層21。
如第2H圖所示，圖案化該金屬層21以形成第一線路21a，並圖案化該介電層22以形成供該電子元件24之該些電極墊2401外露之盲孔222。
如第2I圖所示，於該盲孔222中形成導電盲孔270，於該介電層22上形成電性連接該導電盲孔270的第二線路27，該導電盲孔270、第二線路27、介電層22與第一線路21a係構成一線路重佈層4，該第一線路21a與第二線路27係構成一線路層(未標元件符號)，並以圖案化製程形成具有供部分該第一線路21a與第二線路27外露的開口281之絕緣保護層28，接著，形成複數例如含有銲錫材料之焊線、錫球或凸塊之第二導電元件29於該開口281，以電性連接於該些第二線路27與第一線路21a，該第二線路27復延伸並疊置於該第一線路21a上，或者，該第二線路27係以其側表面電性連接該第一線路21a，如第2I’圖所示。
如第2J圖所示，移除該第二承載板26，並進行切單製程以完成封裝結構2。
於本實施例中，本發明之封裝結構2復可接置另一封裝件2’，以完成如第3圖所示之堆疊式封裝結構(POP)3。
本發明復提供一種封裝結構，係包括：電子元件24，係具有相對之作用面240與非作用面241，且該作用面240具有複數電極墊2401；封裝膠體25，係包覆該電子元件24，且具有外露該作用面240的第一表面25a及相對該第一表面25a之第二表面25b；複數第一導電元件23，係貫穿該封裝膠體25之第一表面25a與第二表面25b，該些第一導電元件23係為金屬球；以及線路重佈層4，係形成於該第一表面25a與作用面240上，且電性連接於該些電極墊2401與該些第一導電元件23。
於前述之封裝結構中，該金屬球係為銲球，且該第一表面25a係與該電子元件24之作用面240齊平。
於本實施例之封裝結構中，該線路重佈層4係包括介電層22、第一線路21a與第二線路27，該介電層22係形成於該第一表面25a與作用面240上，該些第一導電元件23復貫穿該介電層22，該第一線路21a與第二線路27係形成於該介電層22上，該第一線路21a連接該些第一導電元件23，且該第二線路27電性連接該些電極墊2401與第一線路21a，該介電層22具有容設該些第一導電元件23的開孔221，該開孔221與該些第一導電元件23之間存在有孔隙220，且該第二線路27復延伸並疊置於該第一線路21a上。
於所述之封裝結構中，該電子元件24之非作用面241係齊平於該封裝膠體25之第二表面25b，復包括封裝件2’，係接置於該封裝膠體25之第二表面25b上方，且電性連接該些第一導電元件23。
綜上所述，本發明之封裝結構及其製法主要係先接置複數導電元件、再形成封裝膠體，並外露該導電元件於封裝膠體之相對兩表面，藉此，不需以雷射製程逐一形成複數封裝膠體開口及無需於該封裝膠體開口中形成導電元件，且無需進行雷射後之開口清洗製程，並無需具備雷射設備，故本發明之製法能減少製程步驟，且縮短製程時間，並降低製造成本。再者，本發明還能避免因雷射所形成之側壁凹凸不平的該開口而產生導電元件剝離(peeling)之 問題，進而提升封裝結構之可靠度及良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
21a‧‧‧第一線路
22‧‧‧介電層
220‧‧‧孔隙
23‧‧‧第一導電元件
24‧‧‧電子元件
2401‧‧‧電極墊
25‧‧‧封裝膠體
25a‧‧‧第一表面
25b‧‧‧第二表面
27‧‧‧第二線路
270‧‧‧導電盲孔
28‧‧‧絕緣保護層
29‧‧‧第二導電元件
4‧‧‧線路重佈層

Claims (16)

  1. 一種封裝結構，係包括：電子元件，係具有相對之作用面與非作用面，且該作用面具有複數電極墊；封裝膠體，係包覆該電子元件，且具有外露該作用面的第一表面及相對該第一表面之第二表面；複數導電元件，係貫穿該封裝膠體之第一表面與第二表面，該導電元件係為金屬球；以及線路重佈層，係形成於該第一表面與作用面上，且電性連接於該些電極墊及/或導電元件。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該金屬球係為銲球。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該第一表面係與該電子元件之作用面齊平。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該線路重佈層係包括介電層、第一線路與第二線路，該介電層係形成於該第一表面與作用面上，該導電元件復貫穿該介電層，該第一線路與第二線路係形成於該介電層上，該第一線路連接該導電元件，且該第二線路電性連接該些電極墊與第一線路。
  5. 如申請專利範圍第4項所述之封裝結構，其中，該介電層具有容設該導電元件的開孔，該開孔與導電元件之間存在有孔隙。
  6. 如申請專利範圍第4項所述之封裝結構，其中，該第 二線路復延伸並疊置於該第一線路上。
  7. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件之非作用面係齊平於該封裝膠體之第二表面。
  8. 如申請專利範圍第1項所述之封裝結構，復包括封裝件，係接置於該封裝膠體之第二表面上方，且電性連接該導電元件。
  9. 一種封裝結構之製法，係包括：於該第一承載板之一表面上依序形成金屬層與具有複數開孔的介電層，該開孔係外露該金屬層，並將具有相對之作用面與非作用面之電子元件以該作用面接置於該介電層上，且該作用面具有複數電極墊，並於該介電層的開孔中的金屬層上接置複數導電元件，該導電元件係為金屬球；於該介電層上形成封裝膠體，以包覆該電子元件與導電元件，該封裝膠體具有外露該作用面的第一表面及相對該第一表面之第二表面；移除該第一承載板；以及將該金屬層圖案化為第一線路，並於該介電層上形成第二線路，該第二線路電性連接於該些電極墊及/或第一線路。
  10. 如申請專利範圍第9項所述之封裝結構之製法，其中，該介電層具有容設該導電元件的開孔，該開孔與導電元件之間存在有孔隙。
  11. 如申請專利範圍第9項所述之封裝結構之製法，其中， 該第二線路復延伸並疊置於該第一線路上。
  12. 如申請專利範圍第9項所述之封裝結構之製法，其中，該金屬球係為銲球。
  13. 如申請專利範圍第9項所述之封裝結構之製法，於移除該第一承載板之前，復包括從該第二表面側研磨移除部分厚度之該封裝膠體，以令該導電元件外露於該封裝膠體之第二表面。
  14. 如申請專利範圍第9項所述之封裝結構之製法，於移除該第一承載板之前，復包括設置第二承載板於該封裝膠體之第二表面上，並於形成該第一線路與第二線路之後，移除該第二承載板。
  15. 如申請專利範圍第9項所述之封裝結構之製法，於形成該第一線路與第二線路之後，復包括進行切單製程。
  16. 如申請專利範圍第9項所述之封裝結構之製法，於形成該第一線路與第二線路之後，復包括於該封裝膠體之第二表面上方接置封裝件，且該封裝件係電性連接該導電元件。
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