CN104051369A - 一种用于2.5d封装的中间互联层及其制备方法 - Google Patents

一种用于2.5d封装的中间互联层及其制备方法 Download PDF

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CN104051369A
CN104051369A CN201410311847.1A CN201410311847A CN104051369A CN 104051369 A CN104051369 A CN 104051369A CN 201410311847 A CN201410311847 A CN 201410311847A CN 104051369 A CN104051369 A CN 104051369A
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epoxy resin
interconnection layer
substrate
middle interconnection
resin layer
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杨凡力
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Shanghai Zhen Xin Microelectronics Science And Technology Ltd
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Shanghai Zhen Xin Microelectronics Science And Technology Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本发明公开的一种用于2.5D封装的中间互联层，包括基体，基体采用环氧树脂制成，在基体内设置有若干露出基体的铜柱或锡球，其制备方法包括如下步骤：(1)采用硅片或金属框架制成一衬底；(2)在衬底的指定区域内形成若干铜柱或锡球；(3)在衬底形成有铜柱或锡球这一面上采用涂覆或热压方法制备一层环氧树脂层，环氧树脂层淹没掉所述铜柱或锡球；(4)研磨环氧树脂层直至露出铜柱或锡球；(5)在环氧树脂层的研磨面上布线；(6)去掉衬底制成的中间互联层或者将需要倒装焊的管芯焊接在中间互联层的一个面上再去掉衬底。本发明与现有技术相比，采用环氧树脂等有机材料作为中间互联层，不需要TSV等复杂的工艺，加工工艺非常简单。

Description

一种用于2.5D封装的中间互联层及其制备方法
技术领域
本发明涉及半导体器件封装技术领域，特别涉及一种用于2.5D封装的中间互联层及其制备方法。
背景技术
目前用于2.5D封装的中间互联层主要有两类技术，一类技术是采用PCB衬底作为中间互联层，另一类技术是采用硅片作为中间互联层。采用PCB衬底作为中间互联层的工艺成熟，但其存在以下两种缺点：一种缺点是PCB的厚度很厚，与现代电器小型化和薄层化不相吻合；第二种缺点是PCB和环氧树脂之间存在分层的风险，易出现可靠性问题。采用硅片作为中间互联层的技术需要采用粘片、剥离、TSV钻孔和CVD/PVD/铜电镀技术，工艺复杂。
发明内容
本发明的目的之一是针对现有技术所存在的上述诸多问题而提供一种用于2.5D封装的中间互联层，该中间互联层采用环氧树脂作为中间互联层，工艺简单。
本发明的目的之二在于提供上述用于2.5D封装的中间互联层的加工工艺。
为了实现上述发明目的，本发明所采用的技术方案如下：
一种用于2.5D封装的中间互联层，包括基体，所述基体采用环氧树脂制成，在所述基体内设置有若干露出所述基体上、下表面的铜柱或锡球。
上述用于2.5D封装的中间互联层的制备方法，包括如下步骤：
(1)采用硅片或金属框架制成一衬底；
(2)在所述衬底的指定区域内用电镀的方法形成若干铜柱或采用植球的方法制作锡球；
(3)在所述衬底形成有铜柱这一面上采用涂覆或热压方法制备一层环氧树脂层，所述环氧树脂层淹没掉所述铜柱或锡球；
(4)研磨所述环氧树脂层直至露出铜柱或锡球；
(5)在环氧树脂层的研磨面上布线；
(6)去掉所述衬底制成所述的中间互联层或者将需要倒装焊的管芯焊接在中间互联层的一个面上再去掉衬底。
封装时，将需要倒装焊的管芯焊接在中间互联层的一个面上，管芯焊接好以后也可以采用环氧树脂进行封装，在中间互联层的另一个面上植球即可。
由于采用了如上的技术方案，本发明与现有技术相比，采用环氧树脂等有机材料作为中间互联层，不需要TSV等复杂的工艺，加工工艺非常简单。
附图说明
图1为本发明在衬底的指定区域内用电镀的方法形成若干铜柱的示意图。
图2为本发明在衬底形成有铜柱这一面上采用涂覆或热压方法制备一层环氧树脂层并研磨环氧树脂层直至露出铜柱的示意图。
图3为本发明在环氧树脂研磨面上布线的示意图。
图4为本发明将需要倒装焊的管芯焊接在中间互联层的一个面上的示意图。
图5为本发明去掉衬底后在中间互联层的另一个面上植球的示意图。
图6为本发明在管芯上封装环氧树脂的示意图。
具体实施方式
参见附图，图中给出的用于2.5D封装的中间互联层的制备方法，包括如下步骤：
(1)采用硅片或金属框架制成一衬底10；
(2)参见图1，在衬底10的指定区域内用电镀的方法形成若干铜柱20；
(3)参见图2在衬底10形成有铜柱20这一面11上采用涂覆或热压方法制备一层环氧树脂层30，环氧树脂层30淹没掉铜柱20；
(4)参见图2，研磨环氧树脂层30直至露出铜柱20；
(5)参见图3，在环氧树脂层30的研磨面31上布线40；
(6)参见图4，将需要倒装焊的管芯50焊接在环氧树脂层30的研磨面31上的布线40上；
(7)参见图5，去掉衬底10并在环氧树脂层30另一个面32上植锡球60即可。
当然，参见图6，也可以在管芯50上封装环氧树脂70。

Claims (2)

1.一种用于2.5D封装的中间互联层，包括基体，所述基体采用环氧树脂制成，在所述基体内设置有若干露出所述基体上、下表面的铜柱或锡球。
2.权利要求1所述的用于2.5D封装的中间互联层的制备方法，其特征在于，包括如下步骤：
(1)采用硅片或金属框架制成一衬底；
(2)在所述衬底的指定区域内用电镀的方法形成若干铜柱或用植球的方法制造锡球；
(3)在所述衬底形成有铜柱这一面上采用涂覆或热压方法制备一层环氧树脂层，所述环氧树脂层淹没掉所述铜柱或锡球；
(4)研磨所述环氧树脂层直至露出铜柱或锡球；
(5)在环氧树脂层的研磨面上布线；
(6)去掉所述衬底制成所述的中间互联层或者将需要倒装焊的管芯焊接在中间互联层的一个面上再去掉衬底。
CN201410311847.1A 2014-07-02 2014-07-02 一种用于2.5d封装的中间互联层及其制备方法 Pending CN104051369A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320695A (zh) * 2007-06-04 2008-12-10 新光电气工业株式会社 带穿通电极的基板的制造方法
US20100264526A1 (en) * 2006-12-14 2010-10-21 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
CN102254897A (zh) * 2010-05-18 2011-11-23 台湾积体电路制造股份有限公司 具有中介层的封装系统

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100264526A1 (en) * 2006-12-14 2010-10-21 Advanpack Solutions Pte Ltd. Semiconductor package and manufacturing method thereof
CN101320695A (zh) * 2007-06-04 2008-12-10 新光电气工业株式会社 带穿通电极的基板的制造方法
CN102254897A (zh) * 2010-05-18 2011-11-23 台湾积体电路制造股份有限公司 具有中介层的封装系统

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