CN111261530B - 封装件及其形成方法 - Google Patents
封装件及其形成方法 Download PDFInfo
- Publication number
- CN111261530B CN111261530B CN201911203961.1A CN201911203961A CN111261530B CN 111261530 B CN111261530 B CN 111261530B CN 201911203961 A CN201911203961 A CN 201911203961A CN 111261530 B CN111261530 B CN 111261530B
- Authority
- CN
- China
- Prior art keywords
- interconnect structure
- redistribution
- forming
- redistribution structure
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19011—Structure including integrated passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Abstract
形成封装件的方法包括在载体上形成再分布结构,将集成无源器件附接至再分布结构的第一侧上,将互连结构附接至再分布结构的第一侧,集成无源器件介于再分布结构和互连结构之间,在互连结构和再分布结构之间沉积底部填充材料,以及将半导体器件附接至与再分布结构的第一侧相对的再分布结构的第二侧。本发明的实施例还涉及封装件。
Description
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
半导体工业通过不断减小最小部件尺寸来不断提高各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这使得更多的组件,因此更多的功能可以集成至给定的区域中。具有高功能的集成电路需要许多输入/输出焊盘。然而,对于小型化非常重要的应用,可能需要小的封装件。
集成扇出(InFO)封装技术正变得越来越流行,尤其是与晶圆级封装(WLP)技术接合使用时,其中将集成电路封装在通常包含再分布层(RDL)或后钝化互连的封装件中,该后钝化互连通常用于封装件的接触焊盘的扇出布线,使得可以以比集成电路的接触焊盘更大的间距制成电接触件。这样得到的封装结构提供了具有相对低成本和高性能封装件的高功能密度。
发明内容
本发明的一些实施例提供了一种形成封装件的方法,包括:在载体上形成再分布结构;将集成无源器件附接至所述再分布结构的第一侧上;将互连结构附接至所述再分布结构的第一侧,所述集成无源器件介于所述再分布结构和所述互连结构之间;在所述互连结构和所述再分布结构之间沉积底部填充材料;将半导体器件附接至与所述再分布结构的第一侧相对的所述再分布结构的第二侧上。
本发明的另一实施例提供了一种形成封装件的方法,包括:在载体衬底上形成第一接触焊盘;在所述第一接触焊盘上形成再分布结构;在所述再分布结构上形成第二接触焊盘;将集成无源器件电连接至所述第二接触焊盘的第一组;使用导电连接件将互连结构电连接至所述第二接触焊盘的第二组;以及将半导体管芯电连接至所述第一接触焊盘。
本发明的又一实施例涉及一种封装件,包括:互连结构;再分布结构,电连接至所述互连结构;至少一个集成器件,位于所述再分布结构和所述互连结构之间的间隙中,所述至少一个集成器件电连接至所述互连结构;底部填充材料,位于所述再分布结构和所述互连结构之间的间隙中,所述底部填充材料从所述再分布结构延伸至所述互连结构并且至少横向地围绕所述至少一个集成器件;以及至少一个半导体器件,位于所述再分布结构的与所述集成器件相对的侧上,所述至少一个半导体器件电连接至所述再分布结构。
附图说明
当接合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图4示出了根据一些实施例的形成器件结构的中间步骤的截面图。
图5A至图5C示出了根据一些实施例的形成互连结构的中间步骤的截面图。
图6至图11示出了根据一些实施例的形成封装件的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
在本发明中,描述了器件封装件的各个方面及其形成。器件封装件可以是例如系统级封装件。在一些实施例中,可在载体衬底上方形成再分布结构,以及然后将集成无源器件附接至该再分布结构。再分布结构可以是例如扇出结构。互连结构形成在芯衬底上,并且然后通过设置在互连结构和再分布结构之间的集成无源器件附接至再分布结构。然后将半导体器件附接至再分布结构。通过将集成无源器件放置在再分布结构和互连结构之间,可以减小半导体器件和集成无源器件之间的距离,并且可以改善封装件的电性能。
图1至图11示出了根据一些实施例的形成封装件600(见图11)的中间步骤的截面图。图1至图4示出了根据一些实施例的形成器件结构200(见图4)的中间步骤的截面图。图5A至图5C示出了根据一些实施例的形成互连结构300的中间步骤的截面图。图6至图11示出了根据一些实施例的形成封装件600的中间步骤的截面图。
现在参考图1,示出了根据一些实施例的其上已经形成接触焊盘104的载体衬底102。载体衬底102可以包括例如硅基材料,诸如硅衬底(例如硅晶圆)、玻璃材料、氧化硅、或诸如氧化铝等的其它材料或它们的组合。在一些实施例中,载体衬底102可以是面板结构,其可以是例如由诸如玻璃材料或有机材料的合适的介电材料形成的支撑衬底,并且可以具有矩形形状。载体衬底102可以是平面的,以适应附加部件的形成,诸如接触焊盘104。
在一些实施例中,可以在载体衬底102的顶面上形成释放层(未示出),以促进载体衬底102的后续剥离。释放层可以由基于聚合物的材料形成,其可以与载体衬底102一起从将在后续步骤中形成的上面的结构中去除。在一些实施例中,释放层是基于环氧的热释放材料,其在加热时失去粘合性,诸如光热转换(LTHC)释放涂层。在其它实施例中,释放层可以是紫外线(UV)胶,当暴露于紫外线时其失去粘合性。释放层可以以液体的形式分布并且固化,可以是层压在载体衬底102上的层压膜等。释放层的顶面可以是水平的并且可以具有高度的共平面度。
在实施例中,可以首先通过使用诸如PVD、CVD、溅射等合适的形成工艺形成钛、铜或钛-铜合金的一层或多层的晶种层(未示出)来形成接触焊盘104。晶种层形成在载体衬底102或释放层(如果存在)上方。然后可以形成光刻胶(也未示出)以覆盖晶种层,并且然后图案化晶种层以暴露晶种层中的位于随后将形成接触焊盘104的那些部分。一旦已经形成并且图案化光刻胶,则可以在晶种层上形成导电材料。导电材料可以是诸如铜、钛、钨、铝、其它金属等或它们的组合的材料。可以通过诸如电镀或化学镀等的沉积工艺来形成导电材料。然而,虽然所讨论的材料和方法适合于形成导电材料,但是这些仅是实例。可以可选地使用任何其它合适的材料或任何其它合适的形成工艺(诸如CVD或PVD)来形成接触焊盘104。一旦形成导电材料,则可以通过诸如灰化或化学剥离的合适的去除工艺去除光刻胶。此外,在去除光刻胶之后,可以通过例如合适的湿蚀刻工艺或干蚀刻工艺去除晶种层的由光刻胶覆盖的那些部分,其可以使用导电材料作为蚀刻掩模。晶种层的剩余部分和导电材料形成接触焊盘104。
转至图2,根据一些实施例,在接触焊盘104和载体衬底102上方形成再分布结构210。所示的再分布结构210包括绝缘层208A-208G(为清楚起见,仅标记了绝缘层208A和208G),并且包括再分布层209A-209G(为清楚起见,仅标记了再分布层209A和209G)。在其它实施例中,与本文描述的相比,可以在再分布结构210中形成不同数量的绝缘层或再分布层。在一些实施例中,可以以与本文描述的工艺不同的工艺来形成再分布结构210。在一些实施例中,再分布结构210可以是例如扇出结构。在一些实施例中,再分布结构210可以具有在约20μm和约1000μm之间的厚度。
仍参考图2,绝缘层208A形成在接触焊盘104和载体衬底102上方。绝缘层208A可以由一种或多种合适的介电材料制成,诸如氧化物(例如,氧化硅)、氮化物(例如,氮化硅)、聚合物材料(例如,光敏聚合物材料)、聚酰亚胺材料、低k介电材料、其它介电材料等或它们的组合。绝缘层208A可以通过诸如旋涂、层压、CVD等或它们的组合的工艺来形成。绝缘层208A可以具有在约2μm和约50μm之间的厚度,诸如约15μm,但是可以使用任何合适的厚度。可以使用合适的光刻掩模和蚀刻工艺来形成至绝缘层208A中的开口。例如,可以在绝缘层208A上方形成光刻胶并且图案化光刻胶,并且利用一个或多个蚀刻工艺(例如,湿蚀刻工艺或干蚀刻工艺)来去除绝缘层208A的部分。在一些实施例中,绝缘层208A由诸如PBO、聚酰亚胺、BCB等的光敏聚合物形成,其中可以使用光刻掩模和蚀刻工艺直接图案化开口。绝缘层208A中的开口可以暴露接触焊盘104。
然后可以形成再分布层209A,以在再分布结构210内提供附加的布线以及电连接。在实施例中,可以使用类似于接触焊盘104的材料和工艺来形成再分布层209A。例如,可以形成晶种层,以用于再分布层209A的期望图案将光刻胶放置在晶种层的顶部上并且图案化光刻胶。然后可以使用例如镀工艺在光刻胶的图案化开口中形成导电材料(例如,铜、钛等)。然后可以去除光刻胶并且蚀刻晶种层,从而形成再分布层209A。以这种方式,再分布层209A可以形成至接触焊盘104的电连接。
然后,可以在再分布层209A和绝缘层208A上方形成附加的绝缘层208B-208G和再分布层209B-209G,以在再分布结构210内提供附加的布线以及电连接。绝缘层208B-208G和再分布层209B-209G可以形成为交替的层,并且可以使用与用于绝缘层208A或再分布层209A的那些类似的工艺和材料来形成。例如,可以在再分布层(例如,再分布层209A)上方形成绝缘层(例如,绝缘层208B),并且然后使用合适的光刻掩模和蚀刻工艺穿过绝缘层形成开口以暴露下面的再分布层的部分。可以在绝缘层上方形成晶种层,并且可以在晶种层的部分上形成导电材料,从而形成上面的再分布层(例如,再分布层209B)。可以重复这些步骤,以形成具有合适数量和配置的绝缘层和再分布层的再分布结构210。可选地,绝缘层208B-208G或再分布层209B-209G可以与绝缘层208A或再分布层209A不同地形成。绝缘层208B-208G可以形成为每个具有在约2μm和约50μm之间的厚度,诸如约15μm。以这种方式,可以形成电连接至接触焊盘104的再分布结构210。在一些实施例中,再分布结构210是扇出结构。在其它实施例中,第二再分布结构210可以以与本文所述不同的工艺形成。
转至图3,外部连接件212形成在再分布结构210上。在一些实施例中,凸块下金属结构(UBM,未示出)首先形成在再分布结构210的最顶部再分布层(例如,图2中的再分布层209G)的部分上。UBM可以例如包括三个导电材料层,诸如钛层、铜层和镍层。然而,可以使用适合于形成UBM的其它材料和层的布置,诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM的任何合适的材料或材料层都完全包括在本申请的范围之内。可以通过在再分布结构210上方形成UBM的每一层来创建UBM。可以使用诸如电镀或化学镀的镀工艺来实施每层的形成,但是根据所需材料可以可选地使用其它形成工艺,诸如溅射、蒸发或PECVD工艺。一旦形成了所需的层,就可以通过合适的光刻掩模和蚀刻工艺来去除层的部分,以去除不需要的材料并且使UBM保持所需的形状,诸如圆形、八边形、正方形或矩形,但是可以可选地形成任何期望的形状。在一些实施例中,作为再分布结构210的形成的部分,在最顶部再分布层上方形成UBM,其可以包括使用与形成最顶部再分布层相同的光刻步骤。例如,UBM的层可被沉积在最顶部再分布层上方,以及然后在同一工艺中去除最顶部再分布层和UBM的过量材料。
仍参考图3,外部连接件212形成在第二再分布结构210上方。则外部连接件212可以形成在UBM(如果存在)上方。外部连接件212可以是例如接触凸块或焊球,但是可以使用任何合适类型的连接件。在外部连接件212是接触凸块的实施例中,外部连接件212可以包括诸如锡的材料,或者诸如银、无铅锡或铜的其它合适的材料。在外部连接件212是锡焊料凸块的实施例中,外部连接件212可以最初通过使用诸如蒸发、电镀、印刷、焊料转移、球放置等技术形成锡层来形成。一旦在结构上形成锡层,则可以实施回流以将材料成形为外部连接件212所需的凸块形状。在一些实施例中,外部连接件212的厚度可以在约2μm和约500μm之间。在一些实施例中,外部连接件212的间距可以在约25μm和约1250μm之间。
仍参考图3,在形成外部连接件212之后,再分布结构210的最顶部再分布层的一些接触区域213保持没有外部连接件212。接触区域213是集成器件215(见图4)连接的区域。因此,接触区域213可以是接触焊盘,并且在一些实施例中可以在其上形成UBM。如果存在UBM,则可以在与与外部连接件212相关的UBM相同的工艺步骤中形成UBM。
转至图4,将一个或多个集成器件215附接至接触区域213以制成与再分布结构210电连接。如图所示,可以将集成器件215放置在相邻的外部连接件212之间。图4示出了两个集成器件215的放置,但是在其它实施例中,可以使用更多或更少的集成器件215。集成器件215可以是类似的器件或者可以是不同类型的器件。在其它实施例中,可以在形成外部连接件212之前将集成器件215附接至接触区域213。例如,可以通过将诸如焊球(未示出)的集成器件215的连接件(例如,导电凸块或焊盘)顺序地浸入助焊剂中,以及然后使用拾取放置工具将集成器件215的连接件与相应的接触区域213物理对准来将集成器件215连接至接触区域213。在一些情况下,可以实施回流以将集成器件215的连接件接合至接触区域213。
集成器件215可以是例如半导体器件或包括一个或多个无源器件的其它器件,一个或多个无源器件诸如电容器、电阻器、电感器等。集成器件215可以是例如集成无源器件(IPD)。集成器件215还可以包括金属层,根据特定功能的需要,该金属层电耦合至集成器件215内的无源器件等。在一些实施例中,集成器件215可以被配置为为芯片或半导体器件(诸如为半导体器件500(见图10))提供电压或电流稳定性。在一些情况下,通过将集成器件215附接至再分布结构210,可以减小在集成器件215与半导体器件之间的布线距离,这样可以减小在集成器件215和半导体器件之间的电感和电阻。以这种方式,更短的布线距离可以改善器件的更高频率操作并且提供改善的电压或电流稳定性。在一些实施例中,集成器件215的厚度在约20μm和约500μm之间。在一些实施例中,集成器件215具有在约2mm2和约500mm2之间的横向面积。集成器件215可以具有除了这些实例之外的其它尺寸。
转至图5A至图5C,示出了根据一些实施例的形成互连结构300(见图5C)的中间步骤的截面图。互连结构300附接至器件结构200(见图6至图7),并且提供附加的电布线。互连结构300没有有源器件。在一些实施例中,互连结构300可以是例如中介层或“半成品衬底”。互连结构300还可以为附接的器件结构200提供稳定性和刚性,并且可以减少附接的器件结构200的翘曲。图5A示出了根据一些实施例的具有设置在相对表面上的导电层304的芯衬底302的截面图。在一些实施例中,芯衬底302可以包括诸如味之素积聚膜(ABF)、预浸复合纤维(预浸料)材料、环氧树脂、模塑料、环氧模塑料、玻璃纤维增强树脂材料、印刷电路板(PCB)材料、二氧化硅填料、聚合物材料、聚酰亚胺材料、纸、玻璃纤维、非织造玻璃织物、玻璃、陶瓷、其它层压板等或它们的组合的材料。在一些实施例中,芯衬底可以是双面覆铜层压板(CCL)衬底等。芯衬底302可以具有在约20μm和约2000μm之间的厚度,诸如约250μm或约500μm。导电层304可以包括层压或以其它方式形成在芯衬底302的相对侧上的铜、镍、铝、其它导电材料等或它们的组合的一层或多层。在一些实施例中,导电层304可具有在约10nm和约35000nm之间的厚度。
参考图5B,在芯衬底302中形成开口(未示出),在开口内形成通孔306(如下所述)。在一些实施例中,开口例如通过激光钻孔技术形成。在其它实施例中,也可以使用其它工艺,例如机械钻孔、蚀刻等。在一些实施例中,可以在形成开口之后实施可选的表面准备工艺。表面准备工艺可以包括用一种或多种清洁溶液清洁芯衬底302和导电层304的暴露表面的工艺。清洁溶液可以包括硫酸、铬酸、中和碱性溶液、水冲洗液等或它们的组合。在一些情况下,表面准备工艺会去除或减少残留物、油脂、天然氧化膜等。在一些实施例中,可以实施可选的去污工艺以清洁开口附近的区域。除表面准备工艺之外或代替表面准备工艺,可以实施去污工艺。例如,去污工艺可以去除芯衬底302的残留材料。可以通过机械(例如,在湿浆中用细磨料喷砂)、化学(例如,用有机溶剂,高锰酸盐等冲洗)或机械和化学去污相接合的方式完成去污工艺。在表面制备工艺或去污工艺之后,可以使用化学调节剂实施调节处理,该化学调节剂有助于随后的化学镀工艺中使用的活化剂的吸附。在一些实施例中,在调理处理之后,可以对导电层304进行微蚀刻以使导电表面粗糙化,以在导电层304与随后沉积的用于布线层308和309的导电材料之间更好地接合(如下所述)。
仍参考图5B,沉积导电材料以在芯衬底302的侧上形成布线层308,并且在芯衬底302的开口内形成通孔306。在一些实施例中,通过首先在芯衬底302上方形成图案化掩模来形成布线层308和通孔306。图案化掩模可以是例如图案化的光刻胶层。图案化掩模中的开口暴露导电层304的随后将在其上形成导电材料的部分。图案化掩模中的开口也可以暴露芯衬底302中的开口。然后可以使用例如镀工艺、化学镀工艺或其它工艺将导电材料沉积在导电层304的暴露区域上以及芯衬底302中的开口内。在一些实施例中,沉积的导电材料的厚度在约1μm和约50μm之间。在沉积导电材料之后,可以使用湿化学工艺或干工艺(例如,灰化工艺)去除图案化掩模层(例如,光刻胶)。导电层304的由图案化掩模层覆盖的部分可以用图案化掩模层或使用单独的蚀刻工艺去除。以这种方式,在芯衬底302的一侧上形成布线层308。然后可以在芯衬底302的相对侧上实施类似的工艺,以在芯衬底302的相对侧上形成布线层309(和/或通孔306的剩余部分)。以这种方式,导电材料可以在芯衬底302的相对侧上以及延伸穿过芯衬底302的通孔306上形成布线层308和309。
在一些实施例中,在沿着开口的侧壁形成导电材料之后,然后可以如图5B所示用介电材料307填充开口。介电材料307可以为导电材料提供结构支撑和保护。在一些实施例中,介电材料307可以是诸如模制材料、环氧树脂、环氧模塑料、树脂等或它们的组合的材料。可以使用例如旋涂工艺或另一工艺来形成介电材料307。在一些实施例中,导电材料可以完全填充通孔306,而省略介电材料307。
转至图5C,可以在布线层308和309上方形成介电层和附加布线层,以形成布线结构312和316。布线结构312和316形成在芯衬底302的相对侧上,并且可以在互连结构300内提供附加的电布线。布线结构312电连接至布线层308,并且包括交替的介电层310A-310C和布线层311A-311C。布线结构316电连接至布线层309,并且包括交替的介电层314A-314C和布线层315A-315C。布线结构312或316中的每个均可具有任何合适数量的介电层或布线层,包括多于或少于图5C所示的层。在一些实施例中,可以省略布线结构312或316中的一个或两个。在一些实施例中,布线结构312的层数可以与布线结构316的层数不同。
在一些实施例中,通过在布线层308和芯衬底302上方形成介电层310A来形成布线结构312。在一些实施例中,介电层310A可以是诸如积聚材料、ABF、预浸料、层压材料、与上述用于芯衬底302的材料类似的其它材料等或它们的组合的材料。介电层310A可以通过层压工艺、涂覆工艺或其它合适的工艺形成。在一些实施例中,介电层310A的厚度可以在约2μm和约50μm之间。在一些实施例中,可以在介电层310A上方形成导电层(未示出),该介电层可以用作用于形成导电材料(以下描述)的晶种层。导电层可以是例如金属箔,诸如铜箔,或其它类型的材料,诸如上述用于导电层304的材料。在介电层310A中形成开口(未示出),该开口暴露布线层308的部分以用于随后的电连接。在一些实施例中,开口例如通过激光钻孔技术形成。在其它实施例中,也可以使用其它工艺,例如机械钻孔、蚀刻等。在一些实施例中,可以在形成开口之后实施可选的表面准备工艺(例如,去污工艺等)。
然后沉积导电材料以在介电层310A上以及在介电层310A中的开口内形成布线层311A。在一些实施例中,通过首先在介电层310A上方形成图案化掩模来形成布线层311A。图案化掩模可以是例如图案化的光刻胶层。图案化掩模中的开口可以暴露介电层310A(或者,如果存在的话,位于介电层310A上的导电层)的随后将在其上形成导电材料的部分。图案化掩模中的开口也可以暴露介电层310A中的开口。然后可以使用例如镀工艺、化学镀工艺或其它工艺将导电材料沉积在介电层310A的暴露区域上以及介电层310A中的开口内。在一些实施例中,沉积的导电材料的厚度在约1μm和约50μm之间。在沉积导电材料之后,可以使用湿化学工艺或干工艺(例如,灰化工艺)去除图案化掩模层(例如,光刻胶)。以这种方式,附加的布线层311A形成在布线层308上方并且电连接至布线层308。
然后可以在布线层311A和介电层310A上方形成附加的介电层310B-310C和布线层311B-311C,以在布线结构312内提供附加的布线以及电连接。介电层310B-310C和布线层311B-311C可以形成为交替层,并且可以使用与用于介电层310A或布线层311A的工艺和材料类似的工艺和材料来形成。例如,可以在布线层(例如,布线层311A)上方形成介电层(例如,介电层310B),以及然后使用例如激光钻孔工艺在介电层上方形成开口以暴露出下面的布线层的部分。可以在介电层上方形成图案化掩模,以及然后可以形成导电材料并且去除图案化掩模,从而在介电层上方形成布线层。可以重复这些步骤以形成具有合适数量和配置的介电层和布线层的布线结构312。
在一些实施例中,介电层314A-314C和布线层315A-315C可以形成在布线层309上方以形成布线结构316。可以使用与上述布线结构312类似的工艺来形成布线结构316。例如,介电层314A-314C可以与布线层315A-315C交替形成。可以在介电层中形成开口(例如,使用激光钻孔),并且在介电层上方沉积导电材料以形成布线层。可以重复这些步骤以形成具有合适数量和配置的介电层和布线层的布线结构316。布线结构316可以通过通孔306电连接至布线结构312。
在一些实施例中,在互连结构300的布线结构312和316上方形成图案化的保护层(未示出)。保护层可以是例如阻焊剂材料,并且可以形成为保护布线结构312或316的表面。在一些实施例中,保护层可以是通过印刷、层压、旋涂等形成的光敏材料。然后可将光敏材料暴露于光学图案并且显影,从而在光敏材料中形成开口。在其它实施例中,可以通过沉积非光敏介电层(例如,氧化硅、氮化硅等或它们的组合),使用合适的光刻技术在介电层上方形成图案化的光刻胶掩模,以及然后使用合适的蚀刻工艺(例如,湿蚀刻或干蚀刻),使用图案化的光刻胶掩模蚀刻介电层来形成保护层。可以使用相同的技术在布线结构312和布线结构316上方形成保护层并且图案化保护层。也可以使用其它工艺和材料。
在一些实施例中,然后可以对布线结构312或316的最顶部布线层的暴露表面实施可选的可焊性处理。例如,如图5C所示,可以对布线层311C的暴露表面和布线层315C的暴露表面实施可焊性处理。处理可以包括化学镀镍浸钯浸金技术(ENEPIG)工艺、有机可焊性防腐(OSP)工艺等。在一些实施例中,诸如焊料凸块的外部连接件(未示出)可以形成在布线结构312或316一个或两个上。外部连接件可以例如类似于外部连接件212(见图4)或可以类似于下面关于图10描述的外部连接件406。在一些实施例中,互连结构300在与器件结构200不同的设施中制造。
图6示出了根据一些实施例的互连结构300与器件结构200电连接的放置。图6示出了在分割多个器件结构200之前,将多个不同的互连结构300接合至多个器件结构200的实施例。在实施例中,使用例如拾取和放置工艺将互连结构300放置成与外部连接件212(位于器件结构200上)物理接触。可以将互连结构300放置为使得最顶部布线层的暴露区域与对应的外部连接件212对准。例如,布线结构312的布线层311C的区域(见图5C)或布线结构316的布线层315C的区域(见图5C)可以与外部连接件212物理接触。一旦物理接触,则可以利用回流工艺将器件结构200的外部连接件212接合至互连结构300。在一些实施例中,代替或除了形成在器件结构200上的外部连接件212之外,外部连接件形成在互连结构300上。
在图6所示的实施例中,示出了分割之前的器件结构200。在其它实施例中,可以在附接互连结构300之前分割器件结构200。如图6所示,相邻的互连结构300可以被放置为使得在它们之间存在间隙D1。在一些实施例中,可以控制相邻的器件结构200的间隔,从而使得间隙D1为特定距离或在特定距离范围内。例如,间隙D1可以是在约10μm和约5000μm之间的距离。在一些情况下,可以控制间隙D1的距离,以避免在放置期间相邻的互连结构300之间的碰撞。在一些情况下,间隙D1的距离可以控制为以促进模制底部填充物402的后续沉积,如以下关于图7所述。
图7示出了根据一些实施例的附接至器件结构200的互连结构300。如图7所示,集成器件215位于互连结构300和其对应的器件结构200之间的间隙中。以这种方式,可以将集成器件215结合在结构(例如,图11的封装件600)内,而不增加结构的整体厚度。在一些实施例中,在互连结构300的底部介电层和器件结构200的顶部绝缘层之间的垂直距离在约20μm和约5000μm之间。在图7中,底部填充物402沿着互连结构300的侧壁并且在互连结构300和器件结构200之间的间隙中沉积。底部填充物402还可至少部分地围绕一些外部连接件212或一些集成器件215。在一些实施例中,底部填充物402的部分在集成器件215和互连结构300之间延伸。底部填充物402可以是诸如模塑料、环氧树脂、底部填充物、模制底部填充物(MUF)、树脂等的材料。底部填充物402可以保护外部连接件212和集成器件215,并且可以为器件结构提供结构支撑。在一些实施例中,底部填充物402可以在沉积之后固化。在一些实施例中,可在沉积之后减薄底部填充物402。可以例如使用机械研磨或CMP工艺来实施减薄。在一些实施例中,底部填充物402可以沉积在布线结构312上方,并且减薄可以暴露布线结构312的最顶部布线层(例如,布线层311C)。
图8示出了根据一些实施例载体衬底102的剥离和在器件结构200的接触焊盘104上的导电连接件404的形成。可以使用例如热工艺来改变设置在载体衬底102上的释放层的粘合特性,从而将载体衬底102从器件结构200上剥离。在特定实施例中,利用诸如紫外线(UV)激光、二氧化碳(CO2)激光或红外(IR)激光的能量源照射和加热释放层,直至释放层失去其至少一些粘合性能。一旦实施,则可以将载体衬底102和释放层物理地分离并且从器件结构200去除。在一些实施例中,该结构可以被翻转,并且互连结构300可以附接至临时衬底(未示出),诸如带、晶圆、面板、框架、环等。
在图8中,导电连接件404形成在器件结构200的接触焊盘104上方并且电连接至接触焊盘104。在一些实施例中,UBM形成在接触焊盘104上,并且导电连接件404形成在UBM上方。在一些实施例中,首先在布线结构210上方形成保护层(未示出)。可以在UBM(如果存在)上方形成保护层。保护层可以由一种或多种合适的介电材料形成,诸如聚苯并恶唑(PBO)、聚合物材料、聚酰亚胺材料、聚酰亚胺衍生物、氧化物、氮化物等或它们的组合。可以通过诸如旋涂、层压、CVD等的工艺或它们的组合来形成保护层。然后可以在保护层中形成开口以暴露接触焊盘104(其可以包括UBM,如果存在)。可以使用诸如激光钻孔或光刻掩模和蚀刻工艺的合适技术来形成保护层中的开口。然后导电连接件404形成在接触焊盘104上方,并且制成至布线结构210的电连接。
导电连接件404可以是例如接触凸块或焊球(例如,C4球),但是可以使用任何合适类型的连接件。在导电连接件404是接触凸块的实施例中,导电连接件404可以包括诸如锡的材料,或诸如银、无铅锡或铜的其它合适的材料。在导电连接件404是锡焊料凸块的实施例中,导电连接件404可以最初通过使用诸如蒸发、电镀、印刷、焊料转移、球放置等技术形成锡层来形成。一旦在结构上形成锡层,则可以实施回流以将材料成形为导电连接件404所需的凸块形状。在一些实施例中,导电连接件404可以类似于以上关于图3描述的外部连接件212。
图9示出了根据一些实施例的结构的分割以形成封装结构400。在实施例中,可以使用一个或多个锯片分割结构,将结构分割成离散的工件,从而形成一个或多个分割的封装结构400。然而,也可以采用任何合适的分割方法,包括激光烧蚀或一种或多种湿刻蚀。在分割之后,可以从临时衬底去除封装结构400。在一些实施例中,封装结构400可具有在约20mm乘20mm和约500mm乘500mm之间的横向尺寸,诸如约100mm乘100mm,但是封装结构400可以具有除这些尺寸之外的其它尺寸。在一些实施例中,封装结构400可以具有在约20μm和约5000μm之间的垂直厚度。
仍参考图9,每个封装结构400均包括器件结构200和互连结构300。在图9所示的实施例中,器件结构200具有比互连结构300更大的横向尺寸。因为器件结构200比互连结构300宽,所以如图所示,底部填充物402的部分可以在分割之后保留在互连结构300的一个或多个侧壁上。在一些实施例中,底部填充物402可具有与器件结构200的侧壁齐平的一个或多个侧壁。在一些实施例中,互连结构300的横向宽度可以在器件结构200的横向宽度的约50%和约100%之间。在一些实施例中,互连结构300的横向宽度可以在约10mm和约500mm之间。在一些实施例中,器件结构200的横向宽度可以在约20mm和约500mm之间。在其它实施例中,分割工艺从互连结构300的侧壁去除底部填充物402,从而使得互连结构300的侧壁暴露(未示出)。
如本文所述,形成包括附接至器件结构200的互连结构300的封装结构400可以实现许多优势。例如,具有较大横向尺寸的结构可能更易于翘曲或分层。如本文所述的互连结构300可以是相对刚性的,并且因此可以为器件结构200提供结构支撑,从而减少了器件结构200的翘曲。另外,保留在互连结构300的侧壁上的底部填充物402可以为互连结构300提供额外的保护和结构支撑。
图10示出了半导体器件500附接至导电连接件404,从而在半导体器件500和再分布结构210之间制成电连接。可以使用诸如拾取和放置工艺的合适工艺将半导体器件500放置在导电连接件404上。半导体器件500可以包括一个或多个器件,该器件可以包括为预期目的而设计的器件,诸如存储器管芯(例如DRAM晶圆、堆叠式存储器晶圆、高带宽存储器(HBM)管芯等)、逻辑管芯、中央处理单元(CPU)管芯、片上系统(SoC)、晶圆上组件(CoW)、集成扇出结构(InFO)、封装件等或它们的组合。在实施例中,根据特定功能的需要,半导体器件500中包括集成电路器件,诸如晶体管、电容器、电感器、电阻器、金属层、外部连接件等。在一些实施例中,半导体器件500可以包括多个相同类型的器件,或者可以包括不同的器件。图10示出了单个半导体器件500,但是在其它实施例中,可以将一个、两个或三个以上的半导体器件500附接至导电连接件404。
可以将半导体器件500放置为使得半导体器件的导电区域(例如,接触焊盘)与对应的导电连接件404对准。一旦物理接触,则可以利用回流工艺将器件结构200的导电连接件404接合至半导体器件500。在一些实施例中,代替或除了形成在器件结构200上的导电连接件404之外,在半导体器件500上形成外部连接件。在一些实施例中,导电连接件404未形成在器件结构200上,并且半导体器件500使用诸如热压接合技术的直接接合技术接合到器件结构200。如图10所示,底部填充物502可以沿着半导体器件500和器件结构200之间的间隙的侧壁沉积。底部填充物502也可以至少部分地围绕一些导电连接件404。底部填充物502可以是诸如模塑料、环氧树脂、底部填充物、模制底部填充物(MUF)、树脂等的材料,并且可以类似于前述的底部填充物402。
在图11中,外部连接件406形成在互连结构300上方并且电连接至互连结构300,从而形成封装件600。外部连接件406可以形成在布线结构312的最顶部布线层(例如,布线层311C)的暴露部分上。在一些实施例中,UBM形成在布线结构312上方,并且外部连接件406形成在UBM上方。在一些实施例中,首先在布线结构312上方形成保护层(未示出)。可以在UBM(如果存在)上方形成保护层。该保护层可以类似于先前关于图8描述的保护层,并且可以以类似的方式形成。可以在保护层中形成开口以暴露布线结构312(其可以包括UBM,如果存在)的部分。
然后,外部连接件406形成在布线结构312的暴露部分上方,并且制成至布线结构312的电连接。外部连接件406可以是例如接触凸块或焊球,但是可以使用任何合适类型的连接件。在外部连接件406是接触凸块的实施例中,外部连接件406可以包括诸如锡的材料,或诸如银、无铅锡或铜的其它合适的材料。在外部连接件406是锡焊料凸块的实施例中,外部连接件406可以最初通过使用诸如蒸发、电镀、印刷、焊料转移、球放置等技术形成锡层来形成。一旦在结构上形成锡层,则可以实施回流以将材料成形为外部连接件406所需的凸块形状。在一些实施例中,外部连接件406的厚度可以在约2μm和约1000μm之间。在一些实施例中,外部连接件406可以具有在约25μm和约1500μm之间的间距。在一些实施例中,外部连接件406可以类似于以上关于图3描述的外部连接件212。
通过形成其中在再分布结构210和互连结构300之间的间隙中设置集成器件215的封装件600,可以改善封装件600的电性能。例如,可以减小集成器件215与半导体器件500之间的距离,这可以减小布线距离,并且因此减小集成器件215和半导体器件500之间的电阻或电感。例如,通过以这种方式减小距离,还可以减小由于电阻引起的电压降。在一些情况下,在安装在再分布结构210(如图11所示)的相对侧上的半导体器件500和集成器件215之间的距离可以小于再分布结构的同一侧上的半导体器件和邻近该半导体器件安装的集成器件之间的距离。集成器件215和半导体器件500之间的距离也可以小于安装在互连结构内或互连结构的相对侧上的半导体器件和集成器件之间的距离。在一些实施例中,集成器件215和半导体器件500之间的垂直距离可以小于约10mm,诸如小于约0.3mm的距离。在一些情况下,通过将集成器件215安装在本文所述的再分布结构210和互连结构300之间,可以将在集成器件215和半导体器件500之间的等效自感减小大于约85%,诸如大于约99%。通过减小电感,可以改善封装件600的高频性能。例如,封装件的可用操作频率可以增加多达约300%。在一些情况下,可用操作频率可能会增加到约600MHz或更高的频率。另外,由于更稳定的电性能,可以改善封装件600的功率完整性。
在一些情况下,可以使用比布线结构312或316更稳健和可靠的技术来形成再分布结构210。例如,可以使用扇出工艺来形成再分布结构210(例如,在半导体制造厂中),而可以使用积聚工艺来形成布线结构312和316。通过使用更稳健的工艺,与布线结构312和316相比,再分布结构210可以具有更高的良率。在一些情况下,与用于在布线结构312和316中形成布线层的工艺相比,用于形成再分布结构210的工艺可以形成具有较小尺寸和具有较小线宽粗糙度的再分布层。因此,相对于布线结构312和316,再分布结构210可以具有改善的电性能,特别是在高频操作的情况下。
在一些情况下,通过将再分布结构210形成为器件结构200的部分,可以形成互连结构300的具有较少的层的布线结构312或316。通过在再分布结构210内形成封装件600的更多的电布线并且在布线结构312或316内形成更少的电布线,可以改善封装件400的整体电性能,如前所述。再分布结构110和210可以具有比布线结构312和316的各个层更薄的各个层,这可以减小封装件600的整体尺寸。另外,可以通过在再分布结构210内形成更多的层来降低封装件600的总制造成本。
在一些情况下,具有较高热膨胀系数(CTE)差异的封装件或器件的材料会在高温操作下引起分层、短路或其它故障。在一些情况下,再分布结构210可以包括具有比互连结构300的材料的CTE更接近半导体器件500的CTE的材料(或封装件600中的其它材料)。例如,再分布结构210的绝缘层的CTE可以小于布线结构312或316的介电层的CTE。因此,通过在器件结构200中形成更多的电布线并且在互连结构300中形成更少的电布线,可以改善封装件600的可靠性,特别是在较高温度下的操作。
在实施例中,方法包括在载体上形成再分布结构,将集成无源器件附接至再分布结构的第一侧上,将互连结构附接至再分布结构的第一侧,集成无源器件介于在再分布结构和互连结构之间,在互连结构和再分布结构之间沉积底部填充材料,以及将半导体器件附接至与再分布结构的第一侧相对的再分布结构的第二侧。在实施例中,互连结构包括芯衬底。在实施例中,底部填充材料覆盖互连结构的侧壁。在实施例中,覆盖互连结构的侧壁的底部填充材料与再分布结构的侧壁共面。在实施例中,将互连结构附接至再分布结构包括在再分布结构上形成多个焊料凸块,以及将互连结构放置在多个焊料凸块上。在实施例中,该方法还包括在附接集成无源器件和互连结构之后,对集成无源器件和互连结构实施回流工艺。在实施例中,其中集成无源器件在垂直方向上直接设置在半导体器件和互连结构之间。在实施例中,其中形成再分布结构包括在载体上方沉积聚合物层,在聚合物层中图案化开口,在聚合物层上方形成图案化掩模,并且使用图案化掩模在聚合物层上方沉积导电材料。
在实施例中,方法包括在载体衬底上形成第一接触焊盘,在第一接触焊盘上形成再分布结构,在再分布结构上形成第二接触焊盘,将集成无源器件电连接至第二接触焊盘的第一组,使用导电连接件将互连结构电连接至第二接触焊盘的第二组,以及将半导体管芯电连接至第一接触焊盘。在实施例中,集成无源器件横向地设置在两个导电连接件之间。在实施例中,集成无源器件设置在再分布结构和互连结构之间的间隙中。在实施例中,该方法还包括在将互连结构电连接至第二接触焊盘的第二组之后,在互连结构和再分布结构之间沉积模制材料。在实施例中,该方法还包括对再分布结构实施分割工艺,其中,在实施分割工艺之后,底部填充材料保留在互连结构的侧壁上。在实施例中,再分布结构具有第一横向宽度,并且互连结构具有第二横向宽度,其中第一横向宽度大于第二横向宽度。在实施例中,该方法还包括形成互连结构,其中,形成互连结构包括在芯衬底的第一侧上方形成第一多个导电迹线,在芯衬底的第二侧上方形成第二多个导电迹线,以及形成延伸穿过芯衬底的多个通孔,该通孔电连接至第一多个导电迹线和第二多个导电迹线。
在实施例中,封装件包括互连结构、电连接至互连结构的再分布结构、位于再分布结构和互连结构之间的间隙中的至少一个集成器件,至少一个集成器件电连接至互连结构,位于再分布结构和所述互连结构之间的间隙中的底部填充材料,底部填充材料从再分布结构延伸到互连结构并且至少横向地围绕至少一个集成器件,以及位于再分布结构的与集成器件相对的侧上的至少一个半导体器件,该至少一个半导体器件电连接至再分布结构。在实施例中,至少一个集成器件和至少一个半导体器件之间的距离小于0.3mm。在实施例中,互连结构包括芯衬底。在实施例中,底部填充材料沿着互连结构的侧壁延伸。在实施例中,底部填充材料在至少一个集成器件和互连结构之间延伸。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同配置并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (20)
1.一种形成封装件的方法,包括:
在载体上形成再分布结构;
将集成无源器件附接至所述再分布结构的第一侧上;
在附接所述集成无源器件之后,将互连结构附接至所述再分布结构的第一侧,所述集成无源器件介于所述再分布结构和所述互连结构之间;
在所述互连结构和所述再分布结构之间沉积底部填充材料;
将半导体器件附接至与所述再分布结构的第一侧相对的所述再分布结构的第二侧上,其中,所述集成无源器件电连接至所述互连结构,
其中,所述再分布结构的绝缘层的热膨胀系数小于所述互连结构中的布线结构的介电层的热膨胀系数。
2.根据权利要求1所述的方法,其中,所述互连结构包括芯衬底。
3.根据权利要求1所述的方法,其中,所述底部填充材料覆盖所述互连结构的侧壁。
4.根据权利要求3所述的方法,其中,覆盖所述互连结构的侧壁的所述底部填充材料与所述再分布结构的侧壁共面。
5.根据权利要求1所述的方法,其中,将所述互连结构附接至所述再分布结构包括:
在所述再分布结构上形成多个焊料凸块;以及
将所述互连结构放置在所述多个焊料凸块上。
6.根据权利要求1所述的方法,还包括:在附接所述集成无源器件和所述互连结构之后,对所述集成无源器件和所述互连结构实施回流工艺。
7.根据权利要求1所述的方法,其中,所述集成无源器件在垂直方向上直接设置在所述半导体器件和所述互连结构之间。
8.根据权利要求1所述的方法,其中,形成所述再分布结构包括:
在所述载体上方沉积聚合物层;
在所述聚合物层中图案化开口;
在所述聚合物层上方形成图案化掩模;以及
使用所述图案化掩模在所述聚合物层上方沉积导电材料。
9.一种形成封装件的方法,包括:
在载体衬底上形成第一接触焊盘;
在所述第一接触焊盘上形成再分布结构;
在所述再分布结构上形成第二接触焊盘;
将集成无源器件电连接至所述第二接触焊盘的第一组;
在电连接所述集成无源器件之后,使用导电连接件将互连结构电连接至所述第二接触焊盘的第二组;以及
将半导体管芯电连接至所述第一接触焊盘,
其中,所述集成无源器件电连接至所述互连结构,
其中,所述再分布结构的绝缘层的热膨胀系数小于所述互连结构中的布线结构的介电层的热膨胀系数。
10.根据权利要求9所述的方法,其中,所述集成无源器件横向地设置在两个导电连接件之间。
11.根据权利要求9所述的方法,其中,所述集成无源器件设置在所述再分布结构与所述互连结构之间的间隙中。
12.根据权利要求9所述的方法,还包括:在将所述互连结构电连接至所述第二接触焊盘的第二组之后,在所述互连结构和所述再分布结构之间沉积模制材料。
13.根据权利要求12所述的方法,还包括:对所述再分布结构实施分割工艺,其中,在实施所述分割工艺之后,底部填充材料保留在所述互连结构的侧壁上。
14.根据权利要求9所述的方法,其中,所述再分布结构具有第一横向宽度,并且所述互连结构具有第二横向宽度,其中,所述第一横向宽度大于所述第二横向宽度。
15.根据权利要求9所述的方法,还包括:形成所述互连结构,其中,形成所述互连结构包括:
在芯衬底的第一侧上方形成第一多个导电迹线;
在所述芯衬底的第二侧上方形成第二多个导电迹线;以及
形成延伸穿过所述芯衬底的多个通孔,所述通孔电连接至所述第一多个导电迹线和所述第二多个导电迹线。
16.一种封装件,包括:
互连结构;
再分布结构,使用焊料接头电连接至所述互连结构;
至少一个集成器件,位于所述再分布结构和所述互连结构之间的间隙中,所述至少一个集成器件电连接至所述互连结构并且使用所述焊料接头电连接至所述再分布结构;
底部填充材料,位于所述再分布结构和所述互连结构之间的间隙中,所述底部填充材料从所述再分布结构延伸至所述互连结构并且至少横向地围绕所述至少一个集成器件;以及
至少一个半导体器件,位于所述再分布结构的与所述集成器件相对的侧上,所述至少一个半导体器件电连接至所述再分布结构,
其中,所述再分布结构的绝缘层的热膨胀系数小于所述互连结构中的布线结构的介电层的热膨胀系数。
17.根据权利要求16所述的封装件,其中,所述至少一个集成器件和所述至少一个半导体器件之间的距离小于0.3mm。
18.根据权利要求16所述的封装件,其中,所述互连结构包括芯衬底。
19.根据权利要求16所述的封装件,其中,所述底部填充材料沿着所述互连结构的侧壁延伸。
20.根据权利要求16所述的封装件,其中,所述底部填充材料在所述至少一个集成器件与所述互连结构之间延伸。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862774119P | 2018-11-30 | 2018-11-30 | |
US62/774,119 | 2018-11-30 | ||
US16/458,374 US10971446B2 (en) | 2018-11-30 | 2019-07-01 | Semiconductor device and method of manufacture |
US16/458,374 | 2019-07-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111261530A CN111261530A (zh) | 2020-06-09 |
CN111261530B true CN111261530B (zh) | 2022-07-01 |
Family
ID=70849372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201911203961.1A Active CN111261530B (zh) | 2018-11-30 | 2019-11-29 | 封装件及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10971446B2 (zh) |
CN (1) | CN111261530B (zh) |
TW (1) | TWI718704B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10971446B2 (en) * | 2018-11-30 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
KR20210023021A (ko) * | 2019-08-21 | 2021-03-04 | 삼성전자주식회사 | 반도체 패키지 |
US11894318B2 (en) | 2020-05-29 | 2024-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
DE102020130962A1 (de) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und herstellungsverfahren |
US11532582B2 (en) * | 2020-08-25 | 2022-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package and method of manufacture |
KR20230067265A (ko) * | 2021-11-09 | 2023-05-16 | 삼성전기주식회사 | 인쇄회로기판 |
TWI788099B (zh) * | 2021-11-15 | 2022-12-21 | 大陸商芯愛科技(南京)有限公司 | 電子封裝件及其封裝基板 |
TWI781049B (zh) * | 2022-01-24 | 2022-10-11 | 欣興電子股份有限公司 | 電路板結構及其製作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102097301A (zh) * | 2009-11-19 | 2011-06-15 | 新科金朋有限公司 | 在聚合物基体复合衬底上形成电感器的半导体器件和方法 |
CN102254897A (zh) * | 2010-05-18 | 2011-11-23 | 台湾积体电路制造股份有限公司 | 具有中介层的封装系统 |
CN103295998A (zh) * | 2012-02-28 | 2013-09-11 | 台湾积体电路制造股份有限公司 | 具有中介框架的封装件及其形成方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080142946A1 (en) * | 2006-12-13 | 2008-06-19 | Advanced Chip Engineering Technology Inc. | Wafer level package with good cte performance |
US8455300B2 (en) * | 2010-05-25 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit package system with embedded die superstructure and method of manufacture thereof |
US8981559B2 (en) | 2012-06-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9245833B2 (en) * | 2012-08-30 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pads with openings in integrated circuits |
KR102084540B1 (ko) | 2013-10-16 | 2020-03-04 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US10177115B2 (en) | 2014-09-05 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming |
US20160086930A1 (en) | 2014-09-24 | 2016-03-24 | Freescale Semiconductor, Inc. | Fan-out wafer level package containing back-to-back embedded microelectronic components and assembly method therefor |
US9941207B2 (en) * | 2014-10-24 | 2018-04-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of fabricating 3D package with short cycle time and high yield |
US10541226B2 (en) * | 2016-07-29 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming the same |
US10763239B2 (en) | 2017-10-27 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-chip wafer level packages and methods of forming the same |
US10971446B2 (en) * | 2018-11-30 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
-
2019
- 2019-07-01 US US16/458,374 patent/US10971446B2/en active Active
- 2019-10-09 TW TW108136768A patent/TWI718704B/zh active
- 2019-11-29 CN CN201911203961.1A patent/CN111261530B/zh active Active
-
2021
- 2021-04-05 US US17/222,225 patent/US11715686B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102097301A (zh) * | 2009-11-19 | 2011-06-15 | 新科金朋有限公司 | 在聚合物基体复合衬底上形成电感器的半导体器件和方法 |
CN102254897A (zh) * | 2010-05-18 | 2011-11-23 | 台湾积体电路制造股份有限公司 | 具有中介层的封装系统 |
CN103295998A (zh) * | 2012-02-28 | 2013-09-11 | 台湾积体电路制造股份有限公司 | 具有中介框架的封装件及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US10971446B2 (en) | 2021-04-06 |
TW202025406A (zh) | 2020-07-01 |
CN111261530A (zh) | 2020-06-09 |
TWI718704B (zh) | 2021-02-11 |
US11715686B2 (en) | 2023-08-01 |
US20200176378A1 (en) | 2020-06-04 |
US20210225764A1 (en) | 2021-07-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110875196B (zh) | 制造半导体器件的方法和封装件 | |
CN111261530B (zh) | 封装件及其形成方法 | |
CN109786266B (zh) | 半导体封装件及其形成方法 | |
US20220352086A1 (en) | Dense Redistribution Layers in Semiconductor Packages and Methods of Forming the Same | |
US10037963B2 (en) | Package structure and method of forming the same | |
US10062648B2 (en) | Semiconductor package and method of forming the same | |
US20210143131A1 (en) | Device and Method for UBM/RDL Routing | |
US20180331069A1 (en) | Package Structure and Method of Forming the Same | |
KR102400764B1 (ko) | 반도체 디바이스 및 제조 방법 | |
CN113140471A (zh) | 封装件和半导体器件及其制造方法 | |
CN110364443B (zh) | 半导体器件和制造方法 | |
CN112086443A (zh) | 封装体及其形成方法 | |
US20230326850A1 (en) | Semiconductor Device and Method of Manufacture | |
CN112582365A (zh) | 半导体封装件、封装件及其形成方法 | |
US20230386986A1 (en) | Semiconductor Device and Method of Manufacture | |
TW202008481A (zh) | 形成半導體封裝體的方法 | |
US20220367211A1 (en) | Semiconductor Device and Methods of Manufacture | |
CN112687628A (zh) | 半导体器件、半导体器件的制造方法及封装件 | |
KR102379087B1 (ko) | 반도체 디바이스 및 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |