TW202025406A - 封裝體及其製造方法 - Google Patents
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- TW202025406A TW202025406A TW108136768A TW108136768A TW202025406A TW 202025406 A TW202025406 A TW 202025406A TW 108136768 A TW108136768 A TW 108136768A TW 108136768 A TW108136768 A TW 108136768A TW 202025406 A TW202025406 A TW 202025406A
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Abstract
一種封裝體的製造方法包括:在載體上形成重佈線結構;將積體被動裝置貼合至所述重佈線結構的第一側上;將內連線結構貼合至所述重佈線結構的所述第一側,所述積體被動裝置夾置在所述重佈線結構與所述內連線結構之間;在所述內連線結構與所述重佈線結構之間沈積底部填充材料;以及將半導體裝置貼合至所述重佈線結構的與所述重佈線結構的所述第一側相對的第二側上。
Description
半導體產業藉由持續降低最小特徵大小(minimum feature size)而不斷改善各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度,此使得更多組件能夠被整合於給定面積中,因此使得更多功能能夠被整合於給定面積中。具有高功能性的積體電路需要許多輸入/輸出(input/output)接墊。然而,在重視小型化的應用中,可能需要體積更小的封裝體。
積體扇出型(Integrated Fan Out,InFO)封裝技術正變得日漸普遍,特別是當與晶圓級封裝(Wafer Level Packaging,WLP)技術結合時。在晶圓級封裝技術中,積體電路被封裝於通常包括重佈線層(redistribution layer,RDL)或後鈍化內連線(post passivation interconnect)的封裝體中。所述重佈線層或後鈍化內連線用於對封裝體的接觸墊進行扇出型配線(fan-out wiring),以使可以較積體電路的接觸墊大的節距來進行電性接觸。此種所得封裝結構以相對低的成本來提供高功能密度以及提供高效能封裝體。
以下揭露提供用於實施本發明的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於……之下(beneath)」、「位於……下方(below)」、「下部的(lower)」、「位於……上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
在本揭露中,闡述了裝置封裝體及其形成方法的各種態樣。裝置封裝體可例如為系統級封裝體(system-in-package)。在一些實施例中,可在載體基板之上形成重佈線結構,且接著將積體被動裝置(integrated passive device)貼合至重佈線結構。重佈線結構可例如是扇出型結構。在核心基材(core substrate)上形成內連線結構且接著將內連線結構貼合至重佈線結構,其中積體被動裝置設置在內連線結構與重佈線結構之間。然後將半導體裝置貼合至重佈線結構。藉由將積體被動裝置定位在重佈線結構與內連線結構之間,可減小半導體裝置與積體被動裝置之間的距離且可改善封裝體的電性效能。
圖1至圖11根據一些實施例示出形成封裝體600(參見圖11)的中間步驟的剖視圖。圖1至圖4根據一些實施例示出形成裝置結構200(參見圖4)的中間步驟的剖視圖。圖5A至圖5C根據一些實施例示出形成內連線結構300的中間步驟的剖視圖。圖6至圖11根據一些實施例示出形成封裝體600的中間步驟的剖視圖。
現參照圖1,圖1根據一些實施例示出上面形成有接觸墊104的載體基板102。載體基板102可包含例如矽系材料(例如矽基板(例如,矽晶圓)、玻璃材料、氧化矽或其他材料(例如氧化鋁)、類似材料或其組合。在一些實施例中,載體基板102可為面板結構(panel structure),所述面板結構可為例如由合適的介電材料(例如玻璃材料或有機材料)形成的支撐基板,且所述面板結構可具有矩形形狀。載體基板102可為平面的,以適於附加特徵(例如,接觸墊104)的形成。
在一些實施例中,可在載體基板102的頂表面上形成離形層(未示出),以利於載體基板102的後續剝離。離形層可由聚合物系材料形成,所述離形層可與載體基板102一起自將在後續步驟中形成的上覆結構被移除。在一些實施例中,離形層為受熱時會失去其黏合性質的環氧系熱離形材料,例如光熱轉換(Light-to-Heat-Conversion,LTHC)離形塗層。在其他實施例中,離形層可為當暴露於紫外(ultra-violet,UV)光時會失去其黏合性質的紫外(UV)膠。離形層可以液體形態被分配並被固化,或可為疊層至載體基板102上的疊層膜(laminate film)等。離形層的頂表面可被整平且可具有高的共面程度。
在實施例中,可藉由以下方式形成接觸墊104:在開始時使用合適的形成製程(例如物理氣相沈積(physical vapor deposition,PVD)、化學氣相沈積(chemical vapor deposition,CVD)CVD、濺鍍(sputtering)等)形成一或多個鈦層、銅層或鈦-銅合金層的晶種層(未示出)。晶種層形成於載體基板102或離形層(若存在)之上。接著可形成光阻(亦未示出)以覆蓋晶種層且接著將所述光阻圖案化以暴露出晶種層的位於隨後將形成接觸墊104的位置的部分。一旦形成光阻並將光阻圖案化,便可在晶種層上形成導電材料。導電材料可例如是銅、鈦、鎢、鋁、其他金屬、類似材料或其組合等材料。可藉由沈積製程(例如電鍍或無電鍍覆等)形成導電材料。然而,儘管所論述的材料及方法適合形成導電材料,但該些材料與方法僅為實例。作為另外一種選擇,可使用任何其他合適的材料或任何其他合適的形成製程(例如CVD或PVD)來形成接觸墊104。一旦形成導電材料,便可藉由合適的移除製程(例如灰化(ashing)或化學剝除(chemical stripping))來移除光阻。另外,在移除光阻之後,可藉由例如合適的濕式蝕刻製程或乾式蝕刻製程來移除晶種層的先前被光阻覆蓋的部分,所述濕式蝕刻製程或乾式蝕刻製程可使用導電材料作為蝕刻遮罩。晶種層的剩餘部分及導電材料形成接觸墊104。
轉到圖2,根據一些實施例,在接觸墊104及載體基板102之上形成重佈線結構210。所示重佈線結構210包括絕緣層208A至絕緣層208G(為清晰起見,僅標記絕緣層208A及絕緣層208G)且包括重佈線層209A至重佈線層209G(為清晰起見,僅標記重佈線層209A及重佈線層209G)。在其他實施例中,可在重佈線結構210中形成與本文中所述數目不同數目的絕緣層或重佈線層。在一些實施例中,可在與本文中所述者不同的製程中形成重佈線結構210。在一些實施例中,重佈線結構210可為例如扇出型結構。在一些實施例中,重佈線結構210可具有介於約20微米與約1000微米之間的厚度。
仍參照圖2,在接觸墊104及載體基板102之上形成絕緣層208A。絕緣層208A可由例如以下一或多種合適的介電材料製成:氧化物(例如,氧化矽)、氮化物(例如,氮化矽)、聚合物材料(例如,感光性聚合物材料)、聚醯亞胺材料、低介電常數介電材料、其他介電材料、類似材料或其組合。可藉由例如旋轉塗佈、疊層(lamination)、CVD、類似製程或其組合等製程形成絕緣層208A。絕緣層208A可具有介於約2微米與約50微米之間(例如約15微米)的厚度,但可使用任何合適的厚度。可使用合適的微影遮罩及蝕刻製程而在絕緣層208A中形成開口。舉例而言,可在絕緣層208A之上形成光阻並將所述光阻圖案化,且利用一或多個蝕刻製程(例如,濕式蝕刻製程或乾式蝕刻製程)來移除絕緣層208A的一些部分。在一些實施例中,絕緣層208A由感光性聚合物(例如聚苯噁唑(polybenzoxazole,PBO)、聚醯亞胺、苯基環丁烯(benzocyclobutene,BCB)等)形成,可使用微影遮罩及蝕刻製程在絕緣層208A中直接圖案化出開口。絕緣層208A中的開口可暴露出接觸墊104。
然後,可形成重佈線層209A以在重佈線結構210內提供附加的佈線以及電性連接。在實施例中,可使用與接觸墊104類似的材料及製程來形成重佈線層209A。舉例而言,可形成晶種層,且將光阻放置在晶種層的頂部上並圖案化光阻層,而使光阻層具有所欲形成的重佈線層209A之圖案。然後可使用例如電鍍製程在光阻的圖案化開口中形成導電材料(例如,銅、鈦等)。然後可移除光阻並蝕刻晶種層,藉此形成重佈線層209A。以此種方式,重佈線層209A可與接觸墊104形成電性連接。
接著可在重佈線層209A及絕緣層208A之上形成附加的絕緣層208B至絕緣層208G及重佈線層209B至重佈線層209G,以在重佈線結構210內提供附加的佈線及電性連接。絕緣層208B至絕緣層208G及重佈線層209B至重佈線層209G可形成為交替的層,且可使用與用於絕緣層208A或重佈線層209A的製程及材料相似的製程及材料來形成。舉例而言,可在重佈線層(例如,重佈線層209A)之上形成絕緣層(例如,絕緣層208B),且接著使用合適的微影遮罩及蝕刻製程製作穿過絕緣層的開口以暴露出下伏重佈線層的一些部分。可在絕緣層之上形成晶種層且在晶種層的部分上形成導電材料,進而形成上覆重佈線層(例如,重佈線層209B)。可重複進行該些步驟以形成具有合適的數目及配置的絕緣層及重佈線層的重佈線結構210。作為另外一種選擇,可以與絕緣層208A或重佈線層209A不同的方式形成絕緣層208B至絕緣層208G或重佈線層209B至重佈線層209G。絕緣層208B至絕緣層208G可被形成為各自具有介於約2微米與約50微米之間(例如約15微米)的厚度。以此種方式,重佈線結構210可被形成為與接觸墊104電性連接。在一些實施例中,重佈線結構210是扇出型結構。在其他實施例中,可以與本文中所述製程不同的製程形成重佈線結構210。
轉到圖3,在重佈線結構210上形成外部連接件212。在一些實施例中,首先在重佈線結構210的最頂部重佈線層(例如,圖2中的重佈線層209G)的一些部分上形成凸塊下金屬結構(under-bump metallization structures,UBMs,未示出)。凸塊下金屬結構可例如包括三個導電材料層,例如鈦層、銅層及鎳層。然而,可使用適合形成凸塊下金屬結構的材料及層的其他排列方式,例如鉻/鉻銅合金/銅/金的排列方式、鈦/鈦鎢/銅的排列方式或銅/鎳/金的排列方式。任何合適的材料或材料層可用於凸塊下金屬結構且完全旨在包括於當前申請案的範圍內。可藉由在重佈線結構210之上形成凸塊下金屬結構的每一層來產生凸塊下金屬結構。可使用鍍覆製程(例如電鍍或無電鍍覆)來形成凸塊下金屬的每一層,但作為另外一種選擇,可視期望的材料而使用其他形成製程,例如濺鍍、蒸發(evaporation)或電漿增強型化學氣相沈積(plasma enhanced chemical vapor deposition,PECVD)製程來形成凸塊下金屬的每一層。一旦形成期望的層,接著便可藉由合適的微影遮蔽及蝕刻製程移除所述層的一些部分,以移除不期望的材料並使凸塊下金屬結構具有期望的形狀,例如圓形、八邊形、正方形或矩形形狀,但作為另外一種選擇,可形成任何期望的形狀。在一些實施例中,在最頂部重佈線層上的凸塊下金屬結構之形成作為重佈線結構210之形成的一部分,形成凸塊下金屬結構可包括使用用於形成最頂部重佈線層的相同的微影步驟。舉例而言,可在最頂部重佈線層之上沈積凸塊下金屬結構的層,且接著以同一製程移除最頂部重佈線層及凸塊下金屬結構的多餘的材料。
仍參照圖3,在重佈線結構210之上形成外部連接件212。若存在凸塊下金屬結構,則可在凸塊下金屬結構之上形成外部連接件212。外部連接件212可例如為接觸凸塊(contact bump)或焊料球(solder ball),然而可利用任何合適的類型的連接件。在其中外部連接件212是接觸凸塊的實施例中,外部連接件212可包含例如錫等材料或例如銀、無鉛錫或銅等其他合適的材料。在其中外部連接件212是錫焊料凸塊的實施例中,可藉由以下方式形成外部連接件212:在開始時使用例如蒸發、電鍍、印刷、焊料轉移、植球(ball placement)等技術形成錫層。一旦在所述結構上形成錫層,便可執行回焊(reflow)以將所述材料塑形成外部連接件212期望的凸塊形狀。在一些實施例中,外部連接件212可具有介於約2微米與約500微米之間的厚度。在一些實施例中,外部連接件212可具有介於約25微米與約1250微米之間的節距。
仍參照圖3,在形成外部連接件212之後,重佈線結構210的最頂部重佈線層的一些接觸區域213保持不具有外部連接件212。接觸區域213是連接積體裝置215(參見圖4)的區域。因此,接觸區域213可以是接觸墊,並且在一些實施例中,可在上面形成有凸塊下金屬結構。所述凸塊下金屬結構(若存在)可在與和外部連接件212相關聯的凸塊下金屬結構相同的製程步驟中形成。
轉到圖4,將一或多個積體裝置215貼合至接觸區域213以與重佈線結構210進行電性連接。如圖所示,可在相鄰的外部連接件212之間放置積體裝置215。圖4示出放置二個積體裝置215,但在其他實施例中,可使用更多或更少的積體裝置215。積體裝置215彼此可以是類似的裝置,或者可以是不同類型的裝置。在其他實施例中,可在形成外部連接件212之前將積體裝置215貼合至接觸區域213。可例如藉由以下方式將積體裝置215連接至接觸區域213:將用於形成積體裝置215的連接件(例如,導電凸塊或接墊)的(例如是)焊球(未示出)依次浸入焊劑中,且隨後使用拾取及放置工具(pick-and-place tool)以便將積體裝置215的連接件與對應的接觸區域213實體對準。在一些情形中,可執行回焊以將積體裝置215的連接件接合至接觸區域213。
舉例而言,積體裝置215可為包括一或多個被動裝置(例如,電容器、電阻器、電感器等)的半導體裝置或其他裝置。舉例而言,積體裝置215可為積體被動裝置(integrated passive devices,IPDs)。按照特定功能所需,積體裝置215亦可包括金屬化層,所述金屬化層電性耦合至積體裝置215內的被動裝置等。在一些實施例中,積體裝置215可被配置成為晶圓或半導體裝置(例如為圖10所示的半導體裝置500)提供電壓或電流穩定化。在一些情形中,藉由將積體裝置215貼合至重佈線結構210,可縮短積體裝置215與半導體裝置之間的佈線距離,此可減小積體裝置215與半導體裝置之間的電感及電阻。以此種方式,較短的佈線距離可改善裝置在較高頻率的操作,並提供改善的電壓或電流穩定性。在一些實施例中,積體裝置215具有介於約20微米與約500微米之間的厚度。在一些實施例中,積體裝置215具有介於約2平方毫米與約500平方毫米之間的橫向面積。積體裝置215也可具有除該些實例之外的其他尺寸。
轉到圖5A至圖5C,圖5A至圖5C根據一些實施例示出形成內連線結構300(參見圖5C)的中間步驟的剖視圖。內連線結構300貼合至裝置結構200(參見圖6至圖7)並提供附加的電性佈線。內連線結構300不具有主動裝置。在一些實施例中,內連線結構300可為例如中介物(interposer)或「半成品基板(semi-finished substrate)」。內連線結構300亦可為將貼合的裝置結構200提供穩定性及剛性,且可減少將貼合的裝置結構200的翹曲。圖5A根據一些實施例示出核心基材302的剖視圖,核心基材302具有設置於相對的表面上的多個導電層304。在一些實施例中,核心基材302可包含例如以下材料:味之素構成膜(Ajinomoto build-up film,ABF)、預浸漬複合纖維(預浸體(prepreg))材料、環氧樹脂、模製化合物、環氧模製化合物、玻璃纖維強化(fiberglass-reinforced)樹脂材料、印刷電路板(printed circuit board,PCB)材料、二氧化矽填料、聚合物材料、聚醯亞胺材料、紙、玻璃纖維、非織玻璃纖維布(non-woven glass fabric)、玻璃、陶瓷、其他疊層、類似材料或其組合。在一些實施例中,核心基材可為雙面敷銅疊層(copper-clad laminate,CCL)基板等。核心基材302可具有介於約20微米與約2000微米之間(例如約250微米或約500微米)的厚度。導電層304可包括疊層或以其他方式形成至核心基材302的相對側上的一或多個銅層、鎳層、鋁層、其他導電材料層、類似材料層或其組合。在一些實施例中,導電層304可具有介於約10奈米與約35000奈米之間的厚度。
參照圖5B,在核心基材302中形成開口(未示出),且在開口內形成穿孔306(以下進行闡述)。在一些實施例中,藉由例如雷射鑽孔(laser drilling)技術形成所述開口。在其他實施例中亦可使用其他製程,例如,機械鑽孔、蝕刻等形成所述開口。在一些實施例中,在形成開口之後可選擇性地執行表面準備製程(surface preparation process)。表面準備製程可包括用一或多種清潔溶液對核心基材302的被暴露出的表面及導電層304的被暴露出的表面進行清潔的製程。所述清潔溶液可包括硫酸(sulfuric acid)、鉻酸(chromic acid)、中和鹼性溶液(neutralizing alkaline solution)、沖洗液(water rinse)、類似溶液或其組合。在一些情形中,表面準備製程會移除或減少殘餘物、油、原生氧化物膜(native oxide film)等。在一些實施例中,可選擇性地執行除膠渣製程(desmear process),以對靠近開口的區域進行清潔。可執行除膠渣製程及表面準備製程,或執行除膠渣製程而不執行表面準備製程。舉例而言,除膠渣製程可移除核心基材302的殘餘材料。除膠渣製程可以以下方式完成:機械方式(例如,用濕漿料(wet slurry)中的細磨料(fine abrasive)進行噴砂(blasting))、化學方式(例如,用有機溶劑的組合、過錳酸鹽(permanganate)等進行沖洗)或藉由機械及化學除膠渣的組合。在表面準備製程或除膠渣製程之後,可使用化學調節劑(chemical conditioner)來執行調節處理,化學調節劑促進在後續無電鍍覆期間使用的活化劑的吸收。在一些實施例中,可在調節處理之後對導電層304進行微蝕刻(micro-etching),以使導電表面變粗糙,進而在導電層304與隨後沈積的佈線層308及佈線層309(以下進行闡述)的導電材料之間達成更好的接合。
仍參照圖5B,沈積導電材料以在核心基材302的一側上形成佈線層308且在核心基材302中的開口內形成穿孔306。在一些實施例中,佈線層308及穿孔306的行程方法包括首先在核心基材302之上形成圖案化遮罩。圖案化遮罩可為例如圖案化光阻層。圖案化遮罩中的開口會暴露出導電層304的隨後上面將形成導電材料的一些部分。圖案化遮罩中的開口亦可暴露出核心基材302中的開口。接著可使用例如鍍覆製程、無電鍍覆製程或其他製程在導電層304的被暴露出的區域上及核心基材302中的開口內沈積導電材料。在一些實施例中,導電材料被沈積成具有介於約1微米與約50微米之間的厚度。在沈積導電材料之後,可使用濕式化學製程或乾式製程(例如,灰化製程)來移除圖案化遮罩層(例如,光阻)。可隨著圖案化遮罩層移除導電層304的被圖案化遮罩層覆蓋的部分,或使用不同的蝕刻製程來移除圖案化遮罩層以及導電層304的此些部分。以此種方式,在核心基材302的一側上會形成佈線層308。接著可對核心基材302的相對的側執行相似的製程以在核心基材302的相對的側上形成佈線層309(及/或穿孔306的其餘部分)。以此種方式,導電材料可在核心基材302的相對側上形成佈線層308及佈線層309且形成延伸穿過核心基材302的穿孔306。
在一些實施例中,在沿開口的側壁形成導電材料之後,接著可用介電材料307填充開口,如圖5B所示。介電材料307可為導電材料提供結構支撐及保護。在一些實施例中,介電材料307可為例如以下材料:模製材料、環氧樹脂、環氧模製化合物、樹脂、類似材料或其組合。介電材料307可使用例如旋轉塗佈製程或另一製程形成。在一些實施例中,導電材料可完全填充穿孔306,從而省略介電材料307。
轉到圖5C,可在佈線層308及佈線層309之上形成介電層及附加的佈線層以形成佈線結構312及佈線結構316。佈線結構312及佈線結構316形成於核心基材302的相對側上且可在內連線結構300內提供附加的電性佈線。佈線結構312電性連接至佈線層308且包括交替的介電層310A至介電層310C及佈線層311A至佈線層311C。佈線結構316電性連接至佈線層309且包括交替的介電層314A至介電層314C及佈線層315A至佈線層315C。佈線結構312或佈線結構316中的每一者可具有任何合適數目的介電層或佈線層,包括多於或少於圖5C所示的數目。在一些實施例中,可省略佈線結構312或佈線結構316中的一者或二者。在一些實施例中,佈線結構312的層數可不同於佈線結構316的層數。
在一些實施例中,佈線結構312的形成方法包括在佈線層308及核心基材302之上形成介電層310A。在一些實施例中,介電層310A可例如由以下材料構成:構成(build-up)材料、ABF、預浸體材料、疊層材料、與以上針對核心基材302闡述的材料相似的其他種材料、類似材料或其組合。可藉由疊層製程、塗佈製程或另一合適的製程形成介電層310A。在一些實施例中,介電層310A可具有介於約2微米與約50微米之間的厚度。在一些實施例中,可在介電層310A之上形成導電層(未示出),所述導電層可用作形成導電材料的晶種層(以下進行闡述)。導電層可例如為金屬箔(metal foil)(例如銅箔)或其他類型的材料(例如以上針對導電層304闡述的材料)。在介電層310A中形成暴露出佈線層308的部分以用於後續電性連接的開口(未示出)。在一些實施例中,藉由例如雷射鑽孔技術形成所述開口。在其他實施例中,亦可使用其他製程(例如,機械鑽孔、蝕刻等)形成所述開口。在一些實施例中,在形成開口之後可選擇性地執行表面準備製程(例如,除膠渣製程等)。
接著沈積導電材料,以在介電層310A上及介電層310A中的開口內形成佈線層311A。在一些實施例中,佈線層311A的形成方法包括首先在介電層310A之上形成圖案化遮罩。圖案化遮罩可例如為圖案化光阻層。圖案化遮罩中的開口可暴露出介電層310A(或者,若存在,則暴露出介電層310A上的導電層)的隨後上面將形成導電材料的一些部分。圖案化遮罩中的開口亦可暴露出介電層310A中的開口。接著,可使用例如鍍覆製程、無電鍍覆製程或其他製程在介電層310A的被暴露出的區域上及介電層310A中的開口內沈積導電材料。在一些實施例中,導電材料被沈積成具有介於約1微米與約50微米之間的厚度。在沈積導電材料之後,可使用濕式化學製程或乾式製程(例如,灰化製程)來移除圖案化遮罩層(例如,光阻)。以此種方式,在佈線層308之上形成附加的佈線層311A,且附加的佈線層311A電性連接至佈線層308。
接著,可在佈線層311A及介電層310A之上形成附加的介電層310B至介電層310C及佈線層311B至佈線層311C,以在佈線結構312內提供附加的佈線及電性連接。介電層310B至介電層310C及佈線層311B至佈線層311C可形成為交替的層,且可使用與用於介電層310A或佈線層311A的製程及材料相似的製程及材料形成。舉例而言,可在佈線層(例如,佈線層311A)之上形成介電層(例如,介電層310B),且接著使用例如雷射鑽孔製程製作穿過介電層的開口,以暴露出下伏佈線層的一些部分。可在介電層之上形成圖案化遮罩且接著可形成導電材料並移除圖案化遮罩,進而在介電層之上形成佈線層。可重複進行該些步驟以形成具有合適數目及配置的介電層及佈線層的佈線結構312。
在一些實施例中,可在佈線層309之上形成介電層314A至介電層314C及佈線層315A至佈線層315C,以形成佈線結構316。佈線結構316可使用與以上闡述的佈線結構312的製程相似的製程形成。舉例而言,介電層314A至介電層314C可被形成為與佈線層315A至佈線層315C交替堆疊。可(藉由例如,使用雷射鑽孔)於介電層中形成開口,且在介電層之上沈積導電材料以形成佈線層。可重複進行該些步驟以形成具有合適數目及配置的介電層及佈線層的佈線結構316。佈線結構316可藉由穿孔306電性連接至佈線結構312。
在一些實施例中,在內連線結構300的佈線結構312及佈線結構316之上形成圖案化保護層(未示出)。所述保護層可為例如阻焊劑(solder resist)材料,且可被形成為保護佈線結構312或佈線結構316的表面。在一些實施例中,保護層可為藉由印刷、疊層、旋轉塗佈等形成的感光性材料。接著,可將感光性材料暴露於光學圖案(optical pattern)並對感光性材料進行顯影,進而在感光性材料中形成開口。在其他實施例中,可藉由以下方式形成保護層:沈積非感光性介電層(例如,氧化矽、氮化矽、類似材料或其組合),使用合適的微影技術在介電層之上形成圖案化光阻遮罩,且接著使用合適的蝕刻製程(例如,濕式蝕刻或乾式蝕刻)與圖案化光阻遮罩來對介電層進行蝕刻。可使用相同的技術在佈線結構312及佈線結構316之上形成保護層並將所述保護層圖案化。亦可使用其他製程及材料。
在一些實施例中,接著可對佈線結構312或佈線結構316的最頂部佈線層的被暴露出的表面選擇性地執行可焊性處理(solderability treatment)。舉例而言,如圖5C所示,可對佈線層311C的被暴露出的表面以及對佈線層315C的被暴露出的表面執行可焊性處理。所述處理可包括無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)製程、有機可焊性保護劑(organic solderability preservative,OSP)製程等。在一些實施例中,可在佈線結構312或佈線結構316中的一者或者二者上形成外部連接件(未示出)。舉例而言,外部連接件可為焊料凸塊。所述外部連接件可例如相似於外部連接件212(參見圖4)或可相似於以下針對圖10闡述的外部連接件406。在一些實施例中,內連線結構300是在與裝置結構200不同的設施中製造的。
圖6根據一些實施例示出將多個內連線結構300放置成與裝置結構200電性連接。圖6示出在將多個裝置結構200單體化之前,多個不同的內連線結構300將被接合至所述多個裝置結構200的實施例。在實施例中,使用例如拾取及放置製程將內連線結構300放置成與外部連接件212(位於裝置結構200上)實體接觸。可將內連線結構300放置成使得佈線結構的最頂部佈線層的被暴露出的區域與對應的外部連接件212對準。舉例而言,佈線結構312的佈線層311C(參見圖5C)的所述區域或佈線結構316(參見圖5C)的佈線層315C的所述區域可被放置成與外部連接件212實體接觸。一旦實體接觸,便可利用回焊製程將裝置結構200的外部連接件212接合至內連線結構300。在一些實施例中,在內連線結構300上形成外部連接件,而不在裝置結構200上形成外部連接件212,或者,在內連線結構300上形成外部連接件以及在裝置結構200上形成外部連接件212。
在圖6所示的實施例中,示出單體化之前的裝置結構200。在其他實施例中,裝置結構200可在貼合內連線結構300之前被單體化。如圖6所示,可將相鄰的內連線結構300放置成使得在所述相鄰的內連線結構300之間存在間隙D1。在一些實施例中,可對相鄰的內連線結構300的間隔進行控制,使得間隙D1是特定的距離或介於特定的距離範圍內。舉例而言,間隙D1可為介於約10微米與約5000微米之間的距離。在一些情形中,可對間隙D1距離進行控制以避免在放置期間相鄰的內連線結構300之間的碰撞(collision)。在一些情形中,可對間隙D1距離進行控制以利於以下參照圖7闡述的模製底部填充膠402的後續沈積。
圖7根據一些實施例示出內連線結構300貼合至裝置結構200。如圖7所示,積體裝置215位於內連線結構300與其對應的裝置結構200之間的間隙中。以此種方式,積體裝置215可被倂入在結構(例如,圖11所示的封裝體600)內而不會增加結構的整體厚度。在一些實施例中,內連線結構300的底部介電層與裝置結構200的頂部絕緣層之間的垂直距離介於約20微米與約5000微米之間。在圖7中,沿內連線結構300的側壁以及在內連線結構300與裝置結構200之間的間隙中沈積底部填充膠402。底部填充膠402亦可至少局部地環繞一些外部連接件212或一些積體裝置215。在一些實施例中,底部填充膠402的一些部分在積體裝置215與內連線結構300之間延伸。底部填充膠402可例如為模製化合物、環氧樹脂、底部填充膠、模製底部填充膠(molding underfill,MUF)、樹脂等材料。底部填充膠402可保護外部連接件212及積體裝置215且可為裝置結構提供結構支撐。在一些實施例中,底部填充膠402可在沈積之後被固化。在一些實施例中,底部填充膠402可在沈積之後被薄化。可例如使用機械研磨或化學機械研磨(chemical mechanical polishing,CMP)製程執行所述薄化。在一些實施例中,可在佈線結構312之上沈積底部填充膠402,且所述薄化可暴露出佈線結構312的最頂部佈線層(例如,佈線層311C)。
圖8根據一些實施例示出載體基板202的剝離以及在裝置結構200的接觸墊104上形成導電連接件404。可使用例如熱製程以改變設置在載體基板202上的離形層的黏合性質而自裝置結構200剝離載體基板202。在特定實施例中,使用例如紫外線(UV)雷射、二氧化碳(CO2
)雷射或紅外線(IR)雷射等能量源來照射並加熱離形層,直至離形層失去其至少一些黏合性質。一旦執行,便可自裝置結構200實體分離並移除載體基板202及離形層。在一些實施例中,結構可被翻轉,並且內連線結構300可貼合至臨時基板(未示出),例如條帶(tape)、晶圓、面板、框架、環等。
在圖8中,在裝置結構200的接觸墊104之上形成導電連接件404,且將導電連接件404電性連接至裝置結構200的接觸墊104。在一些實施例中,在接觸墊104上形成凸塊下金屬結構,且在凸塊下金屬結構之上形成導電連接件404。在一些實施例中,首先在佈線結構210之上形成保護層(未示出)。若存在凸塊下金屬結構,則可在凸塊下金屬結構之上形成保護層。保護層可由以下一或多種合適的介電材料形成:例如聚苯並噁唑(PBO)、聚合物材料、聚醯亞胺材料、聚醯亞胺衍生物、氧化物、氮化物、類似材料或其組合。可藉由例如旋轉塗佈、疊層、CVD、類似製程或其組合等製程形成保護層。接著,可在保護層中形成開口以暴露出接觸墊104(若存在凸塊下金屬結構,則接觸墊104可包括凸塊下金屬結構)。可利用合適的技術(例如雷射鑽孔或微影遮罩及蝕刻製程)形成保護層中的開口。隨後,在接觸墊104之上形成導電連接件404,且導電連接件404與重佈線結構210進行電性連接。
導電連接件404可例如為接觸凸塊或焊料球(例如,C4球),但也可利用其他任何合適類型的連接件。在其中導電連接件404是接觸凸塊的實施例中,導電連接件404可包含例如錫等材料或例如銀、無鉛錫或銅等其他合適的材料。在其中導電連接件404是錫焊料凸塊的實施例中,可藉由以下方式形成導電連接件404:在開始時使用例如蒸發、電鍍、印刷、焊料轉移、植球等此種技術形成錫層。一旦在所述結構上形成錫層,便可執行回焊以將所述材料塑形成導電連接件404期望的凸塊形狀。在一些實施例中,導電連接件404可類似於以上針對圖3闡述的外部連接件212。
圖9根據一些實施例示出將結構單體化以形成封裝結構400。在實施例中,可使用一或多個鋸片將所述結構單體化,所述一或多個鋸片將所述結構分成分立的部分,藉此形成一或多個單體化封裝結構400。然而,亦可利用任何合適的單體化方法,包括雷射燒蝕或者一或多個濕式蝕刻。在單體化之後,可將封裝結構400自臨時基板移除。在一些實施例中,封裝結構400可具有介於約20毫米乘20毫米與約500毫米乘500毫米之間(例如約100毫米乘100毫米)的橫向尺寸,但封裝結構400也可具有不同於該些尺寸的其他尺寸。在一些實施例中,封裝結構400可具有介於約20微米與約5000微米之間的垂直厚度。
仍參照圖9,每一封裝結構400包括裝置結構200及內連線結構300。在圖9所示的實施例中,裝置結構200的橫向尺寸大於內連線結構300。由於裝置結構200寬於內連線結構300,因此在單體化之後底部填充膠402的部分可保留於內連線結構300的一或多個側壁上,如圖所示。在一些實施例中,底部填充膠402可具有與裝置結構200的側壁成平面的一或多個側壁。在一些實施例中,內連線結構300的橫向寬度可介於裝置結構200的橫向寬度的約50%與約100%之間。在一些實施例中,內連線結構300的橫向寬度可介於約10毫米與約500毫米之間。在一些實施例中,裝置結構200的橫向寬度可介於約20毫米與約500毫米之間。在其他實施例中,單體化製程自內連線結構300的側壁移除底部填充膠402,使得內連線結構300的側壁被暴露出(未示出)。
形成如本文中所闡述的包括貼合至裝置結構200的內連線結構300的封裝結構400可達成一些優點。舉例而言,具有更大的橫向尺寸的結構可能更易於翹曲或分層。如本文中所闡述的內連線結構300可為相對剛性較高的且因此可為裝置結構200提供結構支撐,進而減少裝置結構200的翹曲。另外,保留於內連線結構300的側壁上的底部填充膠402可向內連線結構300提供附加的保護及結構支撐。
圖10示出將半導體裝置500貼合至導電連接件404,藉此在半導體裝置500與重佈線結構210之間進行電性連接。可使用合適的製程(例如拾取及放置製程)將半導體裝置500放置於導電連接件404上。半導體裝置500可包括一或多個裝置,所述一或多個裝置可包括設計用於預期目的的裝置,例如記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、堆疊式記憶體(stacked memory)晶粒、高頻寬記憶體(high-bandwidth memory,HBM)晶粒等)、邏輯晶粒、中央處理單元(central processing unit,CPU)晶粒、系統晶圓(system-on-a-chip,SoC)、晶圓上組件(component on a wafer,CoW)、積體扇出型結構(InFO)、封裝體等或其組合。在實施例中,半導體裝置500按照特定功能所需包括位於其中的積體電路裝置,例如電晶體、電容器、電感器、電阻器、金屬化層、外部連接件等。在一些實施例中,半導體裝置500可包括多於一個同一類型的裝置或可包括不同的裝置。圖10示出單個半導體裝置500,但在其他實施例中,可將一個、兩個或多於三個半導體裝置500貼合至導電連接件404。
可將半導體裝置500放置成使得半導體裝置的導電區域(例如,接觸墊)與對應的導電連接件404對準。一旦實體接觸,便可利用回焊製程將裝置結構200的導電連接件404接合至半導體裝置500。在一些實施例中,在半導體裝置500上形成外部連接件,而不在裝置結構200上形成導電連接件404,或者,在半導體裝置500上形成外部連接件以及在裝置結構200上形成導電連接件404。在一些實施例中,在裝置結構200上未形成導電連接件404,且使用直接接合技術(例如熱壓接合技術(thermocompression bonding technique))將半導體裝置500接合至裝置結構200。如在圖10中所示,可沿半導體裝置500與裝置結構200之間的間隙的側壁沈積底部填充膠502。底部填充膠502亦可至少局部地環繞一些導電連接件404。底部填充膠502可例如為模製化合物、環氧樹脂、底部填充膠、模製底部填充膠(molding underfill,MUF)、樹脂等材料,且可與先前所述的底部填充膠402類似。
在圖11中,在內連線結構300之上形成外部連接件406,並將外部連接件406電性連接至內連線結構300,藉此形成封裝體600。外部連接件406可形成於佈線結構312的最頂部佈線層(例如,佈線層311C)的被暴露出的一些部分上。在一些實施例中,在佈線結構312上形成凸塊下金屬結構,且在凸塊下金屬結構之上形成外部連接件406。在一些實施例中,首先在佈線結構312之上形成保護層(未示出)。若存在凸塊下金屬結構,則保護層可形成於凸塊下金屬結構之上。所述保護層可與先前針對圖8所述的保護層類似,且可以類似的方式形成。可在保護層中形成開口以暴露出佈線結構312(若存在凸塊下金屬結構,其可包括凸塊下金屬結構)的一些部分。
接著在佈線結構312的被暴露出的部分之上形成外部連接件406,且外部連接件406與佈線結構312進行電性連接。外部連接件406可例如為接觸凸塊或焊料球,但可利用任何合適類型的連接件。在其中外部連接件406是接觸凸塊的實施例中,外部連接件406可包含例如錫等材料或例如銀、無鉛錫或銅等其他合適的材料。在其中外部連接件406是錫焊料凸塊的實施例中,可藉由以下方式形成外部連接件406:在開始時使用例如蒸發、電鍍、印刷、焊料轉移、植球等此種技術形成錫層。一旦在所述結構上形成錫層,便可執行回焊以將所述材料塑形成外部連接件406期望的凸塊形狀。在一些實施例中,外部連接件406可具有介於約2微米與約1000微米之間的厚度。在一些實施例中,外部連接件406可具有介於約25微米與約1500微米之間的節距。在一些實施例中,外部連接件406可相似於以上針對圖3闡述的外部連接件212。
藉由形成其中積體裝置215設置在重佈線結構210與內連線結構300之間的間隙中的封裝體600,可改善封裝體600的電性效能。舉例而言,可縮短積體裝置215與半導體裝置500之間的距離,此可減小佈線距離且因此減小積體裝置215與半導體裝置500之間的電阻或電感。舉例而言,藉由以此種方式減小距離,由電阻引起的電壓降亦可被減小。在一些情形中,半導體裝置500與安裝在重佈線結構210的相對側上的積體裝置215之間的距離(如圖11所示)可小於半導體裝置與鄰近所述半導體裝置且安裝在重佈線結構的同一側上的積體裝置之間的距離。積體裝置215與半導體裝置500之間的距離亦可小於半導體裝置與安裝在內連線結構內或內連線結構的相對側上的積體裝置之間的距離。在一些實施例中,積體裝置215與半導體裝置500之間的垂直距離可小於約10毫米,例如為小於約0.3毫米的距離。在一些情形中,藉由如本文中所述將積體裝置215安裝在重佈線結構210與內連線結構300之間,積體裝置215與半導體裝置500之間的等效自感(equivalent self-inductance)可減少大於約85%,例如大於約99%。藉由降低電感,可改善封裝體600的高頻效能。舉例而言,封裝體的可用操作頻率可能會增加多達約300%。在一些情形中,可用的操作頻率可能增加至大約600 MHz或大於600 MHz的頻率。此外,由於更穩定的電性效能,封裝體600的功率完整性(power integrity)可得到改善。
在一些情形中,重佈線結構210可利用較佈線結構312或佈線結構316更穩健且更可靠的技術形成。舉例而言,重佈線結構210可使用扇出型製程形成(例如,在半導體製作廠中),而佈線結構312及佈線結構316可使用積層製程(build-up process)形成。藉由使用更穩健的製程,重佈線結構210可具有較佈線結構312及佈線結構316高的良率。在一些情形中,相較於在佈線結構312及佈線結構316中形成佈線層的製程,形成重佈線結構210的製程可形成具有更小的尺寸且具有更小的線寬粗糙度(line width roughness)的重佈線層。因此,相對於佈線結構312及佈線結構316,重佈線結構210可具有改善的電性效能,特別是在高頻率操作的情形中。
在一些情形中,藉由形成重佈線結構210而作為裝置結構200的一部分,內連線結構300的佈線結構312或佈線結構316可被形成為具有更少的層。藉由在重佈線結構210內形成封裝體600的更多電性佈線以及在佈線結構312或佈線結構316內形成更少電性佈線,封裝體600的總體電性效能可得到改善,如先前所述。重佈線結構210可具有較佈線結構312及佈線結構316的單個層薄的單個層,此可減小封裝體600的總體大小。另外,封裝體600的總體製造成本可藉由在重佈線結構210內形成更多的層而降低。
在一些情形中,封裝體或裝置中具有大的熱膨脹係數(coefficient of thermal expansion,CTE)差異的材料可在較高的溫度操作下造成分層、短路或其他故障。在一些情形中,重佈線結構210可包含的材料所具有的CTE與內連線結構300的材料的CTE相較而言更接近半導體裝置500(或封裝體600中的其他材料)的CTE。舉例而言,重佈線結構210的絕緣層的CTE可小於佈線結構312或佈線結構316的介電層的CTE。因此,藉由在裝置結構200中形成更多電性佈線且在內連線結構300中形成更少電性佈線,封裝體600的可靠性可得到改善,特別是在較高溫度操作下。
在實施例中,一種封裝體的製造方法包括:在載體上形成重佈線結構;將積體被動裝置貼合至所述重佈線結構的第一側上;將內連線結構貼合至所述重佈線結構的所述第一側,其中所述積體被動裝置夾置在所述重佈線結構與所述內連線結構之間;在所述內連線結構與所述重佈線結構之間沈積底部填充材料;以及將半導體裝置貼合至所述重佈線結構的與所述重佈線結構的所述第一側相對的第二側上。在實施例中,所述內連線結構包括核心基材。在實施例中,所述底部填充材料覆蓋所述內連線結構的側壁。在實施例中,覆蓋所述內連線結構的所述側壁的所述底部填充材料與所述重佈線結構的側壁共面。在實施例中,將所述內連線結構貼合至所述重佈線結構包括:在所述重佈線結構上形成多個焊料凸塊;以及將所述內連線結構放置於所述多個焊料凸塊上。在實施例中,所述封裝體的製造方法更包括:在貼合所述積體被動裝置及所述內連線結構之後,對所述積體被動裝置及所述內連線結構執行回焊製程。在實施例中,其中所述積體被動裝置在垂直方向上直接設置在所述半導體裝置與所述內連線結構之間。在實施例中,其中形成所述重佈線結構包括:在所述載體之上沈積聚合物層;在所述聚合物層中圖案化出多個開口;在所述聚合物層之上形成圖案化遮罩;以及使用所述圖案化遮罩而在所述聚合物層之上沈積導電材料。
在實施例中,一種封裝體的製造方法包括:在載體基板上形成多個第一接觸墊;在所述第一接觸墊上形成重佈線結構;在所述重佈線結構上形成多個第二接觸墊;將積體被動裝置電性連接至所述多個第二接觸墊的第一組;使用多個導電連接件將內連線結構電性連接至所述多個第二接觸墊的第二組;以及將半導體晶粒電性連接至所述多個第一接觸墊。在實施例中,所述積體被動裝置橫向設置在所述多個導電連接件的兩者之間。在實施例中,所述積體被動裝置設置在所述重佈線結構與所述內連線結構之間的間隙中。在實施例中,所述方法更包括:在將所述內連線結構電性連接至所述多個第二接觸墊的所述第二組之後,在所述內連線結構與所述重佈線結構之間沈積模製材料。在實施例中,所述封裝體的製造方法更包括:對所述重佈線結構執行單體化製程,其中在執行所述單體化製程之後,底部填充材料保留在所述內連線結構的側壁上。在實施例中,所述重佈線結構具有第一橫向寬度且所述內連線結構具有第二橫向寬度,其中所述第一橫向寬度大於所述第二橫向寬度。在實施例中,所述封裝體的製造方法更包括形成所述內連線結構,其中形成所述內連線結構包括:在核心基材的第一側之上形成多個第一導電跡線;在所述核心基材的第二側之上形成多個第二導電跡線;以及形成延伸穿過所述核心基材的多個穿孔,所述穿孔電性連接至所述多個第一導電跡線且電性連接至所述多個第二導電跡線。
在實施例中,一種封裝體包括:內連線結構;重佈線結構,電性連接至所述內連線結構;至少一個積體裝置,位於所述重佈線結構與所述內連線結構之間的間隙中,所述至少一個積體裝置電性連接至所述內連線結構;底部填充材料,位於所述重佈線結構與所述內連線結構之間的所述間隙中,所述底部填充材料自所述重佈線結構延伸至所述內連線結構並且至少橫向圍繞所述至少一個積體裝置;以及至少一個半導體裝置,位於所述重佈線結構的與所述積體裝置相對的一側上,所述至少一個半導體裝置電性連接至所述重佈線結構。在實施例中,至少一個積體裝置與至少一個半導體裝置之間的距離小於0.3毫米。在實施例中,所述內連線結構包括核心基材。在實施例中,所述底部填充材料沿著所述內連線結構的側壁延伸。在實施例中,所述底部填充材料在所述至少一個積體裝置與所述內連線結構之間延伸。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,該些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
102:載體基板
104:接觸墊
200:裝置結構
202:載體基板
208A-208G:絕緣層
209A-209G:重佈線層
210:重佈線結構
212:外部連接件
213:接觸區域
215:積體裝置
300:內連線結構
302:核心基材
304:導電層
306:穿孔
307:介電材料
308、309:佈線層
310A、310B、310C:介電層
311A、311B、311C:佈線層
312:佈線結構
314A、314B、314C:介電層
315A、315B、315C:佈線層
316:佈線結構
400:封裝結構
402:底部填充膠
404:導電連接件
406:外部連接件
500:半導體裝置
502:底部填充膠
600:封裝體
D1:間隙
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本產業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1至圖4根據一些實施例示出形成裝置結構的中間步驟的剖視圖。
圖5A至圖5C根據一些實施例示出形成內連線結構的中間步驟的剖視圖。
圖6至圖11根據一些實施例示出形成封裝體的中間步驟的剖視圖。
200:裝置結構
202:載體基板
210:重佈線結構
212:外部連接件
215:積體裝置
300:內連線結構
312:佈線結構
316:佈線結構
D1:間隙
Claims (20)
- 一種封裝體的製造方法,包括: 在載體上形成重佈線結構; 將積體被動裝置貼合至所述重佈線結構的第一側上; 將內連線結構貼合至所述重佈線結構的所述第一側,其中所述積體被動裝置夾置在所述重佈線結構與所述內連線結構之間; 在所述內連線結構與所述重佈線結構之間沈積底部填充材料; 將半導體裝置貼合至所述重佈線結構的與所述重佈線結構的所述第一側相對的第二側上。
- 如申請專利範圍第1項所述的封裝體的製造方法,其中所述內連線結構包括核心基材。
- 如申請專利範圍第1項所述的封裝體的製造方法,其中所述底部填充材料覆蓋所述內連線結構的側壁。
- 如申請專利範圍第3項所述的封裝體的製造方法,其中覆蓋所述內連線結構的所述側壁的所述底部填充材料與所述重佈線結構的側壁共面。
- 如申請專利範圍第1項所述的封裝體的製造方法,其中將所述內連線結構貼合至所述重佈線結構包括: 在所述重佈線結構上形成多個焊料凸塊;以及 將所述內連線結構放置於所述多個焊料凸塊上。
- 如申請專利範圍第1項所述的封裝體的製造方法,更包括:在貼合所述積體被動裝置及所述內連線結構之後,對所述積體被動裝置及所述內連線結構執行回焊製程。
- 如申請專利範圍第1項所述的封裝體的製造方法,其中所述積體被動裝置在垂直方向上直接設置在所述半導體裝置與所述內連線結構之間。
- 如申請專利範圍第1項所述的封裝體的製造方法,其中形成所述重佈線結構包括: 在所述載體之上沈積聚合物層; 在所述聚合物層中圖案化出多個開口; 在所述聚合物層之上形成圖案化遮罩;以及 使用所述圖案化遮罩而在所述聚合物層之上沈積導電材料。
- 一種封裝體的製造方法,包括: 在載體基板上形成多個第一接觸墊; 在所述第一接觸墊上形成重佈線結構; 在所述重佈線結構上形成多個第二接觸墊; 將積體被動裝置電性連接至所述多個第二接觸墊的第一組; 使用多個導電連接件將內連線結構電性連接至所述多個第二接觸墊的第二組;以及 將半導體晶粒電性連接至所述多個第一接觸墊。
- 如申請專利範圍第9項所述的封裝體的製造方法,其中所述積體被動裝置橫向設置在所述多個導電連接件的兩者之間。
- 如申請專利範圍第9項所述的封裝體的製造方法,其中所述積體被動裝置設置在所述重佈線結構與所述內連線結構之間的間隙中。
- 如申請專利範圍第9項所述的封裝體的製造方法,更包括:在將所述內連線結構電性連接至所述多個第二接觸墊的所述第二組之後,在所述內連線結構與所述重佈線結構之間沈積模製材料。
- 如申請專利範圍第12項所述的封裝體的製造方法,更包括:對所述重佈線結構執行單體化製程,其中在執行所述單體化製程之後,底部填充材料保留在所述內連線結構的側壁上。
- 如申請專利範圍第9項所述的封裝體的製造方法,其中所述重佈線結構具有第一橫向寬度且所述內連線結構具有第二橫向寬度,其中所述第一橫向寬度大於所述第二橫向寬度。
- 如申請專利範圍第9項所述的封裝體的製造方法,更包括形成所述內連線結構,其中形成所述內連線結構包括: 在核心基材的第一側之上形成多個第一導電跡線; 在所述核心基材的第二側之上形成多個第二導電跡線;以及 形成延伸穿過所述核心基材的多個穿孔,所述穿孔電性連接至所述多個第一導電跡線且電性連接至所述多個第二導電跡線。
- 一種封裝體,包括: 內連線結構; 重佈線結構,電性連接至所述內連線結構; 至少一個積體裝置,位於所述重佈線結構與所述內連線結構之間的間隙中,所述至少一個積體裝置電性連接至所述內連線結構; 底部填充材料,位於所述重佈線結構與所述內連線結構之間的所述間隙中,所述底部填充材料自所述重佈線結構延伸至所述內連線結構並且至少橫向圍繞所述至少一個積體裝置;以及 至少一個半導體裝置,位於所述重佈線結構的與所述積體裝置相對的一側上,所述至少一個半導體裝置電性連接至所述重佈線結構。
- 如申請專利範圍第16項所述的封裝體,其中所述至少一個積體裝置與所述至少一個半導體裝置之間的距離小於0.3毫米。
- 如申請專利範圍第16項所述的封裝體,其中所述內連線結構包括核心基材。
- 如申請專利範圍第16項所述的封裝體,其中所述底部填充材料沿著所述內連線結構的側壁延伸。
- 如申請專利範圍第16項所述的封裝體,其中所述底部填充材料在所述至少一個積體裝置與所述內連線結構之間延伸。
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US10763239B2 (en) * | 2017-10-27 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-chip wafer level packages and methods of forming the same |
US10971446B2 (en) * | 2018-11-30 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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2019
- 2019-07-01 US US16/458,374 patent/US10971446B2/en active Active
- 2019-10-09 TW TW108136768A patent/TWI718704B/zh active
- 2019-11-29 CN CN201911203961.1A patent/CN111261530B/zh active Active
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2021
- 2021-04-05 US US17/222,225 patent/US11715686B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI788099B (zh) * | 2021-11-15 | 2022-12-21 | 大陸商芯愛科技(南京)有限公司 | 電子封裝件及其封裝基板 |
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TWI718704B (zh) | 2021-02-11 |
CN111261530A (zh) | 2020-06-09 |
CN111261530B (zh) | 2022-07-01 |
US20200176378A1 (en) | 2020-06-04 |
US11715686B2 (en) | 2023-08-01 |
US10971446B2 (en) | 2021-04-06 |
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