TW201916298A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW201916298A
TW201916298A TW107104360A TW107104360A TW201916298A TW 201916298 A TW201916298 A TW 201916298A TW 107104360 A TW107104360 A TW 107104360A TW 107104360 A TW107104360 A TW 107104360A TW 201916298 A TW201916298 A TW 201916298A
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Taiwan
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hole
conductive
dielectric layer
layer
conductive feature
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TW107104360A
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TWI652786B (zh
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余振華
蔡豪益
曾明鴻
郭庭豪
林彥良
黃子松
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台灣積體電路製造股份有限公司
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Publication of TWI652786B publication Critical patent/TWI652786B/zh
Publication of TW201916298A publication Critical patent/TW201916298A/zh

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Abstract

提供一種裝置，所述裝置包括第一裝置封裝，所述第一裝置封裝包括：第一重佈線結構，包括第一重佈線及第二重佈線；晶粒，位於第一重佈線結構上；第一通孔，耦合到第一重佈線的第一側；第二通孔，耦合到第二重佈線的第一側且延伸穿過所述第二重佈線；包封體，環繞晶粒、第一通孔、及第二通孔；以及第二重佈線結構，位於包封體之上，所述第二重佈線結構電連接到晶粒、第一通孔、及第二通孔。所述裝置還包括：第一導電連接件，耦合到第一重佈線的第二側，所述第一導電連接件沿與第一通孔的縱向軸線不同的軸線設置；第二導電連接件，耦合到第二重佈線的第二側，所述第二導電連接件沿第二通孔的縱向軸線設置。

Description

半導體封裝及其形成方法
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度的持續提高，半導體行業已經歷快速發展。在很大程度上，集成密度的提高來自於最小特徵大小（minimum feature size）的重複減小，此使得更多的元件能夠集成到給定區域中。隨著對縮小電子裝置的需求的增長，需要更小且更具創造性的半導體晶粒封裝技術。此種封裝系統的一個實例是疊層封裝（Package-on-Package，PoP）技術。在疊層封裝裝置中，頂部半導體封裝被堆疊在底部半導體封裝頂上，以提供高集成水準及元件密度。疊層封裝技術一般能夠生產功能性得到增強且在印刷電路板（printed circuit board，PCB）上佔用空間（footprint）小的半導體裝置。
以下揭露內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本揭露內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，揭露半導體封裝及其形成方法。具體來說，形成具有重佈線的第一重佈線結構。形成從第一導電特徵（conductive feature）的表面延伸的第一通孔。形成從第二導電特徵與第三導電特徵之間的間隙延伸的第二通孔。第二通孔比第一通孔長。將例如焊料等導電連接件貼合到第一重佈線結構的背側。將第一導電連接件耦合到第一導電特徵，且相對于第一通孔偏置。這樣一來，在回焊（reflow）期間形成的金屬間化合物（intermetallic compound，IMC）不在側向上延伸到第一通孔。將第二導電連接件耦合到第二導電特徵及第三導電特徵，且所述第二導電連接件與第二通孔對齊。這樣一來，當在回焊期間形成金屬間化合物時，銅會從第二通孔擴散，而不會從第二導電特徵及第三導電特徵擴散。避免銅從第二導電特徵及第三導電特徵擴散可避免在形成通孔期間使用的晶種層層離（delamination）。
圖1至圖14是根據一些實施例的形成裝置封裝200的製程期間各中間步驟的各種圖。圖1至圖14是剖視圖。可將裝置封裝200稱作集成扇出（integrated fan-out，InFO）型封裝。
在圖1中，示出處於加工的中間階段的裝置封裝200，裝置封裝200包括形成在載體基板100上的釋放層（release layer）102。用於形成裝置封裝200的封裝區600也被例示出。儘管僅示出一個封裝區，然而也可形成有許多封裝區。
載體基板100可為玻璃載體基板、陶瓷載體基板等。載體基板100可為晶片，使得可在載體基板100上同時形成多個封裝。釋放層102可由聚合物系材料形成，所述聚合物系材料可與載體基板100一起從將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層102是會在受熱時失去其粘著特性的環氧樹脂系熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，釋放層102可為會在被暴露至紫外光時失去其粘著特性的紫外光（ultra-violet，UV）膠。釋放層102可作為液體進行分配並進行固化，釋放層102可為被疊層到載體基板100上的疊層體膜（laminate film），或可為其他形式。釋放層102的頂表面可以是等高（leveled）且釋放層102的頂表面可具有高共面程度（degree of coplanarity）。
在圖2中，在釋放層102上形成介電層104。介電層104的底表面可接觸釋放層102的頂表面。在一些實施例中，介電層104是由例如聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide）、苯並環丁烯（benzocyclobutene，BCB）等聚合物形成。在其他實施例中，介電層104是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）等；或者類似材料。可通過例如旋轉塗布（spin coating）、化學氣相沉積（chemical vapor deposition，CVD）、疊層（laminating）、類似製程、或其組合等任何可接受的沉積製程來形成介電層104。
在圖3中，在介電層104之上形成晶種層106。在一些實施例中，晶種層106為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層106包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積（physical vapor deposition，PVD）等來形成晶種層106。
在圖4中，在介電層104之上形成金屬化圖案108。在晶種層106上形成光阻（圖中未示出）並將所述光阻圖案化。可通過旋轉塗布（spin coating）等來形成光阻並可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案108。所述圖案化會形成穿過光阻的開口以暴露出晶種層106。在光阻的開口中及晶種層106的被暴露部分上形成導電材料。可通過例如電鍍（electroplating）或無電鍍覆（electroless plating）等鍍覆製程來形成所述導電材料。所述導電材料可為金屬或金屬合金，例如銅、鈦、鎢、鋁等或其組合。接著，移除光阻以及晶種層106的上面未形成有導電材料的部分。可通過例如使用氧等離子體等的可接受灰化製程（ashing process）或剝除製程（stripping process）來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（如通過濕蝕刻（wet etching）或乾蝕刻（dry etching））來移除晶種層106的被暴露部分。晶種層106的其餘部分及導電材料會形成金屬化圖案108。
可將金屬化圖案108的導電特徵稱作重佈線層或重佈線。可不將重佈線形成為具有均勻的寬度，且所述重佈線中的一些重佈線可包括多個導電特徵。第一重佈線108A可各自包括單一導電特徵，所述單一導電特徵將電連接到裝置封裝200的各裝置。第二重佈線108B可各自包括通過間隙110而隔開的多個導電特徵，且所述多個導電特徵電連接在一起並電連接到裝置封裝200的各裝置。第二重佈線108B的組合寬度WB 實質上等於第一重佈線108A的寬度WA ，或者可有所不同。
在一些實施例中，在形成金屬化圖案108期間單獨地形成第二重佈線108B的導電特徵，例如每一導電特徵可對應於光阻中的暴露出晶種層106的開口。在一些實施例中，在形成金屬化圖案108期間形成單一導電特徵，且之後使用可接受的蝕刻技術形成間隙110以將所述單一導電特徵劃分成多個導電特徵。間隙110被形成為具有寬度WG 。間隙110可從第二重佈線108B的頂表面延伸到第二重佈線108B的底表面，從而暴露出介電層104。間隙110可形成在第二重佈線108B的中心中，使得第二重佈線108B的各導電特徵為相同長度，或者可被形成為相對於第二重佈線108B的中心偏置，使得第二重佈線108B的各導電特徵為不同長度。
在圖5中，在金屬化圖案108及介電層104上形成介電層112。在一些實施例中，介電層112是由聚合物形成，所述聚合物可為例如聚苯並惡唑、聚醯亞胺、苯並環丁烯等可使用光罩（lithography mask）進行圖案化的感光性材料。在其他實施例中，介電層112是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可通過旋轉塗布、疊層、化學氣相沉積、類似製程、或其組合來形成介電層112。
接著將介電層112圖案化以形成暴露出金屬化圖案108的一些部分的開口114。通過可接受的製程來進行所述圖案化，例如當介電層112為感光性材料時通過將所述介電層暴露至光來進行所述圖案化，或者通過使用例如各向異性蝕刻（anisotropic etch）進行蝕刻來進行所述圖案化。形成暴露出第一重佈線108A的第一開口114A，且形成暴露出第二重佈線108B的第二開口114B。第二開口114B形成在第二重佈線108B的間隙110之上；這樣一來，導電特徵的側邊被暴露出，所述導電特徵的頂表面的一些部分被暴露出，且介電層104的一些部分被暴露出。在所說明實施例中，第一開口114A與第二開口114B各自具有相同的寬度WO 。在其他實施例中，第一開口114A與第二開口114B具有不同的寬度。開口114的寬度WO 比間隙110的寬度WG 大。
開口114可形成在金屬化圖案108中的每一者的中心之上，或者可被形成為相對於所述中心偏置。在所示實施例中，第一開口114A被形成為相對於金屬化圖案108的中心偏置，且第二開口114B形成在金屬化圖案108的中心之上。
可將介電層104及112以及金屬化圖案108稱作背側重佈線結構（back-side redistribution structure）116。如圖所示，背側重佈線結構116包括所述兩個介電層104及112以及一個金屬化圖案108。在其他實施例中，背側重佈線結構116可包括任何數目的介電層、金屬化圖案、及通孔。可通過重複進行所述形成金屬化圖案108及介電層112的製程而在背側重佈線結構116中形成一個或多個額外的金屬化圖案及介電層。可在所述形成金屬化圖案期間通過在下伏介電層的開口中形成所述晶種層以及所述金屬化圖案的導電材料來形成通孔。所述通孔可因此對各種金屬化圖案進行內連及電耦合。
在圖6中，在背側重佈線結構116之上及開口114中形成晶種層118。晶種層118位於介電層112之上、金屬化圖案108的被暴露部分之上、及介電層104的被暴露部分之上。在一些實施例中，晶種層118為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層118包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層118。
在圖7中，在晶種層118上形成光阻120並將光阻120圖案化。可通過旋轉塗布等來形成光阻120並可將光阻120暴露至光以進行圖案化。光阻120的圖案對應于隨後將形成的穿孔。所述圖案化會形成穿過光阻120的開口以暴露出晶種層118。在介電層112中在開口114之上設置穿過光阻120的開口，且各所述開口可在第一開口114A與第二開口114B二者之上具有相同寬度WP 。所述開口的寬度WP 比開口114的寬度WO 大。
在圖8中，在光阻120的開口中及晶種層118的被暴露部分上形成導電材料。可通過例如電鍍或無電鍍覆等鍍覆製程來形成所述導電材料。所述導電材料可為金屬或金屬合金，例如銅、鈦、鎢、鋁等或其組合。移除光阻120以及晶種層118的上面未形成有導電材料的一些部分。可通過例如使用氧等離子體等的可接受灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）來移除晶種層118的被暴露部分。晶種層的其餘部分與導電材料會形成穿孔122，穿孔122電連接到重佈線。
由於晶種層118形成在第二重佈線108B的間隙110中，因此會形成延伸穿過第二重佈線108B的第二通孔122B。相反，在第一重佈線108A上會形成第一通孔122A，且第一通孔122A不延伸穿過第一重佈線108A。第一通孔122A與第二通孔122B二者可在介電層112之上具有相同寬度WP ，且在開口114中具有相同寬度WO 。第二通孔122B還在間隙110中具有寬度WG 。由於第二通孔122B具有分別遞減的三種不同的寬度，因此可將第二通孔122B稱作具有梯形結構（ladder structure）。由於第一開口114A被形成為相對於金屬化圖案108的中心偏置，因此第一通孔122A被形成為相對於第一重佈線108A的中心偏置。
儘管將第一通孔122A示為在寬度上具有一種變化且將第二通孔122B示為在寬度上具有兩種變化，然而應知，在其他實施例中，第一通孔122A與第二通孔122B可在寬度上具有任意變化量。根據實施例，第二通孔122B在寬度上具有比第一通孔122A多的變化。
在圖9中，通過粘著劑126將積體電路晶粒124粘著到介電層112。如圖9所示，在封裝區600中粘著一個積體電路晶粒124。在其他實施例中，可在每一區中粘著多個積體電路晶粒124。積體電路晶粒124可為裸晶粒，例如邏輯晶粒（例如，中央處理器（central processing unit）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電力管理晶粒（例如，電力管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、信號處理晶粒（例如，數位信號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，模擬前端（analog front-end，AFE）晶粒）等或其組合。此外，在一些實施例中，積體電路晶粒124在不同封裝區（圖中未示出）中可為不同大小（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒124可為相同大小（例如，相同高度及/或表面積）。
在粘著到介電層112之前，可根據適用于在積體電路晶粒124中形成積體電路的製造製程來加工積體電路晶粒124。舉例來說，積體電路晶粒124各自包括半導體基板128，例如經摻雜的或未經摻雜的矽、或絕緣體上半導體（semiconductor-on-insulator，SOI）基板的有源層。半導體基板可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其組合。也可使用例如多層式基板（multi-layered substrate）或梯度基板（gradient substrate）等其他基板。可在半導體基板128中及/或半導體基板128上形成例如電晶體、二極體、電容器、電阻器等裝置且可通過由例如位於半導體基板128上的一個或多個介電層中的金屬化圖案所形成的內連線結構130將各所述裝置進行內連以形成積體電路。
積體電路晶粒124還包括與外部連接的接墊132（例如，鋁接墊）。接墊132位於可被稱作積體電路晶粒124的相應有源側的部位上。鈍化膜（passivation film）134位於積體電路晶粒124上及接墊132的一些部分上。開口穿過鈍化膜134到達接墊132。例如導電柱（例如，包含例如銅等金屬）等晶粒連接件136位於穿過鈍化膜134的開口中，並且機械地耦合到且電耦合到相應接墊132。可通過例如鍍覆等來形成晶粒連接件136。晶粒連接件136對積體電路晶粒124的相應積體電路進行電耦合。
介電材料138位於積體電路晶粒124的有源側上，例如位於鈍化膜134及晶粒連接件136上。介電材料138在側向上包封晶粒連接件136，且介電材料138在側向上與相應積體電路晶粒124相接。可首先將介電材料138形成為掩埋或覆蓋晶粒連接件136；當晶粒連接件136被掩埋時，介電材料138的頂表面可具有不均勻拓撲（topology）。介電材料138可為聚合物（例如聚苯並惡唑、聚醯亞胺、苯並環丁烯等）、氮化物（例如氮化矽等），氧化物（例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）、類似材料、或其組合，且可例如通過旋轉塗布、疊層、化學氣相沉積等來形成。
粘著劑126位於積體電路晶粒124的背側上並將積體電路晶粒124粘著到背側重佈線結構116（例如圖中的介電層112）。粘著劑126可為任何適合的粘著劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。粘著劑126可被塗覆到積體電路晶粒124的背側，例如塗覆到相應半導體晶片的背側或者可鍍覆在載體基板100的表面之上。可例如通過鋸切（sawing）或切割（dicing）而將積體電路晶粒124單體化，並使用例如拾取及放置工具（pick-and-place tool）通過粘著劑126而將積體電路晶粒124粘著到介電層112。
儘管以上將積體電路晶粒124說明及闡述為裸晶粒（例如，未經封裝晶粒），然而在其他實施例中，積體電路晶粒124可為經封裝晶片（例如，與例如重佈線結構、無源裝置等其他封裝特徵集成在一起的一個或多個裸晶粒）。舉例來說，積體電路晶粒124可為包括多個經堆疊且經內連記憶體晶粒的記憶體封裝（例如，混合記憶體立方（hybrid memory cube））。
在圖10中，在各種元件上形成包封體（encapsulant）140。包封體140可為模塑化合物、環氧樹脂等，且可通過壓縮模塑（compression molding）、傳遞模塑（transfer molding）等來塗覆。包封體140可形成在載體基板100之上，從而隱埋或覆蓋積體電路晶粒124的晶粒連接件136及/或穿孔122。接著將包封體140固化。
在圖11中，對包封體140執行平坦化製程（planarization process）以暴露出穿孔122及晶粒連接件136。所述平坦化製程也可對介電材料138進行研磨。在平坦化製程之後，穿孔122的頂表面、晶粒連接件136的頂表面、介電材料138的頂表面、及包封體140的頂表面是共面的（coplanar）。平坦化製程可為例如化學機械拋光（chemical-mechanical polish，CMP）、研磨製程（grinding process）等。在一些實施例中，例如如果已暴露出穿孔122及晶粒連接件136，則可省略所述平坦化。如上所述，第二通孔122B延伸穿過金屬化圖案108。這樣一來，在平坦化製程之後，當第一通孔122A及第二通孔122B連接到背側重佈線結構116的同一金屬化層時，第二通孔122B比第一通孔122A長。
在圖12中，在包封體140、穿孔122、及晶粒連接件136上形成前側重佈線結構（front-side redistribution structure）142。前側重佈線結構142包括多個介電層及金屬化圖案。舉例來說，前側重佈線結構142可被圖案化成通過相應一個或多個介電層而彼此隔開的多個分立的金屬化圖案。
在一些實施例中，介電層是由聚合物形成，所述聚合物可為例如聚苯並惡唑、聚醯亞胺、苯並環丁烯等可使用光罩進行圖案化的感光性材料。在其他實施例中，介電層是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可通過旋轉塗布、疊層、化學氣相沉積等或其組合來形成介電層。
在形成之後，將介電層圖案化以暴露出下伏導電特徵。將底部介電層圖案化以暴露出穿孔122的一些部分及晶粒連接件136的一些部分，且將一個或多個中間介電層圖案化以暴露出下伏金屬化圖案的一些部分。可通過可接受的製程來進行所述圖案化，例如當介電層為感光性材料時通過將所述介電層暴露至光來進行所述圖案化，或者通過使用例如各向異性蝕刻進行蝕刻來進行所述圖案化。如果介電層為感光性材料，則所述介電層可在曝光之後顯影。
在每一介電層上形成具有通孔的金屬化圖案。在介電層之上及穿過所述介電層的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等沉積製程來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布等來形成光阻並可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露部分上形成導電材料。可通過例如電鍍或無電鍍覆等鍍覆製程來形成所述導電材料。所述導電材料可包括金屬或金屬合金，例如銅、鈦、鎢、鋁等或其組合。接著，移除光阻以及晶種層的上面未形成有導電材料的一些部分。可通過例如使用氧等離子體等的可接受灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）來移除晶種層的被暴露部分。晶種層的其餘部分與導電材料形成前側重佈線結構142的一個金屬化層階的金屬化圖案及通孔。
示出前側重佈線結構142作為實例。可在前側重佈線結構142中形成比所示出的更多或更少的介電層及金屬化圖案。所屬領域中的普通技術人員將易於理解，哪些步驟及製程將被省略或重複進行以形成更多或更少的介電層及金屬化圖案。
將前側重佈線結構142的頂部介電層圖案化以暴露出金屬化圖案的一些部分從而形成導電接墊。導電接墊用於耦合到導電連接件，且可被稱作凸塊下金屬（under bump metallurgy，UBM）144。可通過可接受的製程來進行所述圖案化，例如當頂部介電層為感光性材料時通過將所述頂部介電層暴露至光來進行所述圖案化，或者通過使用例如各向異性蝕刻進行蝕刻來進行所述圖案化。如果頂部介電層為感光性材料，則所述頂部介電層可在曝光之後顯影。接著在前側重佈線結構142的外側（exterior side）上形成凸塊下金屬144。凸塊下金屬144被形成為延伸穿過頂部介電層中的開口以接觸前側重佈線結構142的金屬化層。
作為形成凸塊下金屬144的實例，在頂部介電層之上以及穿過所述頂部介電層的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等沉積製程來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布等來形成光阻並可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於前側重佈線結構142中的導電接墊的圖案。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露部分上形成導電材料。可通過例如電鍍或無電鍍覆等鍍覆製程來形成所述導電材料。所述導電材料可包括金屬或金屬合金，例如銅、鈦、鎢、鋁等或其組合。接著，移除光阻以及晶種層的上面未形成有導電材料的一些部分。可通過例如使用氧等離子體等的可接受灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）來移除晶種層的被暴露部分。晶種層的其餘部分與導電材料形成凸塊下金屬144。
在凸塊下金屬144上形成導電連接件146。導電連接件146可為球柵陣列封裝連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件146可由金屬或金屬合金形成，所述金屬或金屬合金例如為焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中，通過首先使用例如蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等常用方法形成焊料層來形成導電連接件146。一旦已在結構上形成焊料層，則可執行回焊以便將所述材料造型成所期望凸塊形狀。在另一實施例中，導電連接件146為通過濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積等而形成的金屬柱（例如銅柱）。所述金屬柱可不具有焊料且具有實質上垂直的側壁。在一些實施例中，在凸塊下金屬144的頂部上形成金屬頂蓋層（metal cap layer）（圖中未示出）。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可通過鍍覆製程來形成。
在圖13中，執行載體基板剝離（carrier substrate de-bonding）以將載體基板100從背側重佈線結構116（例如，介電層104）脫離（剝離）。根據一些實施例，所述剝離包括將例如雷射或紫外光等光投射在釋放層102上以使得釋放層102在光的熱量下分解，且載體基板100可被移除。接著將所述結構翻轉並放置在膠帶148上。
進一步在圖13中，形成穿過介電層104的開口150以暴露出金屬化圖案108的一些部分。可例如使用雷射鑽孔（laser drilling）、可接受的蝕刻技術等來形成所述開口。形成暴露出第一重佈線108A的第一開口150A，且形成暴露出第二重佈線108B的第二開口150B。第一開口150A被形成為相對于第一通孔122A的中心偏置，使得第一開口150A設置成與介電層112中的第一通孔122A的一些部分相距距離DO 。第二開口150B形成在第二通孔122B的中心下方，使得暴露出延伸穿過第二重佈線108B的晶種層118以及晶種層106的一些部分。
在圖14中，將被開口150暴露出的晶種層106及118的一些部分薄化或完全移除。可通過可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）將晶種層106及118的所述被暴露部分薄化或移除。在其中晶種層106及118包括多個層的實施例中，蝕刻製程可移除被暴露的多個層中的一些層或所有層。在其中晶種層106及118包括位於介電層104之上的鈦層及位於所述鈦層之上的銅層的實施例中，蝕刻製程可移除所述鈦層且使所述銅層保持原樣，由此將所述層薄化。在此種實施例中，使用對於鈦層來說具有選擇性的一種或多種蝕刻劑（例如，以比蝕刻所述銅層的速率實質上更高的速率蝕刻所述鈦層的蝕刻劑）來執行蝕刻製程。在其他實施例中，完全移除晶種層106及118的被暴露部分（例如，移除所有層）。
圖15至圖18是根據一些實施例的形成封裝結構400的製程期間各中間步驟的各種圖。圖15至圖18是剖視圖。封裝結構400可指代疊層封裝（PoP）結構。
在圖15中，將裝置封裝300結合到裝置封裝200。可在每一封裝區600中將裝置封裝300結合到裝置封裝200。裝置封裝300包括基板302及耦合到基板302的一個或多個堆疊晶粒308（308A及308B）。儘管例示出單個晶粒堆疊308（308A及308B），然而在其他實施例中，可並排地設置與基板302的同一表面耦合的多個堆疊晶粒308（各自具有一個或多個堆疊晶粒）。
基板302可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，也可使用化合物材料，例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些的組合等。另外，基板302可為絕緣體上矽（silicon-on-insulator，SOI）基板。通常，絕緣體上矽基板包括一層半導體材料，例如外延矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺（silicon germanium on insulator，SGOI）、或其組合。在一個替代性實施例中，基板302是基於絕緣核，例如玻璃纖維強化樹脂核（fiberglass reinforced resin core）。一種示例性核材料是玻璃纖維樹脂，例如FR4。所述核材料的替代方案包括雙馬來醯亞胺-三嗪（bismaleimide-triazine，BT）樹脂，或作為另一選擇，包括其他印刷電路板（PCB）材料或膜。可對基板302使用例如味之素增層膜（Ajinomoto build-up film，ABF）等的增層膜或其他疊層體。
基板302可包括有源裝置及/或無源裝置（圖中未示出）。如所屬領域中的普通技術人員應意識到，可使用各種各樣的裝置（例如電晶體、電容器、電阻器、這些的組合等）來產生裝置封裝300的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
基板302還可包括金屬化層（圖中未示出）及穿孔306。所述金屬化層可形成在有源裝置及無源裝置之上且被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料（low-k dielectric material））層與導電材料（例如，銅）層形成且可通過任何適合的製程（例如，沉積、鑲嵌（damascene）、雙重鑲嵌（dual damascene）等）來形成，其中通孔對各所述導電材料層進行內連。在一些實施例中，基板302實質上不具有有源裝置及無源裝置。
基板302可具有位於基板302的第一側上以耦合到堆疊晶粒308的接墊303以及位於基板302的第二側上以耦合到導電連接件314的接墊304，所述第二側與基板302的第一側相對。在一些實施例中，接墊303及304是通過向基板302的第一側及第二側上的介電層（圖中未示出）中形成凹槽（圖中未示出）而形成。所述凹槽可被形成為容許接墊303及304被嵌入到所述介電層中。在其他實施例中，由於接墊303及304可形成在所述介電層上，因而所述凹槽被省略。在一些實施例中，接墊303及304包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層（圖中未示出）。可在所述薄晶種層之上沉積接墊303及304的導電材料。可通過電化學鍍覆製程（electro-chemical plating process）、無電鍍覆製程、化學氣相沉積、原子層沉積（atomic layer deposition，ALD）、物理氣相沉積等或其組合來形成導電材料。接墊303及304的導電材料可為銅、鎢、鋁、銀、金、鎳等或其組合。
在實施例中，接墊304及304為包括三個導電材料層的凸塊下金屬，所述三個導電材料層例如為鈦層、銅層、及鎳層。舉例來說，接墊304可包括鈦層（圖中未示出）、主體銅部分304A、及鎳表面處理（nickel finish）304B。鎳表面處理304B可提高裝置封裝300的貨架壽命（shelf life），此在裝置封裝300為例如DRAM模組等記憶體裝置時可格外有利。然而，所屬領域中的普通技術人員應意識到尚有許多適合於形成凸塊下金屬303及304的適合的材料與層的排列方式，例如鉻/鉻-銅合金/銅/金的排列方式、鈦/鈦鎢/銅的排列方式、或銅/鎳/金的排列方式。可用於凸塊下金屬304及304的任何適合的材料或材料層完全旨在包含於當前申請的範圍內。在一些實施例中，穿孔306延伸穿過基板302且將至少一個接墊303耦合到至少一個接墊304。
在所說明實施例中，儘管可使用例如導電凸塊等其他連接方式，然而堆疊晶粒308是通過導線結合件（wire bond）310而耦合到基板302。在實施例中，堆疊晶粒308是堆疊記憶體晶粒。舉例來說，堆疊記憶體晶粒308可包括低功率（low-power，LP）雙倍數據速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4、或類似的記憶體模組。如上所述，在此種實施例中，接墊304可具有鎳表面處理304B。
在一些實施例中，可通過模塑材料312來包封堆疊晶粒308及導線結合件310。可例如使用壓縮模塑在堆疊晶粒308及導線結合件310上模塑出模塑材料312。在一些實施例中，模塑材料312是模塑化合物、聚合物、環氧樹脂、氧化矽填充膠材料等或其組合。可執行固化步驟以將模塑材料312固化，其中所述固化可為熱固化、紫外光固化等或其組合。
在一些實施例中，將堆疊晶粒308及導線結合件310掩埋在模塑材料312中，且在模塑材料312被固化之後，執行平坦化步驟（例如研磨），以移除模塑材料312的過量部分並為裝置封裝300提供實質上平坦的表面。
在形成裝置封裝300之後，通過導電連接件314、接墊304及金屬化圖案108將裝置封裝300機械地結合到且電結合到裝置封裝200。在一些實施例中，通過導線結合件310、接墊303及304、穿孔306、導電連接件314、穿孔122、前側重佈線結構142將堆疊記憶體晶粒308耦合到積體電路晶粒124。
儘管導電連接件314與導電連接件146無需相同，然而導電連接件314可相似於上述導電連接件146且本文中不再對其予以贅述。導電連接件314可設置在基板302的與堆疊記憶體晶粒308相對的側上。在一些實施例中，還可在基板302的與堆疊記憶體晶粒308相對的所述側上形成阻焊劑（solder resist）（圖中未示出）。可在阻焊劑（圖中未示出）中的開口中將導電連接件314設置成電耦合到且機械地耦合到基板302中的導電特徵（例如，接墊304）。阻焊劑可用於保護基板302的各區域免受外部損壞影響。
在一些實施例中，在對導電連接件314進行結合之前，使用例如免清洗焊劑（no-clean flux）等焊劑（圖中未示出）來塗布導電連接件314。可將導電連接件314浸入焊劑中，或可將所述焊劑噴射到導電連接件314上。在另一實施例中，可將焊劑塗覆到金屬化圖案108的表面。
在一些實施例中，導電連接件314上可在其被回焊之前先形成有可選的環氧樹脂焊劑（圖中未示出），其中所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分在裝置封裝300貼合到裝置封裝200之後被保留。此保留的環氧樹脂部分可充當底部填充膠（underfill），以減小因對導電連接件314進行回焊而產生的應力並保護因對導電連接件314進行回焊而產生的接頭（joint）。
可選地，可在裝置封裝200與300之間形成底部填充膠材料316。在實施例中，底部填充膠材料316是用於減緩運行及環境劣化（例如，因運行期間的產熱而造成的應力）對裝置封裝200及300的影響且支撐裝置封裝200及300的保護性材料。底部填充膠材料316可被注射到裝置封裝200與300之間的空間中或以另一種方式形成在所述空間中，且底部填充膠材料316可例如為分配在裝置封裝200與300之間且被接著固化而變硬的液態環氧樹脂。
圖16A、圖16B、圖16C、及圖16D是在執行結合製程以將裝置封裝200與300實體地耦合且電耦合之後導電連接件314及金屬化圖案108的細節圖。裝置封裝200與300之間的結合可為焊料結合。在實施例中，通過回焊製程將裝置封裝300結合到裝置封裝200。圖16A及圖16B分別為示出第一重佈線108A的連接的剖視圖及平面圖。圖16C及圖16D分別為示出第二重佈線108B的連接的剖視圖及平面圖。
在圖16A、圖16B、圖16C、及圖16D中，執行結合製程以將導電連接件314回焊成接觸接墊304及金屬化圖案108。在結合製程之後，在金屬化圖案108與導電連接件314的介面處可形成金屬間化合物（IMC）318。由於晶種層106及118的被暴露部分被局部移除或完全移除，因此金屬間化合物318可局部地或完全地延伸穿過金屬化圖案108。金屬間化合物318還可相對於第一開口150A的側在側向上沿金屬化圖案108延伸距離DI 。
通過結合製程形成的結合件包括與兩種不同金屬接觸的導電連接件314（例如，焊料）。在實施例中，金屬化圖案108是由銅形成，且接墊304具有鎳表面處理304B，從而形成鎳-焊料-銅連接。當形成有此種連接時，在回焊期間銅會從金屬化圖案108擴散到導電連接件314中並朝鎳表面處理304B擴散。在導電連接件314中在實箭頭所示方向上會形成銅擴散梯度。過量的銅從金屬化圖案108擴散到接近晶種層118可能會使晶種層118從金屬化圖案108層離。具體來說，銅從位於晶種層118與介電層104之間的金屬化圖案108的一些部分擴散可能會使晶種層118層離。
在圖16A及圖16B中，將介電層104中的第一開口150A設置成在側向上與介電層112中的第一通孔122A的一些部分相距距離DO 。這樣一來，導電連接件314被設置成在平面圖中在側向上與第一通孔122A的側相距距離DO ，且不沿第一通孔122A的縱向軸線設置。距離DO 被選擇成足夠大以使得金屬間化合物318A不在側向上延伸到第一通孔122A的側。換句話說，距離DO 比距離DI 大，且可為距離DI 的至少兩倍大。在實施例中，距離DI 可介於約2微米（µm）至約13 µm範圍內（例如，為約13 µm），且距離DO 可介於約25 µm至約35 µm範圍內（例如，為約35 µm）。將第一開口150A（參見例如圖13）形成為使得金屬間化合物318A不在側向上延伸到第一通孔122A的側可避免銅從位於晶種層118與介電層104之間的第一重佈線108A的一些部分擴散，從而避免晶種層118層離。
在圖16C及圖16D中，將介電層104中的第二開口150B設置成在側向上對齊第二重佈線108B中的間隙110。這樣一來，在平面圖中導電連接件314在側向上不與第二通孔122B的側間隔開，且沿第二通孔122B的縱向軸線設置。由於晶種層106及118的被暴露部分被局部移除或完全移除，因此金屬間化合物318B在縱向方向上延伸到第二通孔122B中。將金屬間化合物318B形成為延伸到第二通孔122B中可使一些銅從第二通孔122B而非從金屬化圖案108擴散出。此可減少從金屬化圖案108擴散的銅，從而避免晶種層118層離，並且還會避免第二重佈線108B的厚度減小。
如圖所示，金屬化圖案108還包括狹槽322，狹槽322設置在導電連接件314及穿孔122的周邊周圍。狹槽322提供應力緩和，從而提高電連接的可靠性。具體來說，狹槽322為金屬化圖案108提供額外的側壁，從而改善金屬化圖案108與例如介電層112等聚醯亞胺材料之間的粘著。狹槽322被設置成至少局部地圍繞第一重佈線108A中的導電連接件314，且可被設置成完全圍繞第二重佈線108B中的導電連接件314。
在圖17中，通過沿例如位於相鄰封裝區之間的切割道區（scribe line region）進行單體化來執行單體化製程（singulation process）320。在一些實施例中，單體化製程320包括鋸切製程、雷射製程或其組合。單體化製程320將封裝區600從相鄰封裝區（圖中未示出）單體化。示出在單體化之後的所得封裝結構400，所得封裝結構400可來自于封裝區600。
圖18示出貼合到基板500之後的封裝結構400。可將基板500稱為封裝基板500。通過使用導電連接件146將裝置封裝200安裝到基板500而將封裝結構400貼合到基板500。
封裝基板500可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇，也可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合等化合物材料。另外，封裝基板500可為絕緣體上矽基板。一般來說，絕緣體上矽基板包括例如外延矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺、或其組合等半導體材料的層。在一個替代性實施例中，封裝基板500是基於絕緣核，例如玻璃纖維強化樹脂核。一種示例性核材料是玻璃纖維樹脂，例如FR4。核材料的替代方案包括雙馬來醯亞胺-三嗪BT樹脂，或作為另外一種選擇，包括其他印刷電路板材料或膜。可對封裝基板500使用例如味之素增層膜等增層膜或其他疊層體。
封裝基板500可包括有源裝置及無源裝置（圖中未示出）。如所屬領域中的普通技術人員應意識到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生封裝結構400的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
封裝基板500也可包括金屬化層及通孔（圖中未示出）以及位於所述金屬化層及通孔之上的接墊502。所述金屬化層可形成在有源裝置及無源裝置之上且被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料）層與導電材料（例如，銅）層形成且可通過任何適合的製程（例如，沉積、鑲嵌、雙重鑲嵌等）來形成，其中通孔對各所述導電材料層進行內連。在一些實施例中，封裝基板500實質上不具有有源裝置及無源裝置。
在一些實施例中，可對導電連接件146進行回焊以將裝置封裝200貼合到接墊502。導電連接件146將封裝基板500（包括位於封裝基板500中的金屬化層）電耦合到及/或實體地耦合到裝置封裝200。在一些實施例中，可在安裝在封裝基板500上之前將無源裝置（例如，表面安裝裝置（surface mount device，SMD）（圖中未例示））貼合到裝置封裝200（例如，結合到接墊502）。在此種實施例中，可將無源裝置結合到裝置封裝200的與導電連接件146相同的表面。
導電連接件146，導電連接件146上可在其被回焊之前先形成有環氧樹脂焊劑（圖中未示出），所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分會在將裝置封裝200貼合到封裝基板500之後被保留。此保留的環氧樹脂部分可充當底部填充膠，以減小因對導電連接件146進行回焊而產生的應力並保護因對導電連接件314進行回焊而產生的接頭。在一些實施例中，可在裝置封裝200與封裝基板500之間形成環繞導電連接件146的底部填充膠（圖中未示出）。可在貼合裝置封裝200之後通過毛細管流動製程（capillary flow process）而形成所述底部填充膠，或可在貼合裝置封裝200之前通過適合的沉積方法而形成所述底部填充膠。
各實施例可實現多個優點。將導電連接件314設置成在平面圖中在側向上與第一通孔122A的側相距足夠的距離DO 可避免銅從金屬化圖案108擴散到接近晶種層118。將金屬間化合物318B形成為延伸到第二通孔122B中可使一些銅從第二通孔122B而非從金屬化圖案108擴散出。減少從位於晶種層118下方的金屬化圖案108擴散的銅的量可避免晶種層118層離，從而提高所得裝置的可靠性。
根據一些實施例，一種裝置包括第一裝置封裝，所述第一裝置封裝包括：第一重佈線結構，包括第一重佈線及第二重佈線；晶粒，位於第一重佈線結構上；第一通孔，耦合到第一重佈線的第一側；第二通孔，耦合到第二重佈線的第一側且延伸穿過所述第二重佈線；包封體，環繞晶粒、第一通孔、及第二通孔；以及第二重佈線結構，位於包封體之上，所述第二重佈線結構電連接到晶粒、第一通孔、及第二通孔。所述裝置還包括：第一導電連接件，耦合到第一重佈線的第二側，所述第一導電連接件沿與第一通孔的縱向軸線不同的軸線設置；以及第二導電連接件，耦合到第二重佈線的第二側，所述第二導電連接件沿第二通孔的縱向軸線設置。
在一些實施例中，所述裝置還包括：第二裝置封裝，包括第一接墊及第二接墊，第一導電連接件耦合到所述第一接墊，第二導電連接件耦合到所述第二接墊。在一些實施例中，第一接墊及第二接墊具有鎳表面處理。在一些實施例中，第一重佈線及第二重佈線是由銅形成。在一些實施例中，第一重佈線結構還包括：第一介電層，第一重佈線及第二重佈線設置在所述第一介電層上；以及第二介電層，位於第一介電層上。在一些實施例中，第二通孔比第一通孔長。
根據一些實施例，一種方法包括形成第一重佈線結構，所述形成第一重佈線結構包括：在載體基板之上沉積第一介電層；在第一介電層上形成第一導電特徵；在第一介電層上形成第二導電特徵；在第一介電層上形成第三導電特徵；以及在第一導電特徵、第二導電特徵、及第三導電特徵上沉積第二介電層。所述方法還包括：在第一導電特徵上形成第一通孔；在第二導電特徵上、第三導電特徵上、以及所述第二導電特徵與所述第三導電特徵之間形成第二通孔；將晶粒貼合到鄰近第一通孔及第二通孔的第一重佈線結構；使用包封體包封晶粒、第一通孔、及第二通孔；將包封體、第一通孔、及第二通孔平坦化；以及在包封體、第一通孔、第二通孔、及晶粒之上形成第二重佈線結構。
在一些實施例中，所述方法還包括：將載體基板從第一重佈線結構剝離；以及將裝置封裝貼合到第一重佈線結構，所述裝置封裝通過第一連接件貼合到第一導電特徵，所述裝置封裝通過第二連接件貼合到第二導電特徵及第三導電特徵。在一些實施例中，第一連接件不沿第一通孔的縱向軸線設置。在一些實施例中，第二連接件沿第二通孔的縱向軸線設置。在一些實施例中，在平坦化之後，第一通孔比第二通孔長。
根據一些實施例，一種方法包括：在第一介電層上沉積第一晶種層；在第一晶種層上鍍覆第一導電特徵及第二導電特徵；在第一導電特徵及第二導電特徵上沉積第二介電層；在第二介電層中形成第一開口，所述第一開口暴露出第一導電特徵、第二導電特徵、及第一介電層；在第二介電層上及第一開口中沉積第二晶種層；在第一開口中從第二晶種層的一些部分鍍覆第一通孔；將晶粒貼合到第二介電層；以及使用包封體包封第一通孔及晶粒。
在一些實施例中，所述方法還包括：在第一介電層中形成第二開口，所述第二開口暴露出第一晶種層及第二晶種層；對所述第一晶種層的被暴露部分及所述第二晶種層的被暴露部分進行刻蝕，以移除所述第一晶種層的至少一部分及所述第二晶種層的至少一部分；在第二開口中形成能夠回焊的材料，所述能夠回焊的材料沿第一通孔的縱向軸線設置；以及對能夠回焊的材料進行回焊，以從所述能夠回焊的材料以及第一晶種層的導電材料、第二晶種層的導電材料、及第一通孔的導電材料形成金屬間化合物。在一些實施例中，所述方法還包括：使用能夠回焊的材料將裝置封裝貼合到第一導電特徵及第二導電特徵。在一些實施例中，對能夠回焊的材料進行回焊包括將第一通孔的導電材料的一些部分擴散到所述能夠回焊的材料中。在一些實施例中，所述方法還包括：在第一介電層上形成第三導電特徵；在第三導電特徵上沉積第二介電層；在第二介電層中形成第二開口，所述第二開口暴露出第三導電特徵；在第二開口中沉積第二晶種層；以及在第二開口中從第二晶種層的一些部分鍍覆第二通孔。在一些實施例中，所述方法還包括：在第一介電層中形成第三開口，所述第三開口暴露出第一晶種層；對所述第一晶種層的被暴露部分進行刻蝕，以移除所述第一晶種層的至少一部分；在第三開口中形成能夠回焊的材料，所述能夠回焊的材料沿與第二通孔的縱向軸線不同的軸線設置；以及對能夠回焊的材料進行回焊，以從所述能夠回焊的材料以及第一晶種層的導電材料形成金屬間化合物。在一些實施例中，對能夠回焊的材料進行回焊包括將第三導電特徵的導電材料的一些部分擴散到所述能夠回焊的材料中。在一些實施例中，在第二通孔與第一介電層之間不形成任何部分的金屬間化合物。在一些實施例中，所述方法還包括：將第一通孔、第二通孔、及包封體平坦化，在所述平坦化之後，所述第一通孔比所述第二通孔長。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧載體基板
102‧‧‧釋放層
104、112‧‧‧介電層
106、118‧‧‧晶種層
108‧‧‧金屬化圖案
108A‧‧‧第一重佈線
108B‧‧‧第二重佈線
110‧‧‧間隙
114A、150A‧‧‧第一開口
114B、150B‧‧‧第二開口
116‧‧‧背側重佈線結構
120‧‧‧光阻
122、306‧‧‧穿孔
122A‧‧‧第一通孔
122B‧‧‧第二通孔
124‧‧‧積體電路晶粒
126‧‧‧粘著劑
128‧‧‧半導體基板
130‧‧‧內連線結構
132‧‧‧接墊
134‧‧‧鈍化膜
136‧‧‧晶粒連接件
138‧‧‧介電材料
140‧‧‧包封體
142‧‧‧前側重佈線結構
144‧‧‧凸塊下金屬
146‧‧‧導電連接件
148‧‧‧膠帶
150‧‧‧開口
200、300‧‧‧裝置封裝
302‧‧‧基板
303、502‧‧‧接墊
304A‧‧‧主體銅部分
304B‧‧‧鎳表面處理
308A、308B‧‧‧堆疊晶粒
310‧‧‧導線結合件
312‧‧‧模塑材料
314‧‧‧導電連接件
316‧‧‧底部填充膠材料
318A、318B‧‧‧金屬間化合物
320‧‧‧單體化製程
322‧‧‧狹槽
400‧‧‧封裝結構
500‧‧‧基板/封裝基板
600‧‧‧封裝區
DI、DO‧‧‧距離
WA、WG、WO、WP‧‧‧寬度
WB‧‧‧組合寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個樣態。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖14是根據一些實施例的形成裝置封裝的製程期間各中間步驟的各種圖。 圖15至圖18是根據一些實施例的形成封裝結構的製程期間各中間步驟的各種圖。

Claims (20)

  1. 一種裝置，包括： 第一裝置封裝，包括： 第一重佈線結構，包括第一重佈線及第二重佈線； 晶粒，位於所述第一重佈線結構上； 第一通孔，耦合到所述第一重佈線的第一側； 第二通孔，耦合到所述第二重佈線的第一側且延伸穿過所述第二重佈線； 包封體，環繞所述晶粒、所述第一通孔、及所述第二通孔；以及 第二重佈線結構，位於所述包封體之上，所述第二重佈線結構電連接到所述晶粒、所述第一通孔、及所述第二通孔； 第一導電連接件，耦合到所述第一重佈線的第二側，所述第一導電連接件沿與所述第一通孔的縱向軸線不同的軸線設置；以及 第二導電連接件，耦合到所述第二重佈線的第二側，所述第二導電連接件沿所述第二通孔的縱向軸線設置。
  2. 如申請專利範圍第1項所述的裝置，還包括: 第二裝置封裝，包括第一接墊及第二接墊，所述第一導電連接件耦合到所述第一接墊，所述第二導電連接件耦合到所述第二接墊。
  3. 如申請專利範圍第2項所述的裝置，所述第一接墊及所述第二接墊具有鎳表面處理。
  4. 如申請專利範圍第2項所述的裝置，所述第一重佈線及所述第二重佈線是由銅形成。
  5. 如申請專利範圍第1項所述的裝置，所述第一重佈線結構還包括： 第一介電層，所述第一重佈線及所述第二重佈線設置在所述第一介電層上；以及 第二介電層，位於所述第一介電層上。
  6. 如申請專利範圍第5項所述的裝置，所述第二通孔比所述第一通孔長。
  7. 一種方法，包括： 形成第一重佈線結構，包括： 在載體基板之上沉積第一介電層； 在所述第一介電層上形成第一導電特徵； 在所述第一介電層上形成第二導電特徵； 在所述第一介電層上形成第三導電特徵；以及 在所述第一導電特徵、所述第二導電特徵、及所述第三導電特徵上沉積第二介電層； 在所述第一導電特徵上形成第一通孔； 在所述第二導電特徵上、所述第三導電特徵上、以及所述第二導電特徵與所述第三導電特徵之間形成第二通孔； 將晶粒貼合到鄰近所述第一通孔及所述第二通孔的所述第一重佈線結構； 使用包封體包封所述晶粒、所述第一通孔、及所述第二通孔； 將所述包封體、所述第一通孔、及所述第二通孔平坦化；以及 在所述包封體、所述第一通孔、所述第二通孔、及所述晶粒之上形成第二重佈線結構。
  8. 如申請專利範圍第7項所述的方法，還包括： 將所述載體基板從所述第一重佈線結構剝離；以及 將裝置封裝貼合到所述第一重佈線結構，所述裝置封裝通過第一連接件貼合到所述第一導電特徵，所述裝置封裝通過第二連接件貼合到所述第二導電特徵及所述第三導電特徵。
  9. 如申請專利範圍第8項所述的方法，所述第一連接件不沿所述第一通孔的縱向軸線設置。
  10. 如申請專利範圍第8項所述的方法，所述第二連接件沿所述第二通孔的縱向軸線設置。
  11. 如申請專利範圍第7項所述的方法，在所述平坦化之後，所述第一通孔比所述第二通孔長。
  12. 一種方法，包括： 在第一介電層上沉積第一晶種層； 在所述第一晶種層上鍍覆第一導電特徵及第二導電特徵； 在所述第一導電特徵及所述第二導電特徵上沉積第二介電層； 在所述第二介電層中形成第一開口，所述第一開口暴露出所述第一導電特徵、所述第二導電特徵、及所述第一介電層； 在所述第二介電層上及所述第一開口中沉積第二晶種層； 在所述第一開口中從所述第二晶種層的一些部分鍍覆第一通孔； 將晶粒貼合到所述第二介電層；以及 使用包封體包封所述第一通孔及所述晶粒。
  13. 如申請專利範圍第12項所述的方法，還包括： 在所述第一介電層中形成第二開口，所述第二開口暴露出所述第一晶種層及所述第二晶種層； 對所述第一晶種層的被暴露部分及所述第二晶種層的被暴露部分進行蝕刻，以移除所述第一晶種層的至少一部分及所述第二晶種層的至少一部分； 在所述第二開口中形成能夠回焊的材料，所述能夠回焊回焊的材料沿所述第一通孔的縱向軸線設置；以及 對所述能夠回焊的材料進行回焊，以從所述能夠回焊的材料以及所述第一晶種層的導電材料、所述第二晶種層的導電材料、及所述第一通孔的導電材料形成金屬間化合物。
  14. 如申請專利範圍第13項所述的方法，還包括： 使用所述能夠回焊的材料將裝置封裝貼合到所述第一導電特徵及所述第二導電特徵。
  15. 如申請專利範圍第13項所述的方法，對所述能夠回焊的材料進行回焊包括將所述第一通孔的所述導電材料的一些部分擴散到所述能夠回焊的材料中。
  16. 如申請專利範圍第12項所述的方法，還包括： 在所述第一介電層上形成第三導電特徵； 在所述第三導電特徵上沉積所述第二介電層； 在所述第二介電層中形成第二開口，所述第二開口暴露出所述第三導電特徵； 在所述第二開口中沉積所述第二晶種層；以及 在所述第二開口中從所述第二晶種層的一些部分鍍覆第二通孔。
  17. 如申請專利範圍第16項所述的方法，還包括： 在所述第一介電層中形成第三開口，所述第三開口暴露出所述第一晶種層； 對所述第一晶種層的被暴露部分進行蝕刻，以移除所述第一晶種層的至少一部分； 在所述第三開口中形成能夠回焊的材料，所述能夠回焊的材料沿與所述第二通孔的縱向軸線不同的軸線設置；以及 對所述能夠回焊的材料進行回焊，以從所述能夠回焊的材料以及所述第一晶種層的導電材料形成金屬間化合物。
  18. 如申請專利範圍第17項所述的方法，對所述能夠回焊的材料進行回焊包括將所述第三導電特徵的導電材料的一些部分擴散到所述能夠回焊的材料中。
  19. 如申請專利範圍第17項所述的方法，在所述第二通孔與所述第一介電層之間不形成任何部分的所述金屬間化合物。
  20. 如申請專利範圍第16項所述的方法，還包括： 將所述第一通孔、所述第二通孔、及所述包封體平坦化，在所述平坦化之後，所述第一通孔比所述第二通孔長。
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Publication number Priority date Publication date Assignee Title
US10658334B2 (en) * 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
EP3688801A4 (en) * 2017-09-28 2021-05-05 INTEL Corporation PACKAGE ON ACTIVE SILICON SEMICONDUCTOR HOUSING
US11177201B2 (en) * 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
TWI643307B (zh) * 2018-01-30 2018-12-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US10950519B2 (en) * 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11380620B2 (en) * 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11088079B2 (en) 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
KR102551352B1 (ko) 2019-06-28 2023-07-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US11239225B2 (en) * 2019-07-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structures and methods of manufacturing the same
KR20210015071A (ko) * 2019-07-31 2021-02-10 삼성전자주식회사 반도체 패키지
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US20210366852A1 (en) * 2020-05-25 2021-11-25 Nanya Technology Corporation Semiconductor structure and method of forming the same
US11574820B2 (en) * 2020-06-08 2023-02-07 Micron Technology, Inc. Semiconductor devices with flexible reinforcement structure
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11270975B2 (en) * 2020-07-21 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages including passive devices and methods of forming same
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
KR20220015193A (ko) * 2020-07-30 2022-02-08 삼성전자주식회사 반도체 패키지
KR20220036598A (ko) 2020-09-16 2022-03-23 삼성전자주식회사 반도체 패키지 장치
US11776820B2 (en) * 2020-09-30 2023-10-03 Huawei Technologies Co., Ltd. Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11756873B2 (en) * 2021-02-26 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11756870B2 (en) * 2021-04-29 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked via structure disposed on a conductive pillar of a semiconductor die
US11804445B2 (en) * 2021-04-29 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip package structure
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
KR20220161767A (ko) * 2021-05-31 2022-12-07 삼성전자주식회사 반도체 패키지 장치

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3989869B2 (ja) * 2003-04-14 2007-10-10 沖電気工業株式会社 半導体装置及びその製造方法
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8604614B2 (en) * 2010-03-26 2013-12-10 Samsung Electronics Co., Ltd. Semiconductor packages having warpage compensation
WO2011125277A1 (ja) 2010-04-07 2011-10-13 株式会社島津製作所 放射線検出器およびそれを製造する方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8354297B2 (en) * 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US20130186676A1 (en) * 2012-01-20 2013-07-25 Futurewei Technologies, Inc. Methods and Apparatus for a Substrate Core Layer
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
KR101561117B1 (ko) * 2012-09-20 2015-10-16 주식회사 케이티 무선랜 시스템에서 능동 검색 방법
US9343442B2 (en) 2012-09-20 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Passive devices in package-on-package structures and methods for forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9035461B2 (en) * 2013-01-30 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9553059B2 (en) * 2013-12-20 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Backside redistribution layer (RDL) structure
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9666522B2 (en) * 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9646918B2 (en) * 2014-08-14 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US10090241B2 (en) 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US9520372B1 (en) 2015-07-20 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package (WLP) and method for forming the same
US9786617B2 (en) * 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9620465B1 (en) * 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9997464B2 (en) * 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US10541226B2 (en) * 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US10134683B2 (en) * 2017-02-10 2018-11-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10510631B2 (en) * 2017-09-18 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fan out package structure and method of manufacturing the same

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US10971477B2 (en) 2021-04-06
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US10269773B1 (en) 2019-04-23
US20210225812A1 (en) 2021-07-22
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