JP2005276879A - 半導体装置及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】平面視矩形状のチップ実装領域の周囲に電極パッド4が形成されるとともに、チップ実装領域と電極パッド4の形成領域との間にダム5が設けられた実装基板1と、この実装基板5のチップ実装領域にフリップチップ実装された半導体チップ2と、実装基板1と半導体チップ2との間に充填されたアンダーフィル材6とを備える半導体装置の構成として、半導体装置の製造時にアンダーフィル材6が滴下されるチップ実装領域の所定の辺とこれに対応するダム5との間の距離を、チップ実装領域の他の辺とこれに対応するダム5との間の距離よりも長く設定する。
【選択図】図1
Description
Claims (7)
- 平面視矩形状のチップ実装領域の周囲に電極パッドが形成されるとともに、前記チップ実装領域と前記電極パッドの形成領域との間にダムが設けられた実装基板と、
前記実装基板の前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材とを備え、
前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間の距離が、前記チップ実装領域の他の辺と当該他の辺に対応する前記ダムとの間の距離よりも長い
ことを特徴とする半導体装置。 - 平面視矩形状のチップ実装領域の周囲に電極パッドが形成されるとともに、前記チップ実装領域と前記電極パッドの形成領域との間にダムが設けられた実装基板と、
前記実装基板の前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材とを備え、
前記チップ実装領域の所定の辺に対応する位置のみ、または前記所定の辺に対応する位置と当該所定の辺と直角をなす他の2つの辺に対応する位置にのみ、前記ダムを設けてなる
ことを特徴とする半導体装置。 - 前記所定の辺と当該所定の辺に対応する前記ダムとの間の距離が、前記所定の辺と直角をなす他の2つの辺と当該他の2つの辺に対応する前記ダムとの間の距離よりも長い
ことを特徴とする請求項2記載の半導体装置。 - 実装基板のチップ実装領域の周囲でかつ電極パッドの形成領域の内側にダムを形成する第1の工程と、
前記実装基板の前記チップ実装領域に半導体チップをフリップチップ実装する第2の工程と、
前記実装基板と前記半導体チップとの間にアンダーフィル材を充填する第3の工程とを有し、
前記第1の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間の距離が、前記チップ実装領域の他の辺と当該他の辺に対応する前記ダムとの間の距離よりも長くなるように前記ダムを形成し、
前記第3の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間に前記アンダーフィル材を滴下する
ことを特徴とする半導体装置の製造方法。 - 前記第1の工程においては、前記実装基板の前記チップ実装領域にバンプを形成するとともに、前記バンプと同時に前記ダムを形成する
ことを特徴とする請求項4記載の半導体装置の製造方法。 - 実装基板のチップ実装領域の周囲でかつ電極パッドの形成領域の内側にダムを形成する第1の工程と、
前記実装基板の前記チップ実装領域に半導体チップをフリップチップ実装する第2の工程と、
前記実装基板と前記半導体チップとの間にアンダーフィル材を充填する第3の工程とを有し、
前記第1の工程においては、前記チップ実装領域の所定の辺に対応する位置のみ、または前記所定の辺に対応する位置と当該所定の辺と直角をなす他の2つの辺に対応する位置にのみ、前記ダムを形成し、
前記第3の工程においては、前記チップ実装領域の所定の辺と当該所定の辺に対応する前記ダムとの間に前記アンダーフィル材を滴下する
ことを特徴とする半導体装置の製造方法。 - 前記第1の工程においては、前記実装基板の前記チップ実装領域にバンプを形成するとともに、前記バンプと同時に前記ダムを形成する
ことを特徴とする請求項6記載の半導体装置の製造方法。
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Cited By (25)
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KR100691443B1 (ko) | 2005-11-16 | 2007-03-09 | 삼성전기주식회사 | 플립칩 패키지 및 그 제조방법 |
JP2007103855A (ja) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | 半導体装置用基板および半導体装置 |
JP2007157963A (ja) * | 2005-12-05 | 2007-06-21 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
JP2007173361A (ja) * | 2005-12-20 | 2007-07-05 | Sony Corp | 半導体装置 |
JP2007207805A (ja) * | 2006-01-31 | 2007-08-16 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
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