JP2007173361A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2007173361A JP2007173361A JP2005366319A JP2005366319A JP2007173361A JP 2007173361 A JP2007173361 A JP 2007173361A JP 2005366319 A JP2005366319 A JP 2005366319A JP 2005366319 A JP2005366319 A JP 2005366319A JP 2007173361 A JP2007173361 A JP 2007173361A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】本発明の半導体装置20においては、実装基板1上のチップ実装領域とダム5との間の領域の一部にアンダーフィル材の滴下領域21が設けられており、この滴下領域21には、実装基板1と半導体チップ2との間へアンダーフィル材の注入を案内するガイド溝22が形成されている。この構成により、ガイド溝22の形成深さ及び形成範囲に応じた容積分だけアンダーフィル材6の受容量を高めることができるので、滴下されたアンダーフィル材6を半導体チップ2上に這い上がらせたり電極パッド4側に流出させることなく、実装基板1と半導体チップ2との間に適正に注入することが可能となる。また、実装基板1の外形サイズの更なる小型化にも対応することが可能となる。
【選択図】図2
Description
Claims (8)
- チップ実装領域の周囲に電極パッドが形成されるとともに、前記チップ実装領域と前記電極パッドの形成領域との間にダムが設けられた実装基板と、
前記実装基板のチップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材とを備えた半導体装置において、
前記実装基板上には、前記チップ実装領域と前記ダムとの間の領域の一部に前記アンダーフィル材の滴下領域が設けられており、
前記滴下領域には、前記実装基板と前記半導体チップとの間へ前記アンダーフィル材の注入を案内するガイド溝が形成されている
ことを特徴とする半導体装置。 - 前記ガイド溝は、前記チップ実装領域の外側から前記チップ実装領域の内側に亘って形成されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記ガイド溝は、前記チップ実装領域の内側に向かうにつれて深くなるように形成されている
ことを特徴とする請求項2に記載の半導体装置。 - 前記ガイド溝は、前記チップ実装領域の内側に向かうにつれて幅広となるように形成されている
ことを特徴とする請求項2に記載の半導体装置。 - 前記ガイド溝の最大形成幅は、前記半導体チップの一辺の長さに相当する大きさとされている
ことを特徴とする請求項4に記載の半導体装置。 - 前記滴下領域は、前記チップ実装領域の所定の辺と当該所定の辺に対向するダムとの間に設けられており、
前記チップ実装領域の所定の辺と当該所定の辺に対向する前記ダムとの間の距離は、前記チップ実装領域の他の辺と当該他の辺に対向する前記ダムとの間の距離よりも長く設定されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記ガイド溝は、前記実装基板の表面に形成された絶縁保護膜の一部を加工して形成されている
ことを特徴とする請求項1に記載の半導体装置。 - 前記実装基板は、半導体チップである
ことを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005366319A JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
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JP2005366319A JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007173361A true JP2007173361A (ja) | 2007-07-05 |
JP4760361B2 JP4760361B2 (ja) | 2011-08-31 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005366319A Expired - Fee Related JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207805A (ja) * | 2006-01-31 | 2007-08-16 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
KR20100085857A (ko) * | 2009-01-21 | 2010-07-29 | 소니 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
US7880301B2 (en) * | 2006-09-21 | 2011-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
KR20110119566A (ko) * | 2010-04-27 | 2011-11-02 | 스태츠 칩팩, 엘티디. | 반도체 소자 및 그 제조 방법 |
US8110933B2 (en) | 2006-12-26 | 2012-02-07 | Panasonic Corporation | Semiconductor device mounted structure and semiconductor device mounted method |
JP2013537365A (ja) * | 2010-09-09 | 2013-09-30 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | ポリマー充填剤溝を有する半導体チップデバイス |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
US11264354B2 (en) | 2019-10-08 | 2022-03-01 | Samsung Electronics Co., Ltd. | Wafer level package |
Citations (5)
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---|---|---|---|---|
JPH11214586A (ja) * | 1998-01-20 | 1999-08-06 | Murata Mfg Co Ltd | 電子回路装置 |
JP2001308115A (ja) * | 2000-04-20 | 2001-11-02 | Seiko Instruments Inc | 電子回路装置 |
WO2004114402A1 (ja) * | 2003-06-23 | 2004-12-29 | Shinko Electric Industries Co., Ltd. | 配線基板およびその製造方法、並びに配線基板への半導体チップの実装構造 |
JP2005175113A (ja) * | 2003-12-10 | 2005-06-30 | Fdk Corp | フリップチップ実装用プリント配線基板 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
-
2005
- 2005-12-20 JP JP2005366319A patent/JP4760361B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11214586A (ja) * | 1998-01-20 | 1999-08-06 | Murata Mfg Co Ltd | 電子回路装置 |
JP2001308115A (ja) * | 2000-04-20 | 2001-11-02 | Seiko Instruments Inc | 電子回路装置 |
WO2004114402A1 (ja) * | 2003-06-23 | 2004-12-29 | Shinko Electric Industries Co., Ltd. | 配線基板およびその製造方法、並びに配線基板への半導体チップの実装構造 |
JP2005175113A (ja) * | 2003-12-10 | 2005-06-30 | Fdk Corp | フリップチップ実装用プリント配線基板 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207805A (ja) * | 2006-01-31 | 2007-08-16 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
US7880301B2 (en) * | 2006-09-21 | 2011-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US8110933B2 (en) | 2006-12-26 | 2012-02-07 | Panasonic Corporation | Semiconductor device mounted structure and semiconductor device mounted method |
KR101634810B1 (ko) * | 2009-01-21 | 2016-06-29 | 소니 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
KR20100085857A (ko) * | 2009-01-21 | 2010-07-29 | 소니 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
JP2010192886A (ja) * | 2009-01-21 | 2010-09-02 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
US9425070B2 (en) | 2009-01-21 | 2016-08-23 | Sony Corporation | Semiconductor device and a method of manufacturing the same |
TWI458054B (zh) * | 2009-01-21 | 2014-10-21 | Sony Corp | 半導體裝置及半導體裝置之製造方法 |
KR101647853B1 (ko) * | 2010-04-27 | 2016-08-12 | 스태츠 칩팩 피티이. 엘티디. | 반도체 소자 및 그 제조 방법 |
KR20110119566A (ko) * | 2010-04-27 | 2011-11-02 | 스태츠 칩팩, 엘티디. | 반도체 소자 및 그 제조 방법 |
JP2013537365A (ja) * | 2010-09-09 | 2013-09-30 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | ポリマー充填剤溝を有する半導体チップデバイス |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
US11264354B2 (en) | 2019-10-08 | 2022-03-01 | Samsung Electronics Co., Ltd. | Wafer level package |
US11894338B2 (en) | 2019-10-08 | 2024-02-06 | Samsung Electronics Co., Ltd. | Wafer level package |
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