JP2007207805A - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/73201—Location after the connecting process on the same surface
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Abstract
【解決手段】本発明に係る半導体装置の製造方法は、第2の半導体チップ22の端子面の一部が第1の半導体チップ21の周縁21Eから露出するように第2の半導体チップ22を第1の半導体チップ21の上に実装する工程と、第1,第2の半導体チップ21,22の上下を反転する工程と、第2の半導体チップ22の露出した端子面にアンダーフィル材24を供給し、第1の半導体チップ21と第2の半導体チップ22との間にアンダーフィル材24を充填する工程とを有する。
【選択図】図1
Description
図1A〜Cは本発明の第1の実施の形態による半導体装置20の概略構成及び製造方法を示しており、Aは半導体装置20の平面図、Bはアンダーフィル充填工程を示す側断面図、Cは半導体装置20の側断面図である。
図2A〜Cは本発明の第2の実施の形態による半導体装置30の概略構成及び製造方法を示しており、Aは半導体装置30の平面図、Bはアンダーフィル充填工程を示す側断面図、Cは半導体装置30の側断面図である。
図3A〜Cに示した例では、第1の半導体チップ(ロジックチップ)21は縦の長さが8.0mm、横の長さが10.0mmであり、第2の半導体チップ(メモリチップ)22は縦の長さが6.5mm、横の長さが10.4mmである。第2の半導体チップ22を第1の半導体チップ21に対して、第1の半導体チップ21の一周縁21E側に1.5mmはみ出るようにして実装した。
図4A〜Cに示した例では、第1の半導体チップ(ロジックチップ)21は縦の長さが8.0mm、横の長さが11.0mmであり、第2の半導体チップ(メモリチップ)22は縦の長さが9.0mm、横の長さが9.0mmである。第2の半導体チップ22を第1の半導体チップ21に対して、第1の半導体チップ21の一周縁21E側に2.0mmはみ出るようにして実装した。
Claims (7)
- 第1の半導体チップの上に第2の半導体チップをフリップチップ実装した後、前記第1の半導体チップと前記第2の半導体チップとの間にアンダーフィル材を充填する工程を有する半導体装置の製造方法において、
前記第2の半導体チップの端子面の一部が前記第1の半導体チップの周縁から露出するように前記第2の半導体チップを前記第1の半導体チップの上に実装する工程と、
前記第1,第2の半導体チップの上下を反転する工程と、
前記第2の半導体チップの露出した端子面にアンダーフィル材を供給し、前記第1の半導体チップと前記第2の半導体チップとの間に前記アンダーフィル材を充填する工程とを有する
ことを特徴とする半導体装置の製造方法。 - 前記アンダーフィル材を充填する工程では、前記注入ノズルと対向する前記第1の半導体チップの周縁の一部に前記アンダーフィル材のフィレットを形成する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 第1の半導体チップの上に第2の半導体チップがフリップチップ実装され、前記第1,第2の半導体チップの間にアンダーフィル材が充填された半導体装置において、
前記第2の半導体チップは、その端子面の一部が前記第1の半導体チップの周縁から露出するように前記第1の半導体チップの上に実装されており、
前記第2の半導体チップの露出した端子面の一部が前記アンダーフィル材の供給領域とされている
ことを特徴とする半導体装置。 - 前記第1の半導体チップの周縁の一部には、前記アンダーフィル材のフィレットが形成されている
ことを特徴とする請求項3に記載の半導体装置。 - 前記第2の半導体チップの露出した端子面には、前記アンダーフィル材の流出防止用のダムが形成されている
ことを特徴とする請求項3に記載の半導体装置。 - 前記第1の半導体チップの下面には実装基板と接続される外部端子が形成されているとともに、前記第1の半導体チップには当該第1の半導体チップの上面と前記外部端子との間を連絡する層間接続部が形成されている
ことを特徴とする請求項3に記載の半導体装置。 - 前記第1の半導体チップはロジックチップであり、前記第2の半導体チップはメモリチップである
ことを特徴とする請求項3に記載の半導体装置。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
CN104517936A (zh) * | 2013-09-30 | 2015-04-15 | 联发科技股份有限公司 | 封装结构 |
US9093338B2 (en) | 2011-10-20 | 2015-07-28 | Panasonic Corporation | Semiconductor device having chip-on-chip structure |
CN105793979A (zh) * | 2013-12-27 | 2016-07-20 | 英特尔公司 | 光电子封装组件 |
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---|---|---|---|---|
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
US9093338B2 (en) | 2011-10-20 | 2015-07-28 | Panasonic Corporation | Semiconductor device having chip-on-chip structure |
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