JP2007157963A - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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- JP2007157963A JP2007157963A JP2005350191A JP2005350191A JP2007157963A JP 2007157963 A JP2007157963 A JP 2007157963A JP 2005350191 A JP2005350191 A JP 2005350191A JP 2005350191 A JP2005350191 A JP 2005350191A JP 2007157963 A JP2007157963 A JP 2007157963A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Abstract
【解決手段】本発明の半導体装置の製造方法は、アンダーフィル材の流出を堰き止めるダム21の形成を電極パッド4の形成工程と同時に行う。電極パッド4は、実装基板1の上に形成された導体層(例えばアルミニウム層)22をフォトリソグラフィ技術によってパターンエッチングすることで形成される。このとき、同じ導体層22をダム層22A用にパターンエッチングすることで、電極パッド4と同時にダム21が形成される。フォトリソグラフィ技術を用いたパターン加工は、1μm以下(最小でも数十nm程度)の微細加工を高精度に制御可能であるため、はんだめっき法に比べて著しく微細なダムを安定して形成することが可能となる。
【選択図】図3
Description
図1及び図2は、本発明の第1の実施の形態による半導体装置20の概略構成を示している。ここで、図1Aは実装基板1に対する半導体チップ2の実装前の状態を示す側断面図、Bはその実装後の状態を示す側断面図、図2は半導体装置20の平面図及び実装基板1の要部拡大断面図である。
次に、図4及び図5を参照して本発明の第2の実施の形態によるアンダーフィル流出防止用ダム31の構成及びその形成方法について説明する。図4及び図5は当該ダムの一形成方法を示す工程断面図である。
Claims (9)
- 実装基板上のチップ実装領域の周囲に電極パッドを形成する工程と、前記チップ実装領域と前記電極パッドの形成領域との間に前記電極パッド側へのアンダーフィル材の流出を堰き止めるダムを形成する工程とを有する半導体装置の製造方法において、
前記実装基板上に前記電極パッドを構成する導体層を形成する工程と、
前記導体層をパターン加工して電極パッド層とダム層とを分離形成する工程とを有する
ことを特徴とする半導体装置の製造方法。 - 前記電極パッド層と前記ダム層の形成後、前記実装基板上に絶縁保護層を形成する工程を有する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記導体層の形成前に、前記ダム層の下地層を前記実装基板上に形成する工程を有する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記導体層をバンプ下地層として、前記チップ実装領域内にめっきバンプを形成する工程を有する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記チップ実装領域に半導体チップをフリップチップ実装した後、前記実装基板と前記半導体チップとの間にアンダーフィル材を充填する工程を有する
請求項1に記載の半導体装置の製造方法。 - チップ実装領域の周囲に電極パッドが形成されるとともに、前記チップ実装領域と前記電極パッドの形成領域との間にダムが設けられた実装基板と、
前記実装基板の前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材とを備えた半導体装置において、
前記ダムが、前記電極パッドの構成材料からなる第1のダム層と、この第1のダム層を被覆する第2のダム層とで形成されている
ことを特徴とする半導体装置。 - 前記第1のダム層は多層構造を有している
ことを特徴とする請求項6に記載の半導体装置。 - 前記第1のダム層はアルミニウムからなり、前記第2のダム層は絶縁材料からなる
ことを特徴とする請求項6に記載の半導体装置。 - 前記実装基板は、半導体チップである
ことを特徴とする請求項6に記載の半導体装置。
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207805A (ja) * | 2006-01-31 | 2007-08-16 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
JP2009177061A (ja) * | 2008-01-28 | 2009-08-06 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
CN102054795A (zh) * | 2009-10-28 | 2011-05-11 | 三星电机株式会社 | 倒装芯片封装及其制造方法 |
JP2011119609A (ja) * | 2009-12-07 | 2011-06-16 | Fujitsu Semiconductor Ltd | 半導体装置とその製造方法 |
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
JP2014103198A (ja) * | 2012-11-19 | 2014-06-05 | J Devices:Kk | 半導体装置及びその製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000133664A (ja) * | 1998-10-22 | 2000-05-12 | Sony Corp | 半導体装置 |
JP2003234362A (ja) * | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | 半導体装置 |
JP2004063791A (ja) * | 2002-07-29 | 2004-02-26 | Sharp Corp | 小型固体撮像装置 |
JP2004214255A (ja) * | 2002-12-27 | 2004-07-29 | Casio Comput Co Ltd | 電子部品の接続構造 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
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2005
- 2005-12-05 JP JP2005350191A patent/JP4792949B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000133664A (ja) * | 1998-10-22 | 2000-05-12 | Sony Corp | 半導体装置 |
JP2003234362A (ja) * | 2002-02-12 | 2003-08-22 | Yokogawa Electric Corp | 半導体装置 |
JP2004063791A (ja) * | 2002-07-29 | 2004-02-26 | Sharp Corp | 小型固体撮像装置 |
JP2004214255A (ja) * | 2002-12-27 | 2004-07-29 | Casio Comput Co Ltd | 電子部品の接続構造 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207805A (ja) * | 2006-01-31 | 2007-08-16 | Sony Corp | 半導体装置の製造方法及び半導体装置 |
JP2009177061A (ja) * | 2008-01-28 | 2009-08-06 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
CN102054795A (zh) * | 2009-10-28 | 2011-05-11 | 三星电机株式会社 | 倒装芯片封装及其制造方法 |
JP2011097060A (ja) * | 2009-10-28 | 2011-05-12 | Samsung Electro-Mechanics Co Ltd | フリップチップパッケージ及びその製造方法 |
US8558360B2 (en) | 2009-10-28 | 2013-10-15 | Samsung Electro-Mechanics Co., Ltd. | Flip chip package and method of manufacturing the same |
US8809122B2 (en) | 2009-10-28 | 2014-08-19 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing flip chip package |
JP2011119609A (ja) * | 2009-12-07 | 2011-06-16 | Fujitsu Semiconductor Ltd | 半導体装置とその製造方法 |
US8673684B2 (en) | 2009-12-07 | 2014-03-18 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method thereof |
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
JP2014103198A (ja) * | 2012-11-19 | 2014-06-05 | J Devices:Kk | 半導体装置及びその製造方法 |
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