JP4760361B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4760361B2 JP4760361B2 JP2005366319A JP2005366319A JP4760361B2 JP 4760361 B2 JP4760361 B2 JP 4760361B2 JP 2005366319 A JP2005366319 A JP 2005366319A JP 2005366319 A JP2005366319 A JP 2005366319A JP 4760361 B2 JP4760361 B2 JP 4760361B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- chip
- semiconductor chip
- mounting substrate
- underfill material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims (4)
- チップ実装領域と、電極パッド形成領域と、前記チップ実装領域と前記電極パッド形成領域との間に設けられたアンダーフィル材の滴下領域とを有する、配線層を絶縁層で被覆してなる主面と、前記電極パッド形成領域に形成され前記配線層と接続される電極パッドと、前記チップ実装領域及び前記滴下領域と前記電極パッド形成領域との間に設けられたダムとを有する実装基板と、
前記チップ実装領域にフリップチップ実装された半導体チップと、
前記実装基板と前記半導体チップとの間に充填されたアンダーフィル材と、
前記チップ実装領域の外側から前記チップ実装領域の内側に亘って、前記チップ実装領域の内側に向かうにつれて幅広となるように前記滴下領域の前記絶縁層に形成され、前記滴下領域に滴下されたアンダーフィル材を前記実装基板と前記半導体チップとの間へ案内するガイド溝と
を備えた半導体装置。 - 前記ガイド溝の最大形成幅は、前記半導体チップの一辺の長さに相当する大きさとされている請求項1に記載の半導体装置。
- 前記滴下領域は、前記チップ実装領域の所定の辺と当該所定の辺に対向するダムとの間に設けられており、
前記チップ実装領域の所定の辺と当該所定の辺に対向する前記ダムとの間の距離は、前記チップ実装領域の他の辺と当該他の辺に対向する前記ダムとの間の距離よりも長く設定されている請求項1に記載の半導体装置。 - 前記実装基板は、半導体チップである請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005366319A JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005366319A JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007173361A JP2007173361A (ja) | 2007-07-05 |
JP4760361B2 true JP4760361B2 (ja) | 2011-08-31 |
Family
ID=38299547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005366319A Expired - Fee Related JP4760361B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4760361B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4910408B2 (ja) * | 2006-01-31 | 2012-04-04 | ソニー株式会社 | 半導体装置 |
JP2008078382A (ja) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体装置とその製造方法 |
US8110933B2 (en) | 2006-12-26 | 2012-02-07 | Panasonic Corporation | Semiconductor device mounted structure and semiconductor device mounted method |
TWI458054B (zh) * | 2009-01-21 | 2014-10-21 | Sony Corp | 半導體裝置及半導體裝置之製造方法 |
US8399300B2 (en) * | 2010-04-27 | 2013-03-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material |
US8617926B2 (en) * | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
JP2017120800A (ja) * | 2015-12-28 | 2017-07-06 | 富士通株式会社 | 半導体素子、半導体素子の製造方法及び電子機器 |
KR20210041929A (ko) | 2019-10-08 | 2021-04-16 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11214586A (ja) * | 1998-01-20 | 1999-08-06 | Murata Mfg Co Ltd | 電子回路装置 |
JP2001308115A (ja) * | 2000-04-20 | 2001-11-02 | Seiko Instruments Inc | 電子回路装置 |
WO2004114402A1 (ja) * | 2003-06-23 | 2004-12-29 | Shinko Electric Industries Co., Ltd. | 配線基板およびその製造方法、並びに配線基板への半導体チップの実装構造 |
JP2005175113A (ja) * | 2003-12-10 | 2005-06-30 | Fdk Corp | フリップチップ実装用プリント配線基板 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
-
2005
- 2005-12-20 JP JP2005366319A patent/JP4760361B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11214586A (ja) * | 1998-01-20 | 1999-08-06 | Murata Mfg Co Ltd | 電子回路装置 |
JP2001308115A (ja) * | 2000-04-20 | 2001-11-02 | Seiko Instruments Inc | 電子回路装置 |
WO2004114402A1 (ja) * | 2003-06-23 | 2004-12-29 | Shinko Electric Industries Co., Ltd. | 配線基板およびその製造方法、並びに配線基板への半導体チップの実装構造 |
JP2005175113A (ja) * | 2003-12-10 | 2005-06-30 | Fdk Corp | フリップチップ実装用プリント配線基板 |
JP2005276879A (ja) * | 2004-03-23 | 2005-10-06 | Sony Corp | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2007173361A (ja) | 2007-07-05 |
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