WO2023040454A1 - 堆叠封装结构及其封装方法和移动终端设备 - Google Patents

堆叠封装结构及其封装方法和移动终端设备 Download PDF

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Publication number
WO2023040454A1
WO2023040454A1 PCT/CN2022/106713 CN2022106713W WO2023040454A1 WO 2023040454 A1 WO2023040454 A1 WO 2023040454A1 CN 2022106713 W CN2022106713 W CN 2022106713W WO 2023040454 A1 WO2023040454 A1 WO 2023040454A1
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Prior art keywords
substrate
component
components
package
package structure
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PCT/CN2022/106713
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English (en)
French (fr)
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林雪
杨庭栋
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中兴通讯股份有限公司
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Publication of WO2023040454A1 publication Critical patent/WO2023040454A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00

Definitions

  • the present disclosure relates to the technical field of package-on-package, and in particular, to a package-on-package structure, a package method thereof, and a mobile terminal device.
  • PCB printed circuit board
  • POP stacking Packaging
  • the main purpose of the embodiments of the present disclosure is to provide a package-on-package structure and its packaging method and a mobile terminal device, aiming at solving the problem that the upper and lower chips in the existing package-on-package structure are prone to high stress risks.
  • An embodiment of the present disclosure provides a packaging method for a package-on-package structure, including the following steps: stacking a substrate and at least two components so that all the components are sequentially stacked along the normal direction of the substrate state; wherein, each of the components includes a device body and an array of solder balls attached to at least one surface of the device body; at least some of the components are attached with an adhesive layer, so that the substrate and all of the components When the components are stacked, the adhesive material layer is arranged at least around the outer periphery of the solder ball array between two adjacent components; reflow soldering is performed on the substrate and all the components, so that The two adjacent components are welded, and the substrate and the components connected to the substrate are welded, and at the same time, the adhesive material layer is glued to at least two adjacent components .
  • An embodiment of the present disclosure also provides a package-on-package structure, including: a device assembly, the device assembly includes at least two components, and all the components are stacked and welded in sequence; a substrate, the substrate and the device group are stacked, And one of the components is stacked and welded with the substrate; the first adhesive layer is adhesively bonded to two adjacent components; the second adhesive layer is the second adhesive layer.
  • the adhesive layer is glued to the device component and the substrate respectively; the package-on-package structure is obtained by packaging according to the packaging method of the above-mentioned package-on-package structure.
  • An embodiment of the present disclosure further provides a mobile terminal device, where the mobile terminal device includes the aforementioned stacked package structure.
  • FIG. 1 is a schematic flowchart of a packaging method for a stacked packaging structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic top view of components stacked by the packaging method of the package-on-package structure provided by the embodiment of the present disclosure
  • Fig. 3 is a schematic sectional view along line A-A in Fig. 2;
  • Fig. 4 is a schematic sectional view along line B-B in Fig. 2;
  • FIG. 5 is a schematic top view of a packaging structure obtained by a packaging method for a stacked packaging structure provided by an embodiment of the present disclosure
  • Fig. 6 is a schematic sectional view along line C-C in Fig. 5;
  • FIG. 7 is a schematic cross-sectional view along line D-D in FIG. 5 .
  • FIG. 1 to FIG. 7 show a package-on-package structure 40 provided by an embodiment of the present disclosure, a packaging method thereof, and a mobile terminal device.
  • the package-on-package structure 40 can be applied to electronic devices such as smart phones, tablet computers, notebook computers, personal digital assistants, wearable devices, POS machines, and vehicle-mounted computers. Since the packaging method of the package-on-package structure 40 of the embodiment of the present disclosure can make the components 30 have good packaging reliability, and obtain the package-on-package structure 40 with good packaging effect, it can effectively improve the packaging structure including the package-on-package structure provided by the embodiment of the present disclosure. 40 The reliability and quality of electronic equipment, improve product yield.
  • the packaging method of the package-on-package structure 40 provided by the embodiment of the present disclosure may include, but not limited to, the following steps.
  • Step S01 stacking the substrate 10 and at least two components 30 , so that all the components 30 are sequentially stacked along the normal direction of the substrate 10 .
  • each component 30 includes a device body 311 and a solder ball array 312, and the solder ball array 312 is attached to at least one surface of the device body 311; at least some components 30 are attached with an adhesive layer 20, so that the substrate 10 and all When the components 30 are stacked, the adhesive material layer 20 is at least disposed around the outer periphery of the solder ball array 312 between two adjacent components 30 .
  • the substrate 10 includes a printed circuit board or the like.
  • the thickness of the substrate 10 is any thickness within the range of 0.5 mm to 0.7 mm, including 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm and 0.7 mm.
  • good stress protection can be formed for the components 30 on the side away from the substrate 10, thereby effectively improving the protection of the thin substrate. 10-based package-on-package structure 40 reliability.
  • the component 30 includes at least one of a main processor chip, a memory chip and the like. In some embodiments, the component 30 also includes any other suitable chips. In some embodiments, the components 30 include at least two types of components 30, such as a first component 31 and a second component 32, wherein the first component 31 includes a main processor chip, and the second component 32 including memory chips.
  • the structure including two types of components 30 can effectively reduce the layout area in addition to realizing the function of assembling the substrate 10 and the components 30 when packaging to form the package-on-package structure 40 . In some embodiments, at least two components 30 are disposed on the same side of the substrate 10 . In other exemplary embodiments, the number of components 30 may be multiple, such as three or four or more.
  • the number of components 30 is multiple, for example, when the number of components 30 is three, three components 30 can be arranged on the same side of the substrate 10; two components 30 can also be arranged on the substrate 10 on the same side of the substrate 10 , and the remaining component 30 is disposed on the opposite side of the substrate 10 .
  • the number of components 30 is four, it can be that four components 30 are all arranged on the same side of the substrate 10; Three components 30 are disposed on opposite sides of the substrate 10 ; or three components 30 are disposed on the same side of the substrate 10 , and the remaining one component 30 is disposed on the opposite side of the substrate 10 .
  • the number of components 30 is other, it can be reasonably adjusted and designed according to the requirements of the package-on-package structure 40 , so it is not exhaustive here.
  • the number of components 30 on the same side of the substrate 10 is two, if the first component 31 and the second component 32 are included, then the first component 31 is stacked on the substrate 10 first , and then stack the second component 32 on the first component 31 .
  • the orthographic projection of the first component 31 on the substrate 10 coincides with the orthographic projection of the second component 32 on the substrate 10; or, the orthographic projection of the second component 32 on the substrate 10 falls on the first component 31 is within the orthographic projection area of the substrate 10 . Both structures of the first component 31 and the second component 32 can effectively reduce the layout area and improve the structural reliability of the package-on-package structure 40 .
  • the number of components 30 on the same side of the substrate 10 is more than two, then the first component 30 is stacked on the substrate 10 first, and then the second component 30 is stacked on the substrate 10. The first component 30, then the third component 30 is stacked on the second component 30, and so on, until the last component 30 is stacked on the penultimate component 30, and the stacking of the components 30 is completed. set processing.
  • the adhesive material layer 20 includes thermoplastic adhesive.
  • the thermoplastic adhesive includes adhesive strips, colloids, or thermoplastic adhesives in other suitable states. Using thermoplastic glue as the adhesive material layer 20 can ensure that the adhesive material layer 20 can melt and flow along the welding surface during reflow soldering, and after reflow soldering is cooled, it can be re-solidified to form a good bonding effect, thereby to good stress protection.
  • the adhesive material layer 20 is arranged around the solder joint between two adjacent components 30.
  • the reflow soldering can make the adhesive material layer 30 melt and flow along the soldering surface, Moreover, after the reflow soldering is cooled, it can re-solidify to form a good bonding effect, thereby forming a good stress protection for the component 30 .
  • the surface of at least one component 30 in the first component 31 and the second component 32 is attached with an adhesive layer 20.
  • the adhesive material layer 20 may be attached to the first component 31, so that when the first component 31 and the second component 32 are stacked on each other, the adhesive material layer 20 rings are arranged on the outer periphery of the solder ball array 312 between the first component 31 and the second component 32; or the adhesive material 20 is attached to the second component 32, and the adhesive material layer 20 attached should make the first component
  • the adhesive material layer 20 is arranged around the outer periphery of the solder ball array 312 between the first component 31 and the second component 32; or part of the adhesive material layer 20 is attached In the first component 31, part of the adhesive layer 20 is attached to the second component 32, and the adhesive layer 20 attached to the first component 31 and the adhesive layer 20 attached to the second component 32 are When the first component 31 and the second
  • the adhesive material layer 20 is arranged around the outer periphery of the solder ball array 312 in a square pattern, or in a circular pattern around the outer periphery of the solder ball array 312, etc.; or in other shapes, specifically according to The shape of the solder ball array 312 varies.
  • the glue material layer 20 may be formed by one section of thermoplastic glue; it may also be formed by multiple sections of thermoplastic glue, and there is a gap between two adjacent sections of thermoplastic glue.
  • the substrate 10 may also be attached with the adhesive material layer 20 .
  • the adhesive material layer 20 is attached to the substrate 10 , after the subsequent reflow soldering process, the dispensing process may no longer be required.
  • the adhesive material layer 20 can be attached to the component 30 and/or the substrate 10 by bonding. Through bonding, the adhesive material layer 20 can be attached with high reliability, and can be attached to the parts that need to be bonded, so as to improve the uniformity of bonding and lay a foundation for the subsequent formation of a uniform bonding effect.
  • the component 30 when attaching the adhesive layer 20, the component 30 is first fixed, and then the material forming the adhesive layer 20 is adsorbed on the surface of the supporting member, and the supporting member will form the surface of the adhesive layer 20. The material is pushed to the surface of the component 30 and squeezes the material forming the adhesive layer 20 , thereby forming the adhesive layer 20 adhered to the surface of the component 30 . Fixing the component 30 and pressing the adhesive material layer 20 with the supporting member should ensure that when the material forming the adhesive material layer 20 adheres to the surface of the component 30, the component 30 will not be greatly deformed or damaged, Ensure that all parts of the component 30 are evenly stressed.
  • the thickness of the adhesive material layer 20 is less than or equal to the height of the solder ball array 312 surrounded by the adhesive material layer 20, which can not only prevent the influence of the thickness of the adhesive material layer 20 on the flux dipping, but also effectively prevent
  • the influence of the thickness of the adhesive material layer 20 on the stacking of two adjacent components 30 can also be beneficial to the effect of flux between two adjacent components 30, improve the welding effect, and improve the uniformity of bonding .
  • the solder ball array 312 of the first component 31 faces the substrate 10 and is stacked on the first component 31
  • the solder ball array 312 of the second component 32 is facing the first component 31 .
  • the number of components 30 is more than two, they are all stacked in the aforementioned manner, so that there is a solder ball array 312 between the components 30 and the substrate 10 that can be soldered by both, and between two adjacent components 30
  • it also includes dipping the components 30 with flux.
  • the surface of the components 30 is attached with flux, which is beneficial to improve at least two components.
  • the reflow soldering effect of the device 30 is also conducive to forming a good soldering effect between the component 30 directly stacked on the surface of the substrate 10 and the substrate 10 .
  • it also includes dipping the substrate 10 with flux, so as to improve the smoothness of reflow soldering.
  • the adhesive layer 20 can be attached first and then the flux is dipped; the flux can also be dipped first and then the adhesive layer 20 is attached; it is also possible to apply flux to the components 30 directly stacked on the surface of the substrate 10 dipping treatment, then attaching the adhesive material layer 20 to other components 30, and then performing dipping treatment on the components 30 with the adhesive material layer 20, etc., in the packaging process, according to the actual situation The situation is adjusted.
  • Step S02 perform reflow soldering process on the substrate 10 and all components 30, solder two adjacent components 30, and solder the substrate 10 and the components 30 connected to the substrate 10, and at the same time, make the adhesive material layer 20 At least two adjacent components 30 are glued together.
  • one of the components 30 is welded together with the substrate 10 through reflow soldering process, while the other components 30 are respectively soldered together with the adjacent components 30, and are arranged around the outer periphery of the solder ball array 312 .
  • the adhesive material layer 20 is heated and melted to spread and adhere between two adjacent components 30, and penetrate into the gap formed during the soldering process of the solder ball array 312.
  • the melted adhesive material Layer 20 forms a first adhesive layer 42 connected between two adjacent components 30, and at the same time, the first adhesive layer 42 also fills in the gap existing in welding, thereby effectively reducing the gap between two adjacent components 30. There is stress between them, forming stress protection for the components 30 on the side away from the substrate 10 , thereby improving the reliability of the package-on-package structure 40 .
  • the outer periphery of the solder ball array 312 of the components 30 directly connected to the substrate 10 is not provided with the adhesive layer 20, then it also includes dispensing the substrate 10 and the components 30 directly connected to the substrate 10 Steps of processing: after dispensing, a second adhesive layer 43 is obtained, the second adhesive layer 43 is connected between the substrate 10 and the component 30 facing the substrate 10, and the second adhesive layer 43 is filled in the substrate 10 and the component 30 are welded in the gap, thereby reducing the stress existing in the welding of the component 30 and the substrate 10, and strengthening the reliability of the connection between the component 30 and the substrate 10.
  • the step of dispensing can be omitted.
  • a package-on-package structure 40 is obtained through the above packaging method.
  • the package-on-package structure 40 provided by the embodiment of the present disclosure includes a substrate 10 , a device component 41 , a first adhesive layer 42 and a second adhesive layer 43 ; wherein, the device component 41 is stacked on the surface of the substrate 10
  • the device assembly 41 includes at least two components 30, all components 30 are stacked and welded sequentially, and one component 30 is stacked and welded with the substrate 10; the first adhesive layer 42 is glued to two adjacent components 30 ;
  • the second adhesive layer 43 is adhesively bonded with the device component 41 and the substrate 10 .
  • the first adhesive layer 42 is respectively filled in the gap formed by welding two adjacent components 30; the second adhesive layer 43 is filled in the gap formed by the welding of the device assembly 41 and the substrate 10, which has a good welding reliability.
  • the upper layer components 30 and the lower layer components 30 inside the device assembly 41 have good welding reliability and bonding reliability, which can effectively form a good stress protection for the upper layer components 30, so that the stacked packaging structure 40 When assembled into mobile terminal equipment with other components, it has good reliability and product yield rate.
  • the device component 41 and the substrate 10 have good connection reliability, and the device component 41 also has good connection reliability between the upper layer components 30 and the lower layer components 30, even when bumping, vibrating or even bumping and falling, the components 30 on the side away from the substrate 10 and the components on the side close to the substrate 10 It is also not easy to produce stress or peeling between 30, which effectively improves the product quality of mobile terminal equipment, effectively improves the yield rate of products, and at the same time effectively reduces the return rate.
  • the substrate 10 of the package-on-package structure 40 includes a printed circuit board, and the thickness of the printed circuit board includes any thickness within the range of 0.5 mm to 0.7 mm; and the device assembly 41 includes a main processor chip and a memory chip;
  • the first adhesive layer 42 is thermoplastic glue, the main processor chip is welded to the printed circuit board, and the memory chip is welded to the main processor chip, wherein the second adhesive layer 43 is connected between the printed circuit board and the main processor chip, And fill in the soldering gap between the printed circuit board and the main processor chip; the first adhesive layer 42 is connected between the main processor chip and the memory chip, and is filled between the main processor chip and the memory chip.
  • a packaging method for a stacked packaging structure 40 includes the following steps (1)-(5).
  • solder ball array 312 of the device 32 and the first component 31 are disposed on the periphery of the solder ball array
  • a packaging method for a stacked packaging structure 40 includes the following steps (1)-(6).
  • a PCB board that is, the substrate 10
  • a thermoplastic adhesive that is, the first component 31
  • a main processor chip that is, the first component 31
  • a memory chip that is, the second component 32
  • a packaging method for a stacked packaging structure 40 includes the following steps (1)-(4).
  • a PCB board that is, the substrate 10
  • a thickness of 0.5 mm a thermoplastic adhesive
  • a main processor chip that is, the first component 31
  • a memory chip that is, the second component 32
  • the chip faces the surface of the flux groove, and obtains the adhesive material layer 20 surrounding the periphery of the solder ball array 312, then removes the baffle and the supporting member, and then uses a vacuum nozzle to transfer the memory chip to the surface of the main processor chip, and The stack is stacked on the surface of the main processor chip.
  • a packaging method for a stacked packaging structure 40 includes the following steps (1)-(6).
  • PCB board i.e. the substrate 10 with a thickness of 0.65mm, thermoplastic glue, a main processor chip (i.e. the first component 31) and a memory chip (i.e. the second component 32).
  • the chip faces the surface of the flux groove, and obtains a part of the adhesive material layer 20 ringed on the outer periphery of the solder ball array 312, then removes the baffle and the supporting member, and then uses a vacuum nozzle to transfer the memory chip to the surface of the main processor chip , and stacked on the surface of the main processor chip, when the solder ball array 312 of the memory chip is facing the main processor chip, the adhesive material layer 20 on the main processor chip and the adhesive material layer 20 on the memory chip surround each other and The ring is disposed on the periphery of the solder ball array 312 of the memory chip.
  • the packaging method of the package-on-package structure provided by the embodiments of the present disclosure, by attaching the adhesive material layer to some components, so that when multiple components are stacked, the glue between two adjacent components
  • the material layer ring is set on the outer periphery of the solder ball array. After reflow soldering, the adhesive material layer is melted and connected between two adjacent components, and extends and penetrates into the soldering gap between two adjacent components to effectively reduce the cost of components.
  • the existing stress between the devices forms stress protection for the components away from the substrate, so that the packaging reliability of the stacked packaging structure can be effectively improved, and the yield rate of the stacked packaging structure packaging can be improved.
  • the package-on-package structure provided by the embodiments of the present disclosure, in addition to lamination welding, two adjacent components in the device assembly are bonded through the first adhesive layer, while between the device assembly and the substrate except The lamination welding is also glued through the second adhesive layer, so there are good connection characteristics between the device component and the substrate, and within the device component, and a good connection is formed between the components on the side away from the substrate and the adjacent components in the component component. Stress protection makes the package-on-package structure have good structural reliability.
  • the mobile terminal device provided by the embodiments of the present disclosure includes the above-mentioned package-on-package structure, and the package-on-package structure has good structural reliability, so the quality of the mobile terminal device can be effectively improved, and the package-on-package structure can be effectively Reduce the return rate of mobile terminal equipment factory.

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Abstract

本公开实施例提供一种堆叠封装结构及其封装方法和移动终端设备，属于堆叠封装领域。其中封装方法包括以下步骤：将基板和至少两个元器件进行叠设处理，使所有的元器件沿基板的法线方向呈依次层叠的状态；每个元器件包括器件主体和附着于器件主体至少一表面的焊球阵列；至少部分元器件贴附有胶材层，以使基板和所有元器件叠设时胶材层至少环设在相邻两个元器件之间的焊球阵列外周；对基板和所有的元器件进行回流焊接处理，使相邻的两个元器件焊接，且使基板和与基板连接的元器件焊接及使胶材层至少与相邻的两个元器件胶接。

Description

堆叠封装结构及其封装方法和移动终端设备
相关申请的交叉引用
本公开要求享有2021年09月14日提交的名称为“堆叠封装结构及其封装方法和移动终端设备”的中国专利申请CN202111084049.6的优先权，其全部内容通过引用并入本公开中。
技术领域
本公开涉及堆叠封装技术领域，尤其涉及一种堆叠封装结构及其封装方法和移动终端设备。
背景技术
随着移动终端的不断智能化，不仅芯片的功能越来越复杂，而且移动终端越来越精密，尤其印刷电路板(Printed Circuit Board，PCB)器件的布局越来越密集，于是芯片厂商推出堆叠封装(Packageonpackgae，POP)工艺，从而使得印刷电路板器件呈现堆叠封装的效果，从而可以有效减小印刷电路板器件布局于移动终端时占据的面积。但是，目前堆叠封装的印刷电路板器件因易存在应力而导致可靠性较差，甚至引发使用过程中印刷电路板器件的上层器件脱落而导致移动终端失效。这主要是在PCB板和芯片越来越薄的前提下进行堆叠封装时，虽然下层芯片和PCB板之间可以进行点胶加固，但是却难以对上层芯片和下层芯片之间进行有效的点胶，难以保证点胶的一致性和连续性等，从而出现点胶不良；此外，下层芯片和上层芯片之间也会出现焊接不良。多方面的因素导致上层芯片和下层芯片之间存在较高的应力风险。
发明内容
本公开实施例的主要目的在于提供一种堆叠封装结构及其封装方法和移动终端设备，旨在解决现有堆叠封装结构中上层芯片和下层芯片容易出现较高应力风险的问题。
本公开实施例提供一种堆叠封装结构的封装方法，包括以下步骤：将基板和至少两个元器件进行叠设处理，使所有的所述元器件沿所述基板的法线方向呈依次层叠的状态；其中，每个所述元器件包括器件主体和附着于所述器件主体至少一表面的焊球阵列；至少部分所述元器件贴附有胶材层，以使所述基板和所有所述元器件叠设时，所述胶材层至少环设在相邻两个所述元器件之间的所述焊球阵列外周；对所述基板和所有的所述元器件进行回流焊接处理，使相邻的两个所述元器件焊接，且使所述基板和与所述基板连接的所述元器件焊接，同 时，使所述胶材层至少与相邻的两个所述元器件胶接。
本公开实施例还提供一种堆叠封装结构，包括：器件组件，所述器件组件包括至少两个元器件，所有所述元器件依次层叠焊接；基板，所述基板和所述器件组层叠设置，且其中一个所述元器件与所述基板层叠焊接；第一胶接层，所述第一胶接层与相邻的两个所述元器件胶接；第二胶接层，所述第二胶接层与所述器件组件和所述基板分别胶接；所述堆叠封装结构按照上述所述的堆叠封装结构的封装方法封装得到。
本公开实施例还提供一种移动终端设备，所述移动终端设备包括上述所述的堆叠封装结构。
附图说明
为了更清楚地说明本公开实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的堆叠封装结构的封装方法的流程示意图；
图2为本公开实施例提供的堆叠封装结构的封装方法层叠元器件后的俯视示意图；
图3为沿图2中A-A线的剖视示意图；
图4为沿图2中B-B线的剖视示意图；
图5为本公开实施例提供的堆叠封装结构的封装方法获得的封装结构的俯视示意图；
图6为沿图5中C-C线的剖视示意图；
图7为沿图5中D-D线的剖视示意图。
附图标号说明：
10、基板；
20、胶材层；
30、元器件；31、第一元器件；311、器件主体；312、焊球阵列；32、第二元器件；
40、堆叠封装结构；
41、器件组件；
42、第一胶接层；
43、第二胶接层。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
附图中所示的流程图仅是示例说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解、组合或部分合并，因此实际执行的顺序有可能根据实际情况改变。
在此本公开说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本公开。如在本公开说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
图1至图7显示了本公开实施例提供的一种堆叠封装结构40及其封装方法和移动终端设备。其中，堆叠封装结构40可应用于智能手机、平板电脑、笔记本电脑、个人数字助理、穿戴式设备、POS机以及车载电脑等电子设备。由于本公开实施例的堆叠封装结构40的封装方法可以使得元器件30间具有良好的封装可靠性，获得封装效果好的堆叠封装结构40，因而可以有效提高包括本公开实施例提供的堆叠封装结构40的电子设备的可靠性和质量，提高产品良率。
下面结合附图，对本公开的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
请参阅图1至图4以及图5，本公开实施例提供的堆叠封装结构40的封装方法，可以包括，但不限于以下步骤。
步骤S01、将基板10和至少两个元器件30进行叠设处理，使所有的元器件30沿基板10的法线方向呈依次层叠的状态。
其中，每个元器件30包括器件主体311和焊球阵列312，焊球阵列312附着于器件主体311的至少一个表面；至少部分元器件30贴附有胶材层20，以使基板10和所有元器件30叠设时，胶材层20至少环设在相邻两个元器件30之间的焊球阵列312外周。
请参阅图1，在步骤S01的一些实施方式中，基板10包括印刷电路板等。在一些实施方式中，基板10的厚度为包括0.5mm、0.55mm、0.6mm、0.65mm及0.7mm等在0.5mm～0.7mm区间内的任一厚度。基于上述厚度的基板10和至少两个元器件30按照本实施方式的封装方法形成堆叠封装结构40时，可对远离基板10一侧的元器件30形成良好的应力保护，从 而有效提高对薄型基板10基的堆叠封装结构40的可靠性。
在一些实施方式中，元器件30则包括主处理器芯片、存储芯片等中的至少一种。在一些实施方式中，元器件30还包括其他任意适用的芯片。在一些实施方式中，元器件30至少包括两种类型的元器件30，如包括第一元器件31和第二元器件32，其中第一元器件31包括主处理器芯片，第二元器件32包括存储芯片。包括两种类型的元器件30的结构，在封装形成堆叠封装结构40时，除了实现基板10和元器件30组装的功能外，还能有效减小布局面积。在一些实施方式中，至少两个元器件30设于基板10的同侧。而在其他示例性的实施方式中，元器件30的数量可以为多个，如可以是三个或者四个或者更多。当元器件30的数量为多个，比如元器件30的数量为三个时，可以是三个元器件30均设于基板10的同侧；也可以是其中两个元器件30设于基板10的同侧，而剩下一个元器件30设于基板10的相对侧。又如，元器件30的数量为四个时，可以是四个元器件30均设于基板10的同侧；也可以是其中两个元器件30设于基板10的同侧，而剩下两个元器件30设于基板10的相对侧；或者三个元器件30设于基板10的同侧，而剩下一个元器件30设于基板10的相对侧。当元器件30的数量是其他时，可以根据堆叠封装结构40的需要进行合理的调整和设计，故，在此不进行穷举。
在一示例性的实施方式中，基板10同侧的元器件30的数量为两个，如包括第一元器件31和第二元器件32，那么先将第一元器件31叠设于基板10，再将第二元器件32叠设于层叠在第一元器件31。在一些实施方式中，第一元器件31在基板10的正投影和第二元器件32在基板10的正投影重合；或者，第二元器件32在基板10的正投影落在第一元器件31在基板10的正投影区域内。第一元器件31和第二元器件32的这两种结构，都可以有效地减小布局面积，并且提高堆叠封装结构40的结构可靠性。
在一示例性的实施方式中，基板10同侧的元器件30的数量为两个以上，那么先将第一个元器件30叠设于基板10，接着将第二个元器件30叠设于第一个元器件30，再将第三个元器件30层叠于第二个元器件30，依次类推，直至最后一个元器件30叠设在倒数第二个元器件30，完成元器件30的叠设处理。
请参阅图1，在步骤S01的一些实施方式中，胶材层20包括热塑性胶。在一些实施方式中，所述热塑性胶包括胶条、胶体或其他适用状态的热塑性胶等。以热塑性胶作为胶材层20，可以确保在回流焊接时，胶材层20可以熔融并沿着焊接面进行延展流动，且回流焊接冷却后，可以重新凝固以形成良好的胶接效果，从而起到良好的应力保护作用。
在一些实施方中，在至少部分元器件30贴附有胶材层20，以使至少两个元器件30层叠设置时，胶材层20环设在相邻两个元器件30之间的焊球阵列312的外周。当胶材层20环设 于由两个元器件30层叠设置而夹设在两个元器件30的焊球阵列312外周时，进行回流焊接可以使得胶材层30熔融并且沿焊接面延展流动，且回流焊接冷却后，可以重新凝固以形成良好的胶接效果，从而对元器件30形成良好的应力保护。
在一些实施方式中，以元器件30包括第一元器件31和第二元器件32为例，在第一元器件31和第二元器件32中至少一个元器件30的表面贴附胶材层20。在一实施方式中，可以是在第一元器件31的贴附胶材层20，使得贴附的胶材层20在第一元器件31和第二元器件32相互层叠设置时，胶材层20环设在第一元器件31和第二元器件32之间的焊球阵列312的外周；或者在第二元器件32贴附胶材20，贴附的胶材层20应该使得第一元器件31和第二元器件32在相互层叠设置时，胶材层20环设在第一元器件31和第二元器件32之间的焊球阵列312的外周；或者部分胶材层20贴附在第一元器件31，部分胶材层20贴附在第二元器件32，且贴附在第一元器件31的胶材层20和贴附在第二元器件32的胶材层20在第一元器件31和第二元器件32相互层叠设置时，两部分胶材层20环设在第一元器件31和第二元器件32之间的焊球阵列312的外周。在一些实施方式中，胶材层20成方形的图案环设在焊球阵列312的外周，或者呈圆形的图案环设在焊球阵列312的外周等；或者呈其他形状的图案，具体根据焊球阵列312的形状而变化。在一些实施方式中，胶材层20可以是由一段热塑性胶形成；也可以是多段热塑性胶形成，且相邻的两段热塑性胶之间具有间隙。
在一些实施方式中，基板10也可以贴附胶材层20，当基板10贴附形成有胶材层20时，后续的回流焊接处理后，可以不再需要点胶处理。
在一些实施方式中，胶材层20可以通过粘接的方式贴附于元器件30和/或基板10。通过粘接，可使得胶材层20贴附可靠性高，且贴附于需要胶接的部位，以提高胶接均匀性，为后续形成均匀的胶接效果奠定基础。
在一些实施方式中，进行胶材层20贴附处理时，先将元器件30固定，接着将形成胶材层20的材料吸附在承托件的表面，承托件将形成胶材层20的材料推至元器件30的表面，并挤压形成胶材层20的材料，从而形成黏附在元器件30表面的胶材层20。对元器件30进行固定和以承托件挤压胶材层20，应在保证形成胶材层20的材料黏附在元器件30表面时，不会导致元器件30发生较大形变或者受损，保证元器件30的各个部位均匀受力。
在一些实施方式中，胶材层20的厚度小于或者等于胶材层20围设的焊球阵列312的高度，这样不仅可以防止胶材层20厚度对助焊剂蘸取的影响，而且可以有效防止胶材层20厚度在相邻两个元器件30层叠码放时的影响，还可以有利于相邻两个元器件30之间助焊剂助焊效果的发挥，提高焊接效果，以及提高胶接均匀性。
当包括第一元器件31和第二元器件32时，为了使得元器件30和基板10能够进行焊接，第一元器件31的焊球阵列312正对基板10，而层叠于第一元器件31上的第二元器件32的焊球阵列312正对第一元器件31。当元器件30的数量超过两个时，均按照前述方式进行层叠设置，以使得元器件30和基板10之间具有可以供两者焊接的焊球阵列312，而且相邻两个元器件30之间也具有可以供焊接的焊球阵列312。
在一些实施方式中，还包括对元器件30进行助焊剂的蘸取处理，通过对元器件30进行助焊剂的蘸取，使得元器件30的表面附着有助焊剂，有利于提高至少两个元器件30的回流焊接效果，同时有利于直接叠设于基板10表面的元器件30与基板10形成良好的焊接效果。在一些实施方式中，还包括对基板10进行助焊剂的蘸取处理，从而有利于提高回流焊接的顺畅性。
可以先进行胶材层20的贴附再蘸取助焊剂；也可以先蘸取助焊剂再进行胶材层20的贴附；还可以对直接叠设于基板10表面的元器件30进行助焊剂的蘸取处理，接着对其他元器件30进行胶材层20的贴附处理，再对贴有胶材层20的元器件30进行助焊剂的蘸取处理等，在封装过程中，可以根据实际情况进行调整。
步骤S02、对基板10和所有的元器件30进行回流焊接处理，使相邻的两个元器件30焊接，且使基板10和与基板10连接的元器件30焊接，同时，使胶材层20至少与相邻的两个元器件30胶接。
在一实施方式中，通过回流焊接处理，使得其中一个元器件30与基板10焊接在一起，而其他元器件30则分别与相邻的元器件30焊接在一起，环设在焊球阵列312外周的胶材层20在回流焊接的过程中，受热熔融而延展附着在相邻两元器件30之间，并渗入焊球阵列312焊接过程中形成的缝隙里，冷却至室温时，熔融的胶材层20形成连接在相邻两个元器件30之间的第一胶接层42，同时第一胶接层42还填充于焊接存在的缝隙里，从而可以有效降低相邻两个元器件30之间存在应力，形成对远离基板10一侧的元器件30的应力保护，从而提高堆叠封装结构40的可靠性。
在一些实施方式中，如果与基板10直接连接的元器件30的焊球阵列312外周没有环设有胶材层20，那么还包括对基板10和与基板10直接连接的元器件30进行点胶处理的步骤，点胶处理后，得到第二胶接层43，第二胶接层43连接在基板10和与基板10正对的元器件30之间，且第二胶接层43填充于基板10和元器件30焊接存在的缝隙里，从而降低元器件30和基板10焊接存在的应力，加固元器件30和基板10连接的可靠性。而如果与基板10直接连接的元器件30的焊球阵列312外周环设有胶材层20，则可以省去点胶处理的步骤。
如图5至图7所示，经过上述的封装方法，获得一种堆叠封装结构40。
请参阅图5至图7，本公开实施例提供的堆叠封装结构40包括基板10、器件组件41、第一胶接层42和第二胶接层43；其中，器件组件41层叠于基板10表面；器件组件41包括至少两个元器件30，所有的元器件30依次层叠焊接，且其中一个元器件30与基板10层叠焊接；第一胶接层42与相邻的两个元器件30胶接；第二胶接层43与器件组件41和基板10胶接。
在一些实施方式中，第一胶接层42分别填充于相邻两个元器件30焊接形成的缝隙里；第二胶接层43填充于器件组件41和基板10焊接形成的缝隙里，具有良好的焊接可靠性。同时器件组件41内部的上层元器件30和下层元器件30之间具有良好的焊接可靠性和胶接可靠性，可以有效地对上层元器件30形成良好的应力保护，从而可以使得堆叠封装结构40在和其他零部件组装成移动终端设备时，具有良好的可靠性和产品良品率，移动终端设备在制造、运输和使用过程中，器件组件41和基板10具有良好的连接可靠性，而且器件组件41内上层元器件30和下层元器件30之间也具有良好的连接可靠性，即使在颠簸、振动甚至碰撞和跌落时，远离基板10一侧的元器件30和靠近基板10一侧的元器件30之间也不容易产生应力或者剥落，有效地提高了移动终端设备的产品质量，有效地提高了产品的良品率，同时退货率得到有效地降低。
在一些实施方式中，堆叠封装结构40的基板10包括印刷电路板，印刷电路板的厚度包括在0.5mm～0.7mm区间内的任一厚度；而器件组件41包括主处理器芯片和存储芯片；第一胶接层42为热塑性胶，主处理器芯片与印刷电路板焊接，存储芯片与主处理器芯片焊接，其中，第二胶接层43连接于印刷电路板和主处理器芯片之间，且填充于印刷电路板和主处理器芯片焊接的缝隙里；第一胶接层42连接于主处理器芯片和存储芯片之间，且填充于主处理器芯片和存储芯片之间。
为更好的说明本公开实施例的技术方案，下面通过若干实施例做进一步的解释说明。
实施例1
请参阅图1至图4和图5、图6，一种堆叠封装结构40的封装方法，包括以下步骤(1)-(5)。
(1)、提供厚度为0.55mm的PCB板(即基板10)、热塑性胶、第一元器件31(即主处理器芯片)和第二元器件32(即存储芯片)。
(2)、采用真空吸嘴吸取第一元器件31，并将第一元器件31放置于助焊剂槽上，以对第一元器件31进行助焊剂的蘸取，使得第一元器件31的焊球阵列312表面蘸有助焊剂，随 后将第一元器件31叠设于PCB板的表面。
(3)、采用真空吸嘴吸取第二元器件32后转移至助焊剂槽上，对第二元器件32进行助焊剂的蘸取，使得第二元器件32的焊球阵列312表面蘸有助焊剂，随后在第二元器件32背对的助焊剂槽的表面上放置挡板，以将第二元器件32抵压在助焊剂槽槽口，将热塑性胶材放置于承托件(图中未示意)上，并推动承托件，使得承托件将热塑性胶材贴附在第二元器件32朝向助焊剂槽的表面，得到胶材层20，胶材层20环设在焊球阵列312的外周，随后移走挡板和承托件，再用真空吸嘴将第二元器件32转移至第一元器件31的表面，并叠设于第一元器件31的表面，第二元器件32的焊球阵列312和第一元器件31正对胶材层20环设在焊球阵列312的外周。
(4)、对层叠设置的PCB板、第一元器件31和第二元器件32进行回流焊接处理，使得第一元器件31与PCB板焊接，同时使得第二元器件32与第一元器件31焊接，而环设于焊球阵列312外周的胶材层20则熔融连接于第一元器件31和第二元器件32之间，同时延展渗入第一元器件31和第二元器件32焊接过程存在的缝隙里。
(5)、对第一元器件31和PCB板进行点胶处理，得到堆叠封装结构40。
实施例2
请参阅图1至图4和图5、图6，一种堆叠封装结构40的封装方法，包括以下步骤(1)-(6)。
(1)、提供厚度为0.7mm的PCB板(即基板10)、热塑性胶、主处理器芯片(即第一元器件31)和存储芯片(即第二元器件32)。
(2)、采用真空吸嘴吸取主处理器芯片，并将主处理器芯片放置于助焊剂槽上，以对主处理器芯片进行助焊剂的蘸取，使得主处理器芯片的焊球阵列312表面蘸有助焊剂。
(3)、在主处理器芯片背对PCB板的表面贴附热塑性胶，挤压形成胶材层20，并且使得胶材层20在存储芯片叠设在主处理器芯片表面时，胶材层20环设在存储芯片焊球阵列312的外周，随后将主处理器芯片叠设于PCB板的表面。
(4)、采用真空吸嘴吸取存储芯片后转移至助焊剂槽上，对存储芯片进行助焊剂的蘸取，使得存储芯片的焊球阵列312表面蘸有助焊剂，随后用真空吸嘴将存储芯片转移至主处理器芯片表面，和主处理器芯片堆叠码放，存储芯片的焊球阵列312和主处理器芯片正对，并且主处理器芯片表面上的胶材层20环设在焊球阵列312的外周。
(5)、对层叠设置的PCB板、主处理器芯片和存储芯片进行回流焊接处理，使得PCB板和主处理器芯片焊接在一起，同时使得存储芯片和主处理器芯片焊接在一起，而胶材层20 则熔融连接于主处理器芯片和存储芯片之间，同时延展渗入主处理器芯片和存储芯片焊接存在的缝隙里。
(6)、对主处理器芯片和PCB板进行点胶处理，得到堆叠封装结构40。
实施例3
请参阅图1至图4和图5、图6，一种堆叠封装结构40的封装方法，包括以下步骤(1)-(4)。
(1)、提供厚度为0.5mm的PCB板(即基板10)、热塑性胶、主处理器芯片(即第一元器件31)和存储芯片(即第二元器件32)。
(2)、采用真空吸嘴吸取主处理器芯片，并将主处理器芯片放置于助焊剂槽上，以对主处理器芯片进行助焊剂的蘸取，使得主处理器芯片的焊球阵列312表面蘸有助焊剂，随后在主处理器芯片背对的助焊剂槽的表面上放置挡板，以将主处理器芯片抵压在助焊剂槽槽口，将热塑性胶放置于承托件上，并推动承托件，使得承托件将热塑性胶贴附在主处理器芯片朝向助焊剂槽的表面，得到环设在焊球阵列312外周的胶材层20，随后移走挡板和承托件，再用真空吸嘴将存储芯片转移并叠设于PCB板的表面。
(3)、采用真空吸嘴吸取存储芯片后转移至助焊剂槽上，对存储芯片进行助焊剂的蘸取，使得存储芯片的焊球阵列312表面蘸有助焊剂，随后在存储芯片背对的助焊剂槽的表面上放置挡板，以将存储芯片抵压在助焊剂槽槽口，将热塑性胶放置于承托件上，并推动承托件，使得承托件将热塑性胶贴附在存储芯片朝向助焊剂槽的表面，得到环设在焊球阵列312外周的胶材层20，随后移走挡板和承托件，再用真空吸嘴将存储芯片转移至主处理器芯片表面，并堆叠码放于主处理器芯片的表面。
(4)、对层叠设置的PCB板、主处理器芯片和存储芯片进行回流焊接处理，使得PCB板和主处理器芯片焊接在一起，贴附在主处理器芯片表面的胶材层20熔融连接于主处理器芯片和PCB板之间，并延展渗入主处理器芯片和PCB板焊接存在的缝隙里，得到堆叠封装结构40；同时使得存储芯片和主处理器芯片焊接在一起，而贴附在存储芯片表面的胶材层20熔融连接于主处理器芯片和存储芯片之间，并延展渗入主处理器芯片和存储芯片焊接存在的缝隙里。
实施例4
请参阅图1至图4和图5、图6，一种堆叠封装结构40的封装方法，包括以下步骤(1)-(6)。
(1)、提供厚度为0.65mm的PCB板(即基板10)、热塑性胶、主处理器芯片(即第 一元器件31)和存储芯片(即第二元器件32)。
(2)、采用真空吸嘴吸取主处理器芯片，并将主处理器芯片放置于助焊剂槽上，以对主处理器芯片进行助焊剂的蘸取，使得主处理器芯片的焊球阵列312表面蘸有助焊剂。
(3)、在主处理器芯片背对PCB板的表面贴附热塑性胶，得到胶材层20，随后将主处理器芯片叠设于PCB板的表面。
(4)、采用真空吸嘴吸取存储芯片后转移至助焊剂槽上，对存储芯片进行助焊剂的蘸取，使得存储芯片的焊球阵列312表面蘸有助焊剂，随后在存储芯片背对的助焊剂槽的表面上放置挡板，以将存储芯片抵压在助焊剂槽槽口，将热塑性胶放置于承托件上，并推动承托件，使得承托件将热塑性胶贴附在存储芯片朝向助焊剂槽的表面，得到环设在焊球阵列312外周上的部分胶材层20，随后移走挡板和承托件，再用真空吸嘴将存储芯片转移至主处理器芯片表面，并堆叠于主处理器芯片的表面，存储芯片的焊球阵列312和主处理器芯片正对时，主处理器芯片上的胶材层20和存储芯片上的胶材层20相互围合且环设在存储芯片的焊球阵列312外周。
(5)、对层叠码放的PCB板、主处理器芯片和存储芯片进行回流焊接处理，使得PCB板和主处理器芯片焊接在一起，同时使得存储芯片和主处理器芯片焊接在一起，而主处理器芯片上的胶材层20和存储芯片上的胶材层20则熔融连接于主处理器芯片和存储芯片之间，同时延展渗入主处理器芯片和存储芯片焊接存在的缝隙里。
(6)、对主处理器芯片和PCB板进行点胶处理，得到堆叠封装结构40。
相对于一些情况而言，本公开实施例提供的堆叠封装结构的封装方法，通过在部分元器件贴附胶材层，使得多个元器件层叠设置时，相邻两个元器件之间的胶材层环设在焊球阵列的外周，经过回流焊接处理，胶材层熔融连接于相邻的两个元器件之间，并且延展渗入相邻两个元器件的焊接缝隙里，以有效降低元器件之间的存在的应力，并形成对远离基板一侧的元器件的应力保护，从而可以有效提高堆叠封装结构的封装可靠性，提高堆叠封装结构封装的良品率。
相对于一些情况而言，本公开实施例提供的堆叠封装结构，由于器件组件中相邻两个元器件之间除了层叠焊接还通过第一胶接层胶接，而器件组件和基板之间除了层叠焊接还通过第二胶结层胶接，因此器件组件和基板之间、器件组件内具有良好的连接特性，且器件组件中远离基板一侧的元器件和相邻的元器件之间形成良好的应力保护，使得堆叠封装结构具有良好的结构可靠性。
相对于一些情况而言，本公开实施例提供的移动终端设备，由于其包括上述的堆叠封装 结构，而堆叠封装结构具有良好的结构可靠性，因此可使移动终端设备质量得到有效提高，可有效地降低移动终端设备出厂的退货率。
在本公开说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。以上所述，仅为本公开的具体实施例，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种堆叠封装结构的封装方法，其中，包括以下步骤：
    将基板和至少两个元器件进行叠设处理，使所有的所述元器件沿所述基板的法线方向呈依次层叠的状态；
    其中，每个所述元器件包括器件主体和附着于所述器件主体至少一表面的焊球阵列；至少部分所述元器件贴附有胶材层，以使所述基板和所有所述元器件叠设时，所述胶材层至少环设在相邻两个所述元器件之间的所述焊球阵列的外周；
    对所述基板和所有的所述元器件进行回流焊接处理，使相邻的两个所述元器件焊接，且使所述基板和与所述基板连接的所述元器件焊接，同时，使所述胶材层至少与相邻的两个所述元器件胶接。
  2. 根据权利要求1所述的堆叠封装结构的封装方法，其中，所述至少两个元器件的数量为两个，包括第一元器件和第二元器件；
    在所述第一元器件、所述第二元器件中至少一个元器件贴附形成所述胶材层；
    将所述第一元器件叠设于所述基板的一表面，并使所述第一元器件的焊球阵列与所述基板正对；
    将所述第二元器件叠设于所述第一元器件，并使所述第二元器件的焊球阵列与所述第一元器件正对；
    对所述基板、所述第一元器件和所述第二元器件进行回流焊接处理。
  3. 根据权利要求2所述的堆叠封装结构的封装方法，其中，所述胶材层贴附于所述第二元器件；
    或者，所述胶材层贴附于所述第一元器件背对所述基板的表面；
    或者，部分所述胶材层贴附于所述第一元器件背对所述基板的表面，剩余所述胶材层贴附于所述第二元器件。
  4. 根据权利要求3所述的堆叠封装结构的封装方法，其中，所述第一元器件在所述基板的正投影和所述第二元器件在所述基板的正投影重合；
    或者，所述第二元器件在所述基板的正投影落在所述第一元器件在所述基板的正投影区域内。
  5. 根据权利要求4所述的堆叠封装结构的封装方法，其中，所述第一元器件包括主处理器芯片；所述第二元器件包括存储芯片。
  6. 根据权利要求1至5任一项所述的堆叠封装结构的封装方法，其中，所述胶材层的厚 度等于或者小于所述焊球阵列的高度；
    和/或，所述胶材层的材质包括热塑性胶。
  7. 根据权利要求1至5任一项所述的堆叠封装结构的封装方法，其中，所述基板包括印刷电路板；
    和/或，所述基板的厚度在0.5mm～0.7mm区间。
  8. 根据权利要求1至5任一项所述的堆叠封装结构的封装方法，其中，还包括对至少部分所述元器件进行助焊剂的蘸取处理；
    和/或，还包括对所述基板和与所述基板直接连接的所述元器件进行点胶处理的步骤。
  9. 一种堆叠封装结构，其中，包括：
    器件组件，所述器件组件包括至少两个元器件，所有所述元器件依次层叠焊接；
    基板，所述基板和所述器件组层叠设置，且其中一个所述元器件与所述基板层叠焊接；
    第一胶接层，所述第一胶接层与相邻的两个所述元器件胶接；
    第二胶接层，所述第二胶接层与所述器件组件和所述基板胶接；
    所述堆叠封装结构按照权利要求1至8任一项所述的堆叠封装结构的封装方法封装得到。
  10. 根据权利要求9所述的堆叠封装结构，其中，所述第一胶接层还填充于相邻两个所述元器件焊接形成的缝隙里；
    和/或，所述第二胶接层还填充于所述器件组件和所述基板焊接形成的缝隙里。
  11. 一种移动终端设备，其中，包括权利要求9至10任一项所述的堆叠封装结构。
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US20090014856A1 (en) * 2007-07-10 2009-01-15 International Business Machine Corporation Microbump seal
CN102800662A (zh) * 2011-05-26 2012-11-28 株式会社东芝 层叠型半导体装置及其制造方法
CN104637826A (zh) * 2013-11-06 2015-05-20 株式会社东芝 半导体装置的制造方法
CN106206329A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090014856A1 (en) * 2007-07-10 2009-01-15 International Business Machine Corporation Microbump seal
CN102800662A (zh) * 2011-05-26 2012-11-28 株式会社东芝 层叠型半导体装置及其制造方法
CN104637826A (zh) * 2013-11-06 2015-05-20 株式会社东芝 半导体装置的制造方法
CN106206329A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置

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