JP2018041906A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2018041906A
JP2018041906A JP2016176671A JP2016176671A JP2018041906A JP 2018041906 A JP2018041906 A JP 2018041906A JP 2016176671 A JP2016176671 A JP 2016176671A JP 2016176671 A JP2016176671 A JP 2016176671A JP 2018041906 A JP2018041906 A JP 2018041906A
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Japan
Prior art keywords
chip
semiconductor
electrode
semiconductor chip
semiconductor device
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JP2016176671A
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JP6753743B2 (ja
Inventor
祐次 唐金
Yuji Karakane
祐次 唐金
福田　昌利
Masatoshi Fukuda
昌利 福田
本間　荘一
Soichi Honma
荘一 本間
直幸 小牟田
Naoyuki Komuda
直幸 小牟田
幸史 尾山
Yukifumi Oyama
幸史 尾山
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Kioxia Corp
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Toshiba Memory Corp
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Priority to JP2016176671A priority Critical patent/JP6753743B2/ja
Priority to TW105144001A priority patent/TWI620293B/zh
Priority to CN201710054525.7A priority patent/CN107808880B/zh
Priority to US15/445,988 priority patent/US10600773B2/en
Publication of JP2018041906A publication Critical patent/JP2018041906A/ja
Priority to US16/793,323 priority patent/US10903200B2/en
Application granted granted Critical
Publication of JP6753743B2 publication Critical patent/JP6753743B2/ja
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Abstract

【課題】半導体チップ積層体がより効率的に樹脂で封止された半導体装置の製造方法を提供する。
【解決手段】バンプ電極５を有する第１半導体チップ４の第１面上にバンプ電極５及び貫通電極３を有する第２半導体チップ２−３を、バンプ電極５と第１貫通電極３とが重なるように積層させ、第２半導体チップ２−３上に貫通電極３を有する第３半導体チップ２−２を、バンプ電極５と貫通電極３とが重なるように積層させてチップ積層体を形成する。チップ積層体のバンプ電極５をリフローによって貫通電極３に機械的に接続し、第２面を有する配線基板６上に前記第１面が前記第２面側に向くようにチップ積層体を搭載し、前記第２面上及び各半導体チップ間を樹脂封止する。
【選択図】図１

Description

本発明の実施形態は、半導体装置の製造方法に関する。
ＮＡＮＤ型フラッシュメモリ等の高容量を要求されるデバイスにおいて、半導体チップ
を多段に積層して樹脂封止する方法が提案されている。各半導体チップは信号取り出しの
伝達速度をより高速化するためにＴＳＶ（Ｔｈｒｏｕｇｈ Ｓｉｌｉｃｏｎ ＶＩＡ）方
式による積層方式が注目されている。
米国特許出願公開第２０１５／００６９５９６号明細書
本発明が解決しようとする課題は、半導体チップ積層体がより効率的に樹脂で封止され
た半導体装置の製造方法を提供することである。
実施形態の半導体装置の製造方法は、第１バンプ電極を有する第１半導体チップの第１
面上に第２バンプ電極及び第１貫通電極を有する第２半導体チップを、前記第１バンプ電
極と前記第１貫通電極とが重なるように積層させ、前記第２半導体チップ上に第２貫通電
極を有する第３半導体チップを、前記第２バンプ電極と前記第２貫通電極とが重なるよう
に積層させてチップ積層体を形成し、前記チップ積層体の前記第１及び第２バンプ電極を
リフローによって前記第１及び第２貫通電極に機械的に接続し、第２面を有する第１基板
上に前記第１面が前記第２面側に向くように前記チップ積層体を搭載し、前記第２面上及
び前記第１、第２及び第３半導体チップ間を樹脂封止する。
第１の実施形態に係る半導体装置の構成を示す断面図。 第１の実施形態に係る半導体装置の構成を示す断面図。 第１の実施形態に係る半導体装置の製造方法を説明する図。 第１の実施形態に係る半導体装置の製造方法を説明する図。 第１の実施形態に係る半導体装置の製造方法を説明する図。 第１の実施形態に係る半導体装置の製造方法を説明する図。 第１の実施形態に係る半導体装置の製造方法を説明する図。 第２の実施形態に係る半導体装置の構成を示す断面図。 第２の実施形態に係る半導体装置の製造方法を説明する図。 第２の実施形態に係る半導体装置の製造方法を説明する図。
（第１の実施形態）
以下、第１の実施形態に係る半導体装置について図１乃至図７を参照して説明する。な
お、以下の図面の記載において、同一の部分には同一の符号で表している。ただし、図面
は厚さと平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
図１は、第１の実施形態に係る半導体装置の構成を示す断面図である。図１に示すよう
に本実施形態に係る半導体装置は支持基板１、半導体チップ２、貫通電極３、半導体チッ
プ４（ロジックＬＳＩ）及び金属バンプ５を含むチップ積層体と、配線基板６、樹脂モー
ルド７を備える。
本実施形態の半導体装置は、配線基板６上に支持基板１及び半導体チップ２を含むチッ
プ積層体がフリップチップ接続され、半導体チップ２間を含む配線基板６上のチップ積層
体が樹脂でモールドされる。
支持基板１は配線基板６に対向する第１面１ａと、第１面１ａの反対の面である第２面
１ｂとを有する。支持基板１の第１面１ａには、接着剤１１を介して半導体チップ２−１
が接着されている。
支持基板１は例えばリードフレームなどの金属板、シリコン基板、またはフィルム材料
等が用いられる。接着剤１１は例えばダイアタッチフィルムを含む。
半導体チップ２−１の支持基板１と反対の面には、複数の金属バンプ５が形成され、金
属バンプ５は半導体チップ２−２に形成された貫通電極３に電気的に接続されている。ま
た、同様に半導体チップ２−２の貫通電極３は金属バンプ５を介して半導体チップ２−３
に形成された貫通電極３に電気的に接続されている。半導体チップ２−３の配線基板６側
の面には図示しない再配線が形成されている。半導体チップ２−３の貫通電極３は金属バ
ンプ５を介して半導体チップ４と電気的に接続されている。支持基板１、半導体チップ２
及び半導体チップ４を合わせてチップ積層体とする。
半導体チップ２は例えばＮＡＮＤ型フラッシュメモリ等のメモリチップを含む。半導体
チップ２、４はシリコン基板、ＳｉＣやＧａＮなどの基板等を用いることができるが特に
限定されない。
半導体チップ２−２、２−３に設けられた貫通電極（Ｔｈｒｏｕｇｈ Ｓｉｌｉｃｏｎ
Ｖｉａ：ＴＳＶ）３は、半導体チップ２−１、２−２に電位や信号を伝える。
半導体チップ２は共通の半導体チップ４と並列に接続される（バス接続）。つまり、貫
通電極３によってチップ積層方向に形成される共通のデータバスに対して、複数の半導体
チップ２のデータ入出力線が並列接続している。
金属バンプ５は例えば、Ａｕ、Ｎｉ、Ｃｕ、Ｓｎ、Ｂｉ、Ｚｎ、Ｉｎ、またはその合金
を用いる。または、金属バンプに代えてＡｕ、Ｎｉ、Ｃｕ、Ａｌ、Ｐｄ、またはその合金
を含む電極パッドを用いても良い。
本実施形態における半導体チップ２の数は例えば３個を示したが、半導体チップ２の数
は特に限定されない。また、金属バンプ５の数も特に限定されない。
配線基板６は、樹脂製の絶縁層６１と、金属製の配線層６２とを有する。絶縁層６１は
、コア層とビルドアップ層とを有する。配線基板６上には、配線基板６に対して半導体チ
ップ４が最も近く、支持基板１が最も遠くなるようにチップ積層体が搭載されている。
配線基板６は、例えば、図１において、チップ積層体の搭載面である第１面６ａと、第
１面６ａの反対面である第２面６ｂを有している。配線基板６の第２面６ｂには外部接続
端子９が形成されている。半導体装置をＢＧＡパッケージとして使用する場合、外部接続
端子９にはんだボール、はんだメッキ、Ａｕメッキ等を有する突起端子を用いる。半導体
装置をＬＧＡパッケージとして使用する場合には、外部接続端子９に金属ランドを用いる
。
配線基板６の第１面６ａには内部接続端子１０が設けられる。内部接続端子１０は例え
ばはんだバンプ８等を介して半導体チップ４を除いたチップ積層体の最下段の半導体チッ
プ２−３の第１面６ａ側の面に設けられた電極パッド２−３ａに接続される。内部接続端
子１０はチップ積層体との接続時に接続部（接続パッド）として機能するものであり、配
線基板６の配線網を介して外部接続端子９と電気的に接続されている。
配線基板６の第１面６ａ上に位置するチップ積層体、金属バンプ５、及びはんだバンプ
８は全体が樹脂モールド７で覆われ封止されている。
なお、図２に示すように、半導体チップ２及び４間に接着剤１２、及び配線基板６とチ
ップ積層体との間に接着剤１３を設けても良い。これにより、半導体チップ２間、及び配
線基板６とチップ積層体との接続が強固になり、ズレを低減できる。
次に本実施形態に係る半導体装置の製造方法について説明する。
図３乃至図７は本実施形態に係る半導体装置の製造方法を製造工程順に示す断面図であ
る。
図３（ａ）に示すように、金属バンプ５が形成された半導体チップ２−１の金属バンプ
５が形成された面（第１面）とは反対側の面に接着剤１１を設け、支持基板１の第１面１
ａに接着させる。
次に、図３（ｂ）に示すように貫通電極３があらかじめ形成され、かつ金属バンプ５を
有する半導体チップ２−２を半導体チップ２−１上に積層する。貫通電極３の形成は、例
えばＢＳＶ（Ｂａｃｋ Ｓｉｄｅ ＶＩＡ）方式のウエハプロセスによって行なわれる。
なお、ＢＳＶ方式とは、基板表面に半導体素子と配線を有するＬＳＩ及び表電極を形成し
、基板裏面から配線に向かってホールを形成し、ホールに金属を埋め込むことでＴＳＶを
形成する方法である。
ここで、半導体チップ２−２に形成された貫通電極３が、半導体チップ２−１に形成さ
れた金属バンプ５と、支持基板１に対して略垂直なＺ軸に上下に重なるように積層される
。同様にして貫通電極３を有する半導体チップ２−３を半導体チップ２−２上に積層する
（図４（ａ））。半導体チップ２−３には例えば半導体チップ２−２と反対側の面に再配
線（図示しない）と電極パッド２−３ａを有する。なお、半導体チップ２の積層において
、半導体チップ２−１にあらかじめ金属バンプ５を形成せず、半導体チップ２−２及び２
−３の支持基板１側の面にあらかじめ金属バンプ５を形成し、上述のように積層させる方
法を用いても良い。
次に、図４（ｂ）に示すように、金属バンプ５が形成された半導体チップ４を半導体チ
ップ２−３上に積層する。この時、例えば金属バンプ５が半導体チップ２−３の貫通電極
３上に位置するように搭載される。なお、半導体チップ２−３の配線基板６と対向する面
には再配線が形成されていても良い。その場合、再配線上に金属バンプ５が搭載される。
このようにしてチップ積層体が完成する。
上記のチップ積層体において、それぞれの半導体チップ２を積層させるときの温度は金
属バンプ５の溶融温度未満でおこない、それにより半導体チップ間を機械的に接続しない
ようにしている。これにより半導体チップを積層するときに、金属バンプ５の溶融や凝固
を繰り返すことにより金属バンプ５が脆くなり、半導体チップ２の接続部が破断する虞を
低減できる。
なお、上述のように製造途中で半導体チップ２間の金属バンプ５を機械的に接続しない
ため、製造工程内で半導体チップ２の上下に重なる金属バンプ５同士の位置ズレが生じる
虞がある。したがって、位置ズレを防ぐために、全ての半導体チップを積層しチップ積層
体を形成後、樹脂封止を行う前にチップ積層体の還元リフローを行うことが望ましい。ま
たは、図２に示したようにあらかじめ半導体チップ２の表面に接着剤（接着性を有する樹
脂）１２を形成しておき、接着剤１２を用いて半導体チップの間を固定させる方法を用い
てもよい。
次に図５に示すように、配線を有する配線基板６の第１面６ａの内部接続端子１０上に
はんだバンプ８を形成し、上述のように製造されたチップ積層体を第１面６ａにフリップ
チップ実装する。この際、半導体チップ２−３に形成された電極パッド２−３ａと配線基
板６上のはんだバンプ８が配線基板６と重なるようにする。また、フリップチップ実装す
るときの温度は、配線基板６に形成されたはんだバンプ８の溶融温度未満でおこなっても
良い。
なお、チップ積層体を実装する前に、配線基板６上に接着剤１３をあらかじめ形成して
おき、図２に示すようにチップ積層体と配線基板６とを固定させる方法を用いてもよい。
次に、チップ積層体が搭載された配線基板６を還元雰囲気内で加熱し、半導体チップの
金属バンプ５及び配線基板６のはんだバンプ８を溶融させる。これにより半導体チップ２
の間及びチップ積層体と配線基板６を電気的に接続させる。
次に、図６に示すように、半導体チップ２の間およびチップ積層体と配線基板６の間も
含めた配線基板６上をトランスファーモールドによって樹脂モールド７で一括封止する。
図７に示すように、配線基板６の第２面６ｂに外部接続端子９を形成する。最後に半導
体装置の断片化（シンギュレーション）を行う（図示しない）。
上記のようにして本実施形態の半導体装置が完成する。
本実施形態に係る半導体装置の製造方法によれば、チップ積層体を形成後に、アンダー
フィル剤等で一度チップ間に樹脂を充填することなく、トランスファーモールドにより一
括で全体を樹脂封止することが可能になる。そのため工程数が削減できる。
また、チップ積層体を形成する際に、全ての半導体チップを積層した後に還元雰囲気中
に晒すことによって一度に金属バンプと貫通電極を接続させるため、金属バンプの溶融及
び凝固を繰り返すことにより金属バンプが脆くなり、半導体チップの接続部が破断する虞
を低減できる。
（第２の実施形態）
次に、第２の実施形態について、図８及び図９を参照しながら説明する。
第２の実施形態は、第１の実施形態と比較して、支持基板を用いないという点が異なる
。なお、それ以外は第１の実施形態と同様である。
図８は第２の実施形態に係る半導体装置の構成を示す断面図である。図８に示すように
、本実施形態の半導体装置は第１の実施形態と比較して支持基板を用いない。つまり、配
線基板上のチップ積層体の最上段は半導体チップ２−１となる。なお、その他の構成は第
１の実施形態と同様であるためその説明は省略する。
第２の実施形態に係る半導体装置の製造方法は、図９（ａ）に示すように金属バンプ５
があらかじめ形成された半導体チップ２−１上に、貫通電極３及び金属バンプ５があらか
じめ形成された半導体チップ２−２を積層する。この時、半導体チップ２−１に対して略
垂直なＺ軸方向において、半導体チップ２−１の金属バンプ５と半導体チップ２−２の貫
通電極３との位置が重なるように積層させる。その後の工程は第１の実施形態と同様なた
め説明を省略する。なお、図９（ｂ）に示すように、半導体チップ２及び４間、及びチッ
プ積層体と配線基板６との間に接着剤１２、１３を用いても良い。
以上、本実施形態に係る半導体装置によれば、第１の実施形態と同様な効果を有し、さ
らには第１の実施形態と比較して支持基板を用いずにチップ積層体を形成することが可能
なため、工程数及び費用が削減される。
次に、第２の実施形態のその他の製造方法について、図１０を参照しながら説明する。
その他の製造方法は、第２の実施形態の製造方法と比較して、テープ材料を用いる点で
異なる。なお、それ以外は第２の実施形態と同様である。
図１０（ａ）に示すように、接着性のあるテープ材料１００を準備し、その上に金属バ
ンプが形成された半導体チップ２−１を接着させる。テープ材料１００はたとえば、片面
に接着性を有するものであればその形状や材質は問わない。その後、第２の実施形態と同
様にチップ積層体を形成する。チップ積層体の金属バンプを還元雰囲気等によって電気的
に接続させた後に、テープ材料１００をチップ積層体から剥離させる。テープ材料１００
の剥離は、例えばピックアップツールＡ及び吸着ツールＢ等を用いる。
図１０（ｂ）にピックアップツールＡおよび吸着ツールＢを用いたテープ材料１００の
剥離方法を示している。ピックアップツールＡにより、チップ積層体を突き上げると同時
に吸着ツールＢによりチップ積層体の半導体チップ４を吸着させることで、テープ材料１
００をチップ積層体から剥離させることが可能になる。なお、この時吸着させる半導体チ
ップは半導体チップ２でも良い。その後の製造方法は第２の実施形態に示したとおりであ
る。
以上、本実施形態に係る半導体装置のその他の製造方法によれば、第１の実施形態と同
様の効果を有し、さらには第１の実施形態と比較してテープ材料を後に剥離させるため、
半導体装置の面積を削減することが可能になる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したも
のであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その
他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の
省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や
要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる
１ 支持基板
１ａ、６ａ 第１面
１ｂ、６ｂ 第２面
２ 半導体チップ
３ 貫通電極
４ 半導体チップ（ロジックＬＳＩ）
５ 金属バンプ
６ 配線基板
７ 樹脂モールド
８ はんだバンプ
９ 外部接続端子
１０ 内部接続端子
１１、１２、１３ 接着剤
６１ 絶縁層
６２ 配線層
１００ テープ材料

Claims (9)

  1. 第１バンプ電極を有する第１半導体チップの第１面上に第２バンプ電極及び第１貫通電
    極を有する第２半導体チップを、前記第１バンプ電極と前記第１貫通電極とが重なるよう
    に積層させ、
    前記第２半導体チップ上に第２貫通電極を有する第３半導体チップを、前記第２バンプ
    電極と前記第２貫通電極とが重なるように積層させてチップ積層体を形成し、
    前記チップ積層体の前記第１及び第２バンプ電極をリフローによって前記第１及び第２
    貫通電極に機械的に接続し、
    第２面を有する第１基板上に前記第１面が前記第２面側に向くように前記チップ積層体
    を搭載し、
    前記第２面上及び前記第１、第２及び第３半導体チップ間を樹脂封止する、
    半導体装置の製造方法。
  2. 第１半導体チップの第１面上に、第１バンプ電極及び第１貫通電極を有する第２半導体
    チップを前記第１バンプ電極が前記第１面に接するように積層させ、
    前記第２半導体チップ上に、第２バンプ電極及び第２貫通電極を有する第３半導体チッ
    プを前記第２バンプ電極と前記第１貫通電極とが重なるように積層させてチップ積層体を
    形成し、
    前記チップ積層体の前記第１及び第２バンプ電極をリフローによって前記第１及び第２
    貫通電極に機械的に接続し、
    第２面を有する第１基板上に前記第１面が前記第１面側に向くように前記チップ積層体
    を搭載し、
    前記第２面上及び前記第１、第２及び第３半導体チップ間を樹脂封止する、
    半導体装置の製造方法。
  3. 前記第１半導体チップの前記第１面と反対面に第１樹脂を介して第２基板を設けること
    を特徴とする請求項１または２に記載の半導体装置の製造方法。
  4. テープ材料に前記第１半導体チップの前記第１面と反対面を接着させることを特徴とす
    る請求項１または２に記載の半導体装置の製造方法。
  5. 前記リフローは、還元雰囲気中で行うことを特徴とする請求項１乃至４のいずれか１項
    に記載の半導体装置の製造方法。
  6. 前記樹脂封止はトランスファーモールドによって行うことを特徴とする請求項１乃至５
    のいずれか１項に記載の半導体装置の製造方法。
  7. 前記第１及び第２バンプ電極はＡｕ、Ｎｉ、Ｃｕ、Ｓｎ、Ｂｉ、Ｚｎ、Ｉｎ、及びその
    合金のいずれかを含む金属バンプ、またはＡｕ、Ｎｉ、Ｃｕ、Ａｌ、Ｐｄ、及びその合金
    のいずれかを含む電極パッドであることを特徴とする請求項１乃至６のいずれか１項に記
    載の半導体装置の製造方法。
  8. 前記チップ積層体を形成後、
    ピックアップツール及び吸着ツールを用いて前記テープ材料を剥離することを特徴とす
    る請求項４に記載の半導体装置の製造方法。
  9. 前記第１、第２及び第３半導体チップ間、または前記チップ積層体及び前記第１基板と
    の間に更に接着樹脂を有することを特徴とする請求項１乃至８のいずれか１項に記載の半
    導体装置の製造方法。
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