CN103022021B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN103022021B CN103022021B CN201210350172.2A CN201210350172A CN103022021B CN 103022021 B CN103022021 B CN 103022021B CN 201210350172 A CN201210350172 A CN 201210350172A CN 103022021 B CN103022021 B CN 103022021B
- Authority
- CN
- China
- Prior art keywords
- chip
- stacks
- die
- semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 198
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 186
- 238000003475 lamination Methods 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 claims description 81
- 229920005989 resin Polymers 0.000 claims description 81
- 238000004382 potting Methods 0.000 claims description 39
- 238000005520 cutting process Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 2
- 101150106357 slc32a1 gene Proteins 0.000 claims 1
- 238000003860 storage Methods 0.000 description 53
- 230000015654 memory Effects 0.000 description 24
- 229910000679 solder Inorganic materials 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 230000009467 reduction Effects 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 239000007767 bonding agent Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000002788 crimping Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000013007 heat curing Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000005764 inhibitory process Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000011664 signaling Effects 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 229910017944 Ag—Cu Inorganic materials 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 2
- 229910020888 Sn-Cu Inorganic materials 0.000 description 2
- 229910020988 Sn—Ag Inorganic materials 0.000 description 2
- 229910019204 Sn—Cu Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 102100035683 Axin-2 Human genes 0.000 description 1
- 101700047552 Axin-2 Proteins 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 241000949477 Toona ciliata Species 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (19)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011206869 | 2011-09-22 | ||
JP206869/2011 | 2011-09-22 | ||
JP2012200287A JP5936968B2 (ja) | 2011-09-22 | 2012-09-12 | 半導体装置とその製造方法 |
JP200287/2012 | 2012-09-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103022021A CN103022021A (zh) | 2013-04-03 |
CN103022021B true CN103022021B (zh) | 2016-05-11 |
Family
ID=47910372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210350172.2A Active CN103022021B (zh) | 2011-09-22 | 2012-09-19 | 半导体装置及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8941246B2 (zh) |
JP (1) | JP5936968B2 (zh) |
CN (1) | CN103022021B (zh) |
TW (1) | TWI483376B (zh) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9000599B2 (en) * | 2013-05-13 | 2015-04-07 | Intel Corporation | Multichip integration with through silicon via (TSV) die embedded in package |
KR102041639B1 (ko) * | 2013-07-08 | 2019-11-07 | 삼성전기주식회사 | 고주파 모듈 |
JP2015056563A (ja) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2015177062A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
JP2015177007A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
US9786643B2 (en) * | 2014-07-08 | 2017-10-10 | Micron Technology, Inc. | Semiconductor devices comprising protected side surfaces and related methods |
DE102014112430A1 (de) | 2014-08-29 | 2016-03-03 | Ev Group E. Thallner Gmbh | Verfahren zur Herstellung eines leitenden Mehrfachsubstratstapels |
JP6276151B2 (ja) | 2014-09-17 | 2018-02-07 | 東芝メモリ株式会社 | 半導体装置 |
JP6212011B2 (ja) * | 2014-09-17 | 2017-10-11 | 東芝メモリ株式会社 | 半導体製造装置 |
CN107004672B (zh) * | 2014-12-18 | 2020-06-16 | 索尼公司 | 半导体装置、制造方法及电子设备 |
JP6495692B2 (ja) * | 2015-03-11 | 2019-04-03 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
JP2016225484A (ja) * | 2015-06-01 | 2016-12-28 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
KR102401109B1 (ko) | 2015-06-03 | 2022-05-23 | 삼성전자주식회사 | 반도체 패키지 |
JP6421083B2 (ja) | 2015-06-15 | 2018-11-07 | 株式会社東芝 | 半導体装置の製造方法 |
US9741695B2 (en) * | 2016-01-13 | 2017-08-22 | Globalfoundries Inc. | Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding |
KR102579876B1 (ko) | 2016-02-22 | 2023-09-18 | 삼성전자주식회사 | 반도체 패키지 |
JP6524003B2 (ja) | 2016-03-17 | 2019-06-05 | 東芝メモリ株式会社 | 半導体装置 |
JP2018107394A (ja) * | 2016-12-28 | 2018-07-05 | 新光電気工業株式会社 | 配線基板及び電子部品装置とそれらの製造方法 |
US11081451B2 (en) * | 2017-03-10 | 2021-08-03 | Intel Corporation | Die stack with reduced warpage |
JP6679528B2 (ja) | 2017-03-22 | 2020-04-15 | キオクシア株式会社 | 半導体装置 |
KR102315325B1 (ko) | 2017-07-05 | 2021-10-19 | 삼성전자주식회사 | 반도체 패키지 |
EP3580782A4 (en) * | 2017-08-21 | 2020-12-02 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL MEMORY COMPONENTS AND METHOD FOR SHAPING THEM |
US10700028B2 (en) | 2018-02-09 | 2020-06-30 | Sandisk Technologies Llc | Vertical chip interposer and method of making a chip assembly containing the vertical chip interposer |
KR102506698B1 (ko) * | 2018-02-19 | 2023-03-07 | 에스케이하이닉스 주식회사 | 보강용 탑 다이를 포함하는 반도체 패키지 제조 방법 |
CN113851153B (zh) | 2018-03-09 | 2023-12-26 | Hoya株式会社 | 间隔件、基板的层积体和基板的制造方法 |
JP7144951B2 (ja) | 2018-03-20 | 2022-09-30 | キオクシア株式会社 | 半導体装置 |
KR102589736B1 (ko) | 2018-03-26 | 2023-10-17 | 삼성전자주식회사 | 반도체 칩 및 이를 포함하는 반도체 패키지 |
CN110660805B (zh) * | 2018-06-28 | 2023-06-20 | 西部数据技术公司 | 包含分支存储器裸芯模块的堆叠半导体装置 |
JP2019220621A (ja) * | 2018-06-21 | 2019-12-26 | キオクシア株式会社 | 半導体装置及びその製造方法 |
WO2020000392A1 (en) | 2018-06-29 | 2020-01-02 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices with stacked device chips using interposers |
KR102551751B1 (ko) * | 2018-11-06 | 2023-07-05 | 삼성전자주식회사 | 반도체 패키지 |
JP6689420B2 (ja) * | 2019-01-17 | 2020-04-28 | キオクシア株式会社 | 半導体装置および半導体装置の製造方法 |
US10879260B2 (en) | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
US10923438B2 (en) | 2019-04-26 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for forming the same |
JP2021048195A (ja) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2021129084A (ja) | 2020-02-17 | 2021-09-02 | キオクシア株式会社 | 半導体装置およびその製造方法 |
CN117133727A (zh) * | 2023-08-29 | 2023-11-28 | 江苏柒捌玖电子科技有限公司 | 一种三维堆叠封装结构及其封装方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1665027A (zh) * | 2004-03-01 | 2005-09-07 | 株式会社日立制作所 | 半导体器件 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2997231B2 (ja) * | 1997-09-12 | 2000-01-11 | 富士通株式会社 | マルチ半導体ベアチップ実装モジュールの製造方法 |
JP4419049B2 (ja) * | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
JP4345705B2 (ja) | 2005-04-19 | 2009-10-14 | エルピーダメモリ株式会社 | メモリモジュール |
JP4191167B2 (ja) * | 2005-05-16 | 2008-12-03 | エルピーダメモリ株式会社 | メモリモジュールの製造方法 |
JP4507101B2 (ja) | 2005-06-30 | 2010-07-21 | エルピーダメモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP2007036104A (ja) * | 2005-07-29 | 2007-02-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4753725B2 (ja) * | 2006-01-20 | 2011-08-24 | エルピーダメモリ株式会社 | 積層型半導体装置 |
JP4910512B2 (ja) * | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
TWI349318B (en) * | 2007-04-11 | 2011-09-21 | Siliconware Precision Industries Co Ltd | Stackable semiconductor device and manufacturing method thereof |
JP2008294367A (ja) * | 2007-05-28 | 2008-12-04 | Nec Electronics Corp | 半導体装置およびその製造方法 |
TWI355731B (en) * | 2008-02-26 | 2012-01-01 | Powertech Technology Inc | Chips-between-substrates semiconductor package and |
JP2010107388A (ja) * | 2008-10-30 | 2010-05-13 | Denso Corp | マルチチップパッケージ |
JP2010161102A (ja) * | 2009-01-06 | 2010-07-22 | Elpida Memory Inc | 半導体装置 |
TWI401785B (zh) * | 2009-03-27 | 2013-07-11 | Chipmos Technologies Inc | 多晶片堆疊封裝 |
JP5543125B2 (ja) * | 2009-04-08 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置および半導体装置の製造方法 |
JP2010287852A (ja) | 2009-06-15 | 2010-12-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
WO2011065544A1 (ja) * | 2009-11-27 | 2011-06-03 | 日本電気株式会社 | 半導体装置、3次元実装型半導体装置、半導体モジュール、電子機器、及びその製造方法 |
-
2012
- 2012-09-12 JP JP2012200287A patent/JP5936968B2/ja active Active
- 2012-09-17 TW TW101134048A patent/TWI483376B/zh active
- 2012-09-19 CN CN201210350172.2A patent/CN103022021B/zh active Active
- 2012-09-20 US US13/623,249 patent/US8941246B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1665027A (zh) * | 2004-03-01 | 2005-09-07 | 株式会社日立制作所 | 半导体器件 |
Also Published As
Publication number | Publication date |
---|---|
CN103022021A (zh) | 2013-04-03 |
JP5936968B2 (ja) | 2016-06-22 |
TWI483376B (zh) | 2015-05-01 |
JP2013080912A (ja) | 2013-05-02 |
US8941246B2 (en) | 2015-01-27 |
US20130075895A1 (en) | 2013-03-28 |
TW201316486A (zh) | 2013-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103022021B (zh) | 半导体装置及其制造方法 | |
CN102222657B (zh) | 多圈排列双ic芯片封装件及其生产方法 | |
CN104064486B (zh) | 半导体装置以及层叠型半导体装置的制造方法 | |
TWI414049B (zh) | 半導體裝置之製造方法 | |
CN101335253B (zh) | 半导体封装体以及使用半导体封装体的半导体器件 | |
US10903200B2 (en) | Semiconductor device manufacturing method | |
CN102136434A (zh) | 在引线键合的芯片上叠置倒装芯片的方法 | |
TW200531188A (en) | Land grid array packaged device and method of forming same | |
CN103594447B (zh) | 封装密度大高频性能好的ic芯片堆叠封装件及制造方法 | |
CN102231372B (zh) | 多圈排列无载体ic芯片封装件及其生产方法 | |
CN107564872A (zh) | 一种具备高散热扇出型封装结构的芯片及其制作方法 | |
CN103887256A (zh) | 一种高散热芯片嵌入式电磁屏蔽封装结构及其制作方法 | |
CN102231376B (zh) | 多圈排列无载体双ic芯片封装件及其生产方法 | |
CN102222658B (zh) | 多圈排列ic芯片封装件及其生产方法 | |
CN207559959U (zh) | 声表面波器件气密性晶圆级封装结构 | |
CN203895460U (zh) | 一种封装结构 | |
JP4626445B2 (ja) | 半導体パッケージの製造方法 | |
CN102651323B (zh) | 半导体封装结构的制法 | |
CN108598046A (zh) | 芯片的封装结构及其封装方法 | |
KR20080086178A (ko) | 스택 패키지 제조 방법 | |
CN108573933A (zh) | 半导体装置及其制造方法 | |
CN203573977U (zh) | 封装密度大高频性能好的ic芯片堆叠封装件 | |
CN103208467A (zh) | 内嵌封装体的封装模块及其制造方法 | |
CN202196776U (zh) | 一种扁平无载体无引线引脚外露封装件 | |
KR100656476B1 (ko) | 접속 강도를 높인 시스템 인 패키지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170802 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
|
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220113 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |