US20140141572A1 - Semiconductor assemblies with multi-level substrates and associated methods of manufacturing - Google Patents
Semiconductor assemblies with multi-level substrates and associated methods of manufacturing Download PDFInfo
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- US20140141572A1 US20140141572A1 US14/165,855 US201414165855A US2014141572A1 US 20140141572 A1 US20140141572 A1 US 20140141572A1 US 201414165855 A US201414165855 A US 201414165855A US 2014141572 A1 US2014141572 A1 US 2014141572A1
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Definitions
- the present disclosure is related to semiconductor assemblies with multi-level substrates and associated methods of manufacturing.
- FIG. 1A is a cross-sectional view of a BOC semiconductor assembly in accordance with the prior art.
- the semiconductor assembly 100 includes a substrate 102 , a semiconductor die 104 attached to the substrate 102 with an adhesive 106 , and an encapsulant 108 encapsulating the semiconductor die 104 and at least a portion of the substrate 102 .
- the substrate 102 includes a first side 102 a proximate the semiconductor die 104 , a second side 102 b opposite the first side 102 a, and an opening 118 between the first and second sides 102 a and 102 b.
- the opening 118 exposes a connection region 110 on the semiconductor die 104 .
- a plurality of traces 112 are located on the second side 102 b of the substrate 102 and are electrically connected to the connection region 110 via a plurality of wirebonds 114 .
- a plurality of electrical couplers 116 e.g., solder balls are attached to ball sites on the substrate 102 .
- FIG. 1B is a bottom view of the semiconductor assembly 100 of FIG. 1A
- FIG. 1C is an enlarged view of a portion of the semiconductor assembly 100 shown in FIG. 1B
- the semiconductor die 104 can include a plurality of bond sites 119 in the connection region 110 .
- the individual bond sites 119 are coupled to corresponding terminals 113 of the individual traces 112 on the semiconductor substrate 102 via the wirebonds 114 .
- the plurality of traces 112 fan out from the terminals 113 to contact corresponding ball pads 120 .
- FIG. 1A illustrates a BOC semiconductor assembly in accordance with the prior art.
- FIG. 1B is a bottom view of the BOC semiconductor assembly of FIG. 1A .
- FIG. 1C is an enlarged view of the BOC shown in FIG. 1B .
- FIG. 2A illustrates a BOC semiconductor assembly with a multi-level substrate in accordance with embodiments of the present technology.
- FIGS. 2B and 2C are plan views of first and second substrate levels, respectively, of the multi-level substrate shown in FIG. 2A .
- FIGS. 3A and 3B illustrate a process of forming the multi-level substrate shown in FIG. 2A , in accordance with embodiments of the technology.
- FIG. 4A illustrates a BOC semiconductor assembly with a multi-level substrate in accordance with additional embodiments of the present technology.
- FIGS. 4B and 4C are plan views of first and second substrate levels of the multi-level substrate shown in FIG. 4A .
- FIGS. 5 and 6 illustrate BOC semiconductor assemblies with a multi-level substrate in accordance with further embodiments of the present technology.
- Typical semiconductor assemblies or packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates.
- Substrates can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces.
- semiconductor pieces e.g., doped silicon wafers or gallium arsenide wafers
- non-conductive pieces e.g., various ceramic substrates
- conductive pieces e.g., various ceramic substrates
- FIG. 2A illustrates a BOC semiconductor assembly 200 with a multi-level substrate 202 configured in accordance with embodiments of the present technology.
- the semiconductor assembly 200 can include the multi-level substrate 202 , a semiconductor die 204 attached to the substrate 202 with an adhesive 206 , and an encapsulant 208 encapsulating the semiconductor die 204 and at least a portion of the substrate 202 .
- the semiconductor die 204 can include a memory die, a processor, and/or other suitable types of dies.
- the encapsulant 208 can include an epoxy and/or other suitable compositions. Even though a particular arrangement of the foregoing components is shown in FIG. 2A for illustration purposes, in other embodiments, the semiconductor die 204 may also be attached to the substrate 202 in a flip-chip configuration and/or other suitable configurations.
- the substrate 202 can include a first side 202 a proximate the semiconductor die 204 , a second side 202 b opposite the first side 202 a, and an opening 218 extending through the substrate 202 from the first side 202 a to the second side 202 b.
- the opening 218 exposes a connection region 210 on the semiconductor die 204 .
- the connection region includes bond sites 219 that are connected internally to structures within the semiconductor die 204 .
- the opening 218 may be omitted, for example, if the semiconductor die 204 is coupled to the substrate 202 in a flip-chip configuration.
- the substrate 202 includes a first routing level 211 , a second routing level 212 , and conductive vias 213 between the first and second routing levels 211 and 212 .
- the individual first and second routing levels 211 and 212 can be in generally parallel planes, and can include a trace, a plate, and/or other suitable routing structures.
- Individual conductive vias 213 can include a first end 213 a in contact with the first routing level 211 and a second end 213 b in contact with the second routing level 212 .
- a plurality of wirebonds 214 electrically connect individual bond sites 219 at the connection area 210 of the semiconductor die 204 to the first routing level 211 .
- the wirebonds 214 can also be connected to the second routing level 212 , as described in more detail below with reference to FIG. 4A .
- the substrate 202 may include three, four, or any other suitable number of routing levels in configurations generally similar to or different from that shown in FIG. 2A , depending upon the embodiment.
- the second ends 213 b of the individual vias 213 can be electrically connected to individual ball sites 224 via connectors 226 .
- the ball sites 224 can be configured as a ball grid array to receive a plurality of electrical couplers 216 (e.g., solder balls) as shown in FIG. 2A .
- FIGS. 2B and 2C are bottom views of the first and second routing levels 211 and 212 , respectively.
- the individual wirebonds 214 are electrically coupled between a terminal 215 of the individual trace 222 on the first routing level 211 and corresponding bond sites 219 in the connection region 210 .
- the individual traces 222 fan out from the terminals 215 to connect with the first ends 213 a of the conductive vias 213 .
- the second routing level 212 includes the second ends 213 b of the individual vias 213 , which are electrically connected to corresponding ball sites 224 with corresponding connectors 226 , as discussed above with reference to FIG. 2A .
- the bond sites 219 FIG.
- the wire bonds 214 and electrical couplers 216 can readily be connected to the substrate 202 from the same side of the substrate 202 .
- the first routing level 211 of the substrate 202 has a plurality of traces 222 that fan out to form a target pattern of the first ends 213 a of the conductive vias 213 .
- the illustrated first routing level 211 does not include any ball sites.
- the traces 222 can fan out without hindrance from the ball sites 224 because the ball sites 224 are on the second routing level 212 which is in a different plane than the plane containing the traces 222 .
- the traces 222 on the first routing level 211 can pass under or over any number of ball sites 224 without interference from the ball sites 224 because the ball sites 224 are on the second routing level 212 .
- embodiments of the substrate 202 can accommodate a large number of traces 222 and ball sites 224 even though the semiconductor die 204 has a small size.
- FIGS. 3A and 3B illustrate a process of forming the multi-level substrate 202 in FIG. 2A in accordance with embodiments of the technology.
- the process for forming the first routing level 211 and the second routing level 212 are shown side by side for illustration purposes. In certain embodiments these processing stages may be performed concurrently. In other embodiments these operating stages may be performed at least partially in series.
- the substrate material 302 includes a generally non-conductive core 301 with a first conductive material 304 a (e.g. copper) on a first side 301 a and a second conductive material 304 b on a second side 301 b.
- An initial stage 310 of forming the first routing level 211 can include stripping the first conductive material 304 a from the first side 301 a of the non-conductive core 301 .
- the second conductive material 304 b may be patterned and selectively removed from the second side 301 b of the non-conductive core 301 , forming the first routing level 211 .
- Preparing the second routing level 202 can include stripping the first conductive material 304 a from the first side 301 a of a separate non-conductive core 301 (stage 312 ) and patterning and selectively removing the second conductive material 304 b to form a targeted pattern for the second routing level 212 (stage 314 ).
- a solder mask 306 is formed over the second routing level 212 at stage 316 .
- the solder mask 306 may be omitted.
- Stage 316 can include removing a portion of the solder mask 306 and the generally non-conductive core 301 to form a portion of the opening 218 in the substrate 202 .
- the formed first and second routing levels 211 and 212 can then be generally aligned at stage 318 .
- the first routing level 211 and the second routing level 212 can be laminated together at stage 320 .
- Conductive vias 313 between the first and second routing levels 211 and 212 can be subsequently formed at stage 322 using through-substrate via forming techniques and/or other suitable techniques.
- the non-conductive core 301 of the first routing level 211 can be selectively removed to form another portion of the opening 218 in the substrate 202 at stage 324 .
- the semiconductor die 204 FIG. 2A
- the second routing level 212 can also include contact areas electrically coupled to the connection region 210 of the semiconductor die 204 .
- the second routing level 212 can include at least one contact area 230 electrically coupled to the connection region 210 of the semiconductor die 204 via a wirebond 215 .
- the first routing level 211 is shown divided into a first signal plane 232 and a second signal plane 234 in a side-by-side arrangement.
- the individual first and second signal planes 232 and 234 are electrically coupled to the connection region 210 with the wirebonds 214 .
- at least one of the first and second signal planes 232 , 234 can include a power plane, a ground plane, and/or other suitable signal planes that are electrically common to multiple terminals of the die 204 ( FIG. 4A ).
- the second routing level 212 can include a plurality of traces 236 that fan out from a plurality of terminals 235 into a plurality of ball sites 224 .
- the individual terminals 235 are electrically connected to the connection region 210 via the wirebonds 215 .
- the first and second routing levels 211 and 212 are connected with the conductive vias 213 , in a manner generally similar to that discussed above with reference to FIGS. 2A-2C .
- FIGS. 5 and 6 are cross-sectional views of BOC semiconductor assemblies 500 and 600 , respectively, configured in accordance with additional embodiments of the present technology.
- Embodiments of the semiconductor assemblies 500 and 600 can be generally similar to those shown in FIGS. 2A and 4A , respectively, except that the semiconductor assemblies 500 and 600 individually include a conductive material 240 between the substrate 202 and the semiconductor die 204 .
- the conductive material 240 can include a metal plate, a metal alloy plate, and/or other suitable materials and/or structures with sufficient thermal conductivity to conduct heat from the semiconductor die 202 .
- the conductive material 240 may be replaced with other suitable heat conducting components (e.g., Peltier elements) or may be omitted.
- the traces and the ball sites to which they connect can be located on different levels or strata of the substrate. This arrangement allows the designer greater flexibility when selecting the routes for the traces and the locations for the ball sites because the routes can follow paths that are independent of the ball site locations, so long as individual routes can be connected to the corresponding ball sites with vias, as described above.
- Another feature of at least some embodiments is that the ball sites on one level of the substrate and portions of the traces on another level of the substrate are both accessible from the same side or face of the substrate. This arrangement allows the manufacturer to access the traces for wirebonding and access the ball sites for depositing solder balls or other electrical couplers with the substrate facing the same direction.
- the two routing levels are initially formed on separate non-conductive cores, which are then joined.
- the conductive material on one side of each core is removed.
- portions of this conductive material can remain, e.g., to carry out additional routing functions.
- the traces and ball pads can have arrangements different than those specifically illustrated in the foregoing Figures.
- the materials described in the context of particular embodiments above can have different constituents and/or properties in other embodiments.
Abstract
Description
- This application is a divisional of U.S. application Ser. No. 13/206,321 filed Aug. 9, 2011, now U.S. Pat. No. 8,637,987, which is incorporated herein by reference.
- The present disclosure is related to semiconductor assemblies with multi-level substrates and associated methods of manufacturing.
- Board-on-chip (“BOC”) techniques have been used for packaging high speed memory components.
FIG. 1A is a cross-sectional view of a BOC semiconductor assembly in accordance with the prior art. As shown inFIG. 1A , thesemiconductor assembly 100 includes asubstrate 102, asemiconductor die 104 attached to thesubstrate 102 with anadhesive 106, and anencapsulant 108 encapsulating the semiconductor die 104 and at least a portion of thesubstrate 102. Thesubstrate 102 includes afirst side 102 a proximate the semiconductor die 104, asecond side 102 b opposite thefirst side 102 a, and anopening 118 between the first andsecond sides connection region 110 on the semiconductor die 104. A plurality oftraces 112 are located on thesecond side 102 b of thesubstrate 102 and are electrically connected to theconnection region 110 via a plurality ofwirebonds 114. A plurality of electrical couplers 116 (e.g., solder balls) are attached to ball sites on thesubstrate 102. -
FIG. 1B is a bottom view of thesemiconductor assembly 100 ofFIG. 1A , andFIG. 1C is an enlarged view of a portion of thesemiconductor assembly 100 shown inFIG. 1B . As shown inFIGS. 1B and 1C , the semiconductor die 104 can include a plurality ofbond sites 119 in theconnection region 110. Theindividual bond sites 119 are coupled tocorresponding terminals 113 of theindividual traces 112 on thesemiconductor substrate 102 via thewirebonds 114. As is clearly shown inFIGS. 1B and 1C , the plurality oftraces 112 fan out from theterminals 113 to contactcorresponding ball pads 120. - Over the course of time, manufacturers have made dies smaller and smaller to meet user demands. As the semiconductor dies 104 have become smaller, the number of
ball pads 120 and thetraces 112 required on thesubstrate 102 has increased such that thelarge ball pads 120 can interfere with routes of thetraces 112. One conventional solution for dealing with this problem is to use aggressive design rules and wire bond profiles to decrease the sizes of all features on both thesemiconductor die 102 and thesubstrate 104. However, such a conventional technique is still limited due to the number ofball pads 120 that are typically required. -
FIG. 1A illustrates a BOC semiconductor assembly in accordance with the prior art. -
FIG. 1B is a bottom view of the BOC semiconductor assembly ofFIG. 1A . -
FIG. 1C is an enlarged view of the BOC shown inFIG. 1B . -
FIG. 2A illustrates a BOC semiconductor assembly with a multi-level substrate in accordance with embodiments of the present technology. -
FIGS. 2B and 2C are plan views of first and second substrate levels, respectively, of the multi-level substrate shown inFIG. 2A . -
FIGS. 3A and 3B illustrate a process of forming the multi-level substrate shown inFIG. 2A , in accordance with embodiments of the technology. -
FIG. 4A illustrates a BOC semiconductor assembly with a multi-level substrate in accordance with additional embodiments of the present technology. -
FIGS. 4B and 4C are plan views of first and second substrate levels of the multi-level substrate shown inFIG. 4A . -
FIGS. 5 and 6 illustrate BOC semiconductor assemblies with a multi-level substrate in accordance with further embodiments of the present technology. - Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. Typical semiconductor assemblies or packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates. Substrates can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to
FIGS. 2A-6 . -
FIG. 2A illustrates aBOC semiconductor assembly 200 with amulti-level substrate 202 configured in accordance with embodiments of the present technology. As shown inFIG. 2A , thesemiconductor assembly 200 can include themulti-level substrate 202, asemiconductor die 204 attached to thesubstrate 202 with anadhesive 206, and anencapsulant 208 encapsulating thesemiconductor die 204 and at least a portion of thesubstrate 202. Thesemiconductor die 204 can include a memory die, a processor, and/or other suitable types of dies. The encapsulant 208 can include an epoxy and/or other suitable compositions. Even though a particular arrangement of the foregoing components is shown inFIG. 2A for illustration purposes, in other embodiments, the semiconductor die 204 may also be attached to thesubstrate 202 in a flip-chip configuration and/or other suitable configurations. - In the illustrated embodiment, the
substrate 202 can include afirst side 202 a proximate the semiconductor die 204, asecond side 202 b opposite thefirst side 202 a, and anopening 218 extending through thesubstrate 202 from thefirst side 202 a to thesecond side 202 b. Theopening 218 exposes aconnection region 210 on the semiconductor die 204. The connection region includesbond sites 219 that are connected internally to structures within the semiconductor die 204. In other embodiments, theopening 218 may be omitted, for example, if the semiconductor die 204 is coupled to thesubstrate 202 in a flip-chip configuration. - As shown in
FIG. 2A , thesubstrate 202 includes afirst routing level 211, asecond routing level 212, andconductive vias 213 between the first andsecond routing levels second routing levels conductive vias 213 can include afirst end 213 a in contact with thefirst routing level 211 and asecond end 213 b in contact with thesecond routing level 212. In the illustrated embodiment, a plurality ofwirebonds 214 electrically connectindividual bond sites 219 at theconnection area 210 of the semiconductor die 204 to thefirst routing level 211. In other embodiments, at least some of thewirebonds 214 can also be connected to thesecond routing level 212, as described in more detail below with reference toFIG. 4A . In further embodiments, thesubstrate 202 may include three, four, or any other suitable number of routing levels in configurations generally similar to or different from that shown inFIG. 2A , depending upon the embodiment. In any of these embodiments, the second ends 213 b of theindividual vias 213 can be electrically connected toindividual ball sites 224 viaconnectors 226. Theball sites 224 can be configured as a ball grid array to receive a plurality of electrical couplers 216 (e.g., solder balls) as shown inFIG. 2A . -
FIGS. 2B and 2C are bottom views of the first andsecond routing levels FIG. 2B , theindividual wirebonds 214 are electrically coupled between a terminal 215 of theindividual trace 222 on thefirst routing level 211 andcorresponding bond sites 219 in theconnection region 210. The individual traces 222 fan out from theterminals 215 to connect with the first ends 213 a of theconductive vias 213. As shown inFIG. 2C , thesecond routing level 212 includes the second ends 213 b of theindividual vias 213, which are electrically connected to correspondingball sites 224 withcorresponding connectors 226, as discussed above with reference toFIG. 2A . The bond sites 219 (FIG. 2B ) and the ball sites 224 (FIG. 2A ) can be accessible from the same side (e.g., the same major surface) of thesubstrate 202, as shown inFIG. 2A . As a result, and with continued reference toFIG. 2A , thewire bonds 214 and electrical couplers 216 (e.g., solder balls) can readily be connected to thesubstrate 202 from the same side of thesubstrate 202. - As shown in
FIGS. 2B and 2C , thefirst routing level 211 of thesubstrate 202 has a plurality oftraces 222 that fan out to form a target pattern of the first ends 213 a of theconductive vias 213. The illustratedfirst routing level 211 does not include any ball sites. As a result, thetraces 222 can fan out without hindrance from theball sites 224 because theball sites 224 are on thesecond routing level 212 which is in a different plane than the plane containing thetraces 222. In other words, thetraces 222 on thefirst routing level 211 can pass under or over any number ofball sites 224 without interference from theball sites 224 because theball sites 224 are on thesecond routing level 212. As a result, embodiments of thesubstrate 202 can accommodate a large number oftraces 222 andball sites 224 even though the semiconductor die 204 has a small size. -
FIGS. 3A and 3B illustrate a process of forming themulti-level substrate 202 inFIG. 2A in accordance with embodiments of the technology. As shown inFIG. 3A , the process for forming thefirst routing level 211 and thesecond routing level 212 are shown side by side for illustration purposes. In certain embodiments these processing stages may be performed concurrently. In other embodiments these operating stages may be performed at least partially in series. - As shown in
FIG. 3A , separate pieces or elements of asubstrate material 302 are used to form the first and second routing levels, respectively. Thesubstrate material 302 includes a generallynon-conductive core 301 with a firstconductive material 304 a (e.g. copper) on afirst side 301 a and a secondconductive material 304 b on asecond side 301 b. Aninitial stage 310 of forming thefirst routing level 211 can include stripping the firstconductive material 304 a from thefirst side 301 a of thenon-conductive core 301. Subsequently, the secondconductive material 304 b may be patterned and selectively removed from thesecond side 301 b of thenon-conductive core 301, forming thefirst routing level 211. - Preparing the
second routing level 202 can include stripping the firstconductive material 304 a from thefirst side 301 a of a separate non-conductive core 301 (stage 312) and patterning and selectively removing the secondconductive material 304 b to form a targeted pattern for the second routing level 212 (stage 314). As shown inFIG. 3A , asolder mask 306 is formed over thesecond routing level 212 atstage 316. In other embodiments thesolder mask 306 may be omitted.Stage 316 can include removing a portion of thesolder mask 306 and the generallynon-conductive core 301 to form a portion of theopening 218 in thesubstrate 202. The formed first andsecond routing levels stage 318. - As shown in
FIG. 3B , thefirst routing level 211 and thesecond routing level 212 can be laminated together atstage 320.Conductive vias 313 between the first andsecond routing levels stage 322 using through-substrate via forming techniques and/or other suitable techniques. Subsequently, thenon-conductive core 301 of thefirst routing level 211 can be selectively removed to form another portion of theopening 218 in thesubstrate 202 atstage 324. Subsequently, the semiconductor die 204 (FIG. 2A ) can be attached to thesubstrate 202 and subsequently encapsulated withencapsulant 218 according to conventional techniques for BOC packaging. - Even though the
wirebonds 214 are shown inFIG. 2A as extending between theconnection region 210 of the semiconductor die 204 and thefirst routing level 211, in other embodiments thesecond routing level 212 can also include contact areas electrically coupled to theconnection region 210 of the semiconductor die 204. For example, as shown inFIG. 4A , thesecond routing level 212 can include at least onecontact area 230 electrically coupled to theconnection region 210 of the semiconductor die 204 via awirebond 215. - As shown in
FIG. 4B , thefirst routing level 211 is shown divided into afirst signal plane 232 and asecond signal plane 234 in a side-by-side arrangement. The individual first and second signal planes 232 and 234 are electrically coupled to theconnection region 210 with the wirebonds 214. In certain embodiments, at least one of the first and second signal planes 232, 234 can include a power plane, a ground plane, and/or other suitable signal planes that are electrically common to multiple terminals of the die 204 (FIG. 4A ). As shown inFIG. 4C , thesecond routing level 212 can include a plurality oftraces 236 that fan out from a plurality ofterminals 235 into a plurality ofball sites 224. Theindividual terminals 235 are electrically connected to theconnection region 210 via thewirebonds 215. The first andsecond routing levels conductive vias 213, in a manner generally similar to that discussed above with reference toFIGS. 2A-2C . -
FIGS. 5 and 6 are cross-sectional views ofBOC semiconductor assemblies semiconductor assemblies FIGS. 2A and 4A , respectively, except that thesemiconductor assemblies conductive material 240 between thesubstrate 202 and the semiconductor die 204. Theconductive material 240 can include a metal plate, a metal alloy plate, and/or other suitable materials and/or structures with sufficient thermal conductivity to conduct heat from the semiconductor die 202. In further embodiments, theconductive material 240 may be replaced with other suitable heat conducting components (e.g., Peltier elements) or may be omitted. - One feature of several of the foregoing embodiments is that the traces and the ball sites to which they connect can be located on different levels or strata of the substrate. This arrangement allows the designer greater flexibility when selecting the routes for the traces and the locations for the ball sites because the routes can follow paths that are independent of the ball site locations, so long as individual routes can be connected to the corresponding ball sites with vias, as described above. Another feature of at least some embodiments is that the ball sites on one level of the substrate and portions of the traces on another level of the substrate are both accessible from the same side or face of the substrate. This arrangement allows the manufacturer to access the traces for wirebonding and access the ball sites for depositing solder balls or other electrical couplers with the substrate facing the same direction.
- From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. For example, in an embodiment shown in
FIG. 3A , the two routing levels are initially formed on separate non-conductive cores, which are then joined. As part of this process, the conductive material on one side of each core is removed. In other embodiments, portions of this conductive material can remain, e.g., to carry out additional routing functions. The traces and ball pads can have arrangements different than those specifically illustrated in the foregoing Figures. The materials described in the context of particular embodiments above can have different constituents and/or properties in other embodiments. - Certain aspects of the technology described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments of the invention have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the invention. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
Claims (11)
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US9912448B2 (en) * | 2012-02-13 | 2018-03-06 | Sentinel Connector Systems, Inc. | Testing apparatus for a high speed communications jack and methods of operating the same |
WO2015148388A1 (en) * | 2014-03-24 | 2015-10-01 | Sentinel Connector Systems, Inc. | Testing apparatus for a high speed cross over communications jack and methods of operating the same |
WO2015148386A1 (en) * | 2014-03-24 | 2015-10-01 | Sentinel Connector Systems, Inc. | Testing apparatus for a high speed communications jack and methods of operating the same |
US9761562B2 (en) | 2015-05-06 | 2017-09-12 | Micron Technology, Inc. | Semiconductor device packages including a controller element |
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US6773965B2 (en) * | 1999-05-25 | 2004-08-10 | Micron Technology, Inc. | Semiconductor device, ball grid array connection system, and method of making |
US6430058B1 (en) | 1999-12-02 | 2002-08-06 | Intel Corporation | Integrated circuit package |
US7107561B2 (en) | 2004-08-09 | 2006-09-12 | Lsi Logic Corporation | Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits |
US7217994B2 (en) | 2004-12-01 | 2007-05-15 | Kyocera Wireless Corp. | Stack package for high density integrated circuits |
US7401313B2 (en) | 2005-10-26 | 2008-07-15 | Lsi Corporation | Method and apparatus for controlling congestion during integrated circuit design resynthesis |
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