TWI743118B - High speed communication jack - Google Patents

High speed communication jack Download PDF

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TWI743118B
TWI743118B TW106114632A TW106114632A TWI743118B TW I743118 B TWI743118 B TW I743118B TW 106114632 A TW106114632 A TW 106114632A TW 106114632 A TW106114632 A TW 106114632A TW I743118 B TWI743118 B TW I743118B
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layer
socket
holes
signal
shielding
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TW106114632A
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TW201813215A (en
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布瑞特 D. 羅賓森
賈斯汀 瓦格納
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美商哨兵連接器系統股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461Means for preventing cross-talk
    • H01R13/6464Means for preventing cross-talk by adding capacitive elements
    • H01R13/6466Means for preventing cross-talk by adding capacitive elements on substrates, e.g. printed circuit boards [PCB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6473Impedance matching
    • H01R13/6474Impedance matching by variation of conductive properties, e.g. by dimension variations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/648Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding  
    • H01R13/658High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse]
    • H01R13/6581Shield structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66Structural association with built-in electrical component
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66Structural association with built-in electrical component
    • H01R13/665Structural association with built-in electrical component with built-in electronic circuit
    • H01R13/6658Structural association with built-in electrical component with built-in electronic circuit on printed circuit board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R24/00Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
    • H01R24/60Contacts spaced along planar side wall transverse to longitudinal axis of engagement
    • H01R24/62Sliding engagements with one side only, e.g. modular jack coupling devices
    • H01R24/64Sliding engagements with one side only, e.g. modular jack coupling devices for high frequency, e.g. RJ 45
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0277Bendability or stretchability details
    • H05K1/028Bending or folding regions of flexible printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R2107/00Four or more poles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05Flexible printed circuits [FPCs]
    • H05K2201/056Folded around rigid support or component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/09336Signal conductors in same plane as power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10295Metallic connector elements partly mounted in a hole of the PCB
    • H05K2201/10303Pin-in-hole mounted pins

Abstract

A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, forming a shielding case surrounding the housing, forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing.

Description

高速通訊插座High-speed communication socket

參考相關申請案 此揭示為提申日期2014年10月1日名稱「高速通訊插座」的美國專利申請案第14/504,088號的部分連續案,該案請求提申日期2013年1月11日名稱「高速通訊插座」的美國專利案第8,858,266號的優先權,二案全文爰引於此並融入本說明書之揭示。With reference to the related application, this disclosure is a partial continuation of the U.S. Patent Application No. 14/504,088 named "High Speed Communication Socket" dated October 1, 2014, and the request date of the application date is January 11, 2013. The priority of US Patent No. 8,858,266 for "High Speed Communication Socket", the full text of the second case is quoted here and incorporated into the disclosure of this specification.

發明領域 此揭示係有關於使用來連結網路電纜至裝置的網路連結插座。FIELD OF THE INVENTION This disclosure relates to a network connection socket used to connect a network cable to a device.

發明背景 隨著電氣通訊裝置及其相關聯的應用變得愈來愈複雜及威力強大,其收集資訊且與其它裝置分享資訊的能力也變得更重要。此等智慧型互聯網裝置的激增已經導致連結的網路上需要有增高的資料通量以提供滿足此項需求需要的改良資料率。結果,經常性地改良現有通訊協定標準或產生新標準。幾乎全部此等標準皆直接地或間接地要求或從透過有線網路的高解析度信號的通訊而顯著獲益。此等高解析度信號,其可具有較大頻寬,及補償地可具有較高頻率要求,須以一致方式支援。然而,即便各項標準的較為晚近版本提供理論上的較高資料率或速度,其速度仍受某些實體組件的目前設計所限。不幸地,此等實體組件的設計仍受困於缺乏瞭解達成數十億赫茲及更高頻率的一致信號品質需要什麼條件。BACKGROUND OF THE INVENTION As electrical communication devices and their associated applications become more complex and powerful, their ability to collect information and share information with other devices has also become more important. The proliferation of these smart Internet devices has led to the need for increased data throughput on connected networks to provide improved data rates to meet this demand. As a result, the existing communication protocol standards are constantly improved or new standards are created. Almost all of these standards directly or indirectly require or benefit significantly from the communication of high-resolution signals via wired networks. These high-resolution signals, which may have a larger bandwidth, and the compensation ground may have higher frequency requirements, must be supported in a consistent manner. However, even if the more recent versions of the standards provide theoretically higher data rates or speeds, their speed is still limited by the current design of certain physical components. Unfortunately, the design of these physical components still suffers from a lack of understanding of what is required to achieve consistent signal quality at billions of hertz and higher frequencies.

舉例言之,通訊插座使用於通訊裝置及裝備用於使用來發射及接收表示通訊資料的電氣信號的電纜之連結或耦合。註冊插座(RJ)乃用於連結電信及資料裝備的標準化實體介面。RJ標準化實體介面包括插座構造及布線圖案兩者。常用於資料裝備的RJ標準化實體介面為RJ45實體網路介面,又稱RJ45插座。RJ45插座廣泛使用於本地區域網路,諸如實施美國電機及電子工程師學會(IEEE)802.3乙太網路協定者。RJ45插座係以各種標準描述,包括由美國國家標準學會(ANSI)/美國電信工業協會(TIA)於ANSI/TIA-1096-A中頒布者。For example, communication sockets are used in communication devices and equipment for the connection or coupling of cables used to transmit and receive electrical signals representing communication data. Registered socket (RJ) is a standardized physical interface used to connect telecommunications and data equipment. The RJ standardized physical interface includes both socket structure and wiring pattern. The RJ standardized physical interface commonly used in data equipment is the RJ45 physical network interface, also known as the RJ45 socket. RJ45 sockets are widely used in local area networks, such as those that implement the IEEE 802.3 Ethernet protocol. RJ45 sockets are described in various standards, including those promulgated by the American National Standards Institute (ANSI)/American Telecommunications Industry Association (TIA) in ANSI/TIA-1096-A.

全部電氣介面組件,諸如電纜及插座,包括RJ45插座,不僅抵抗電流的初始流動,同時也對抗對其做任何改變。此項性質稱作電抗。兩型相關電抗為電感電抗及電容電抗。電感電抗例如可基於電流流經抵抗的電纜移動而產生,其引發磁場而於電纜中感應電壓。另一方面,電容電抗係當來自二相對表面的電子一起接近放置時由出現的靜電荷所產生。All electrical interface components, such as cables and sockets, including RJ45 sockets, not only resist the initial flow of current, but also resist any changes to it. This property is called reactance. The two types of related reactance are inductive reactance and capacitive reactance. Inductive reactance can be generated based on the movement of a current through a resisting cable, for example, which induces a magnetic field to induce a voltage in the cable. On the other hand, capacitive reactance is generated by electrostatic charges that appear when electrons from two opposing surfaces are placed close together.

為了減少或避免發射信號之任何降級,通訊電路的各種組件較佳地具有匹配阻抗。若否,則具有一個阻抗值的負載將以不同阻抗位準反射或回波由電纜所攜載的部分信號,造成信號故障。因此理由故,資料通訊裝備設計師及製造商,諸如電纜販售商,設計及測試其電纜以驗證電纜的阻抗值,以及電阻及電容位準遵照某些效能參數。RJ45插座也是接近每個通訊電路的顯著組件,然而,插座製造商並未對其效能提供相同程度的注意。如此,雖然現有RJ45插座的相關問題於測試中已有明確記載及瞭解其對高頻信號線的負面影響,但業界似乎不情願解決實體層之此種重要組件的問題。結果,需要有改良的高速通訊插座。In order to reduce or avoid any degradation of the transmitted signal, various components of the communication circuit preferably have matching impedances. If not, a load with one impedance value will reflect or echo part of the signal carried by the cable at different impedance levels, causing signal failure. For this reason, data communication equipment designers and manufacturers, such as cable vendors, design and test their cables to verify the impedance values of the cables, as well as the resistance and capacitance levels to comply with certain performance parameters. The RJ45 socket is also a significant component close to every communication circuit, however, socket manufacturers have not paid the same degree of attention to its performance. In this way, although the related problems of the existing RJ45 socket have been clearly documented in the test and the negative impact on the high-frequency signal line is understood, the industry seems reluctant to solve the problem of such an important component of the physical layer. As a result, there is a need for improved high-speed communication sockets.

發明概要 本發明之一個實施例包括一高速通訊插座包括一殼體其包括用於接納一插頭的一埠口,該埠口包括各自連結至該插頭中之一對應信號線的多數針腳,包圍該殼體的一屏蔽外殼,於該殼體中之一電路板具有一基體,延伸貫穿該基體的多數第一通孔而各個第一通孔係經組配以容納該殼體上的一針腳,延伸貫穿該基體的多數第二通孔而各個第二通孔係經組配以容納該殼體上的一針腳,於該基體之一頂層上的一第一集合之線跡其連結至少一個第一通孔與至少一個對應第二通孔,於該基體中之該頂層之一第一側上的一第一屏蔽層,於該基體中相鄰該第一屏蔽層的一第二屏蔽層及於該基體之與該頂層之一相對側上的一第二集合之線跡其連結至少一個第一通孔與至少一個第二通孔。SUMMARY OF THE INVENTION One embodiment of the present invention includes a high-speed communication socket including a housing including a port for receiving a plug. The port includes a plurality of pins each connected to a corresponding signal line in the plug, surrounding the A shielding shell of the housing, a circuit board in the housing has a base, extending through a plurality of first through holes of the base, and each of the first through holes is assembled to accommodate a pin on the housing, A plurality of second through holes extending through the base body and each second through hole is assembled to accommodate a stitch on the housing, and a first set of stitches on a top layer of the base body connects at least one first through hole A through hole and at least one corresponding second through hole, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent to the first shielding layer in the substrate, and A second set of stitches on an opposite side of the base body and the top layer connects at least one first through hole and at least one second through hole.

於另一實施例中,該第二集合之線跡連結不同通孔而該等通孔連結至該頂面上。In another embodiment, the stitches of the second set connect different through holes and the through holes are connected to the top surface.

於另一實施例中,該插座包括在該頂面上介於一第一集合之線跡間的一第一隔離區。In another embodiment, the socket includes a first isolation region on the top surface between a first set of traces.

於另一實施例中,該插座包括在該頂面上介於一第二集合之線跡間的一第二隔離區。In another embodiment, the socket includes a second isolation region on the top surface between the traces of a second set.

於另一實施例中,該第一屏蔽層係被覆蓋於一導電材料中。In another embodiment, the first shielding layer is covered in a conductive material.

於另一實施例中,該導電材料不覆蓋環繞該等第一通孔及第二通孔之該周邊的一區。In another embodiment, the conductive material does not cover an area surrounding the periphery of the first through holes and the second through holes.

於另一實施例中,該第二屏蔽層係被覆蓋於一導電材料中。In another embodiment, the second shielding layer is covered in a conductive material.

於另一實施例中,該導電材料不覆蓋環繞該等第一通孔及第二通孔之該周邊的一區。In another embodiment, the conductive material does not cover an area surrounding the periphery of the first through holes and the second through holes.

於另一實施例中,該導電材料係包含銅及精加工銀。In another embodiment, the conductive material includes copper and refined silver.

於另一實施例中,該導電材料係包含銅及精加工銀。In another embodiment, the conductive material includes copper and refined silver.

本發明之另一個實施例包括一製造一高速通訊插座之方法,該方法包括下列步驟:形成包括用於接納一插頭的一埠口的一殼體,該埠口包括多數針腳其各自連結至該插頭中之一對應信號線,形成環繞該殼體的一屏蔽外殼,形成一基體的一頂層,於該基體中之該頂層之一第一側上的一第一屏蔽層,相鄰該基體中之該第一屏蔽層的一第二屏蔽層,及形成相鄰該第二屏蔽層的一底層,形成延伸貫穿該基體的多數第一通孔而各個第一通孔係經組配以容納該殼體上的一針腳,形成延伸貫穿該基體的多數第二通孔而各個第二通孔係經組配以容納該殼體上的一針腳,於該基體之一頂層上形成一第一集合之線跡其連結至少一個第一通孔與至少一個對應第二通孔,於該基體之與該頂層之一相對側上形成一第二集合之線跡其連結至少一個第一通孔與至少一個第二通孔。Another embodiment of the present invention includes a method of manufacturing a high-speed communication socket. The method includes the following steps: forming a housing including a port for receiving a plug, the port including a plurality of pins each connected to the One of the plugs corresponds to the signal line, forming a shielding shell surrounding the housing, forming a top layer of a base, and a first shielding layer on a first side of the top layer in the base is adjacent to the base A second shielding layer of the first shielding layer and a bottom layer adjacent to the second shielding layer form a plurality of first through holes extending through the substrate, and each first through hole is configured to accommodate the A pin on the housing forms a plurality of second through holes extending through the base, and each second through hole is assembled to accommodate a pin on the housing, forming a first set on a top layer of the base The stitches connect at least one first through hole and at least one corresponding second through hole, and a second set of stitches are formed on an opposite side of the substrate and the top layer, which connects at least one first through hole and at least A second through hole.

於另一實施例中,該第二集合之線跡連結不同通孔而該等通孔連結至該頂面上。In another embodiment, the stitches of the second set connect different through holes and the through holes are connected to the top surface.

於另一實施例中,該方法包括在該頂面上介於一第一集合之線跡間形成一第一隔離區之該步驟。In another embodiment, the method includes the step of forming a first isolation region between a first set of traces on the top surface.

於另一實施例中,該方法包括在該頂面上介於一第二集合之線跡間形成一第二隔離區之該步驟。In another embodiment, the method includes the step of forming a second isolation region between the traces of a second set on the top surface.

於另一實施例中,該第一屏蔽層係被覆蓋於一導電材料中。In another embodiment, the first shielding layer is covered in a conductive material.

於另一實施例中,該導電材料不覆蓋環繞該等第一通孔及第二通孔之該周邊的一區。In another embodiment, the conductive material does not cover an area surrounding the periphery of the first through holes and the second through holes.

於另一實施例中,該第二屏蔽層係被覆蓋於一導電材料中。In another embodiment, the second shielding layer is covered in a conductive material.

於另一實施例中,該導電材料不覆蓋環繞該等第一通孔及第二通孔之該周邊的一區。In another embodiment, the conductive material does not cover an area surrounding the periphery of the first through holes and the second through holes.

於另一實施例中,該導電材料係包含銅及精加工銀。In another embodiment, the conductive material includes copper and refined silver.

於另一實施例中,該導電材料係包含銅及精加工銀。In another embodiment, the conductive material includes copper and refined silver.

較佳實施例之詳細說明 圖1例示依據本揭示之各個面向的一個實施例組配的高速通訊插座其包括RJ45插座110、可撓性印刷電路板(PCB)120、及插座罩130。如於本文中描述,依據本揭示之各個面向,可撓性PCB 120提供其可直接焊接至RJ45插座110之各個針腳上的平衡射頻調諧電路,而插座罩130提供RJ45插座110及可撓性PCB 120的屏蔽,以及作為接地底座。RJ45插座110、可撓性PCB 120、及插座罩130組合時可提供類似調諧波導的功能及通訊信號可通過其中傳輸的一管,於該處通訊信號之能量部分於該管外部行進通過插座罩130;及通訊信號之資訊部分於該管內部沿無電阻金線行進;藉此允許獲得高速資料信號速度。舉例言之,預期可支援40十億位元(Gb)及以上的資料速度。Detailed Description of the Preferred Embodiment FIG. 1 illustrates a high-speed communication socket assembled according to an embodiment of various aspects of the present disclosure, which includes an RJ45 socket 110, a flexible printed circuit board (PCB) 120, and a socket cover 130. As described herein, according to various aspects of the present disclosure, the flexible PCB 120 provides a balanced radio frequency tuning circuit that can be directly soldered to each pin of the RJ45 socket 110, and the socket cover 130 provides the RJ45 socket 110 and the flexible PCB 120 shielding, and as a grounding base. When the RJ45 socket 110, the flexible PCB 120, and the socket cover 130 are combined, they can provide a function similar to a tuning waveguide and a tube through which communication signals can be transmitted, where the energy part of the communication signal travels outside the tube through the socket cover 130; and the information part of the communication signal travels along the non-resistance gold wire inside the tube; thereby allowing high-speed data signal speed to be obtained. For example, it is expected to support data speeds of 40 gigabit (Gb) and above.

雖然以下使用RJ45通訊插座,但本通訊插座並不限於RJ45通訊插座及可使用於任何類型的高速通訊插座,包括全部類別的模組式RJ型連接器、通用串列匯流排(USB)連接器及插座、火線(Firewire)(1394)連接器及插座、高畫質多媒體介面(HDMI)連接器及插座、D-次迷你型連接器及插座、帶型連接器及插座、或接收高速通訊信號的任何其它連接器及插座。Although RJ45 communication sockets are used below, this communication socket is not limited to RJ45 communication sockets and can be used for any type of high-speed communication sockets, including all types of modular RJ connectors and universal serial bus (USB) connectors And sockets, Firewire (1394) connectors and sockets, high-definition multimedia interface (HDMI) connectors and sockets, D-subminiature connectors and sockets, ribbon connectors and sockets, or receive high-speed communication signals Any other connectors and sockets.

於本揭示之各個面向中,此處揭示的各種針腳及線跡可由任何合宜導電元素組成,諸如金、銀、或銅、或合金及任何導電元素之組合。舉例言之,RJ45插座110之針腳與插頭接頭的集合可包括鍍金銅針腳或導線,而可撓性PCB 120之線跡的集合可包括鍍金銅路徑。鍍金係用來於銅上提供防蝕導電層,其通常為容易氧化的材料。另外,一層合宜障壁金屬,諸如鎳,可在施加金鍍覆之前沈積於銅基體上。鎳層藉由給金層提供機械背襯而改良金鍍覆的耐磨性。鎳層也可減少可能存在於金層中之孔徑的影響。於較高頻率,金鍍覆可能不僅減少信號損耗,同時也可增加來自蒙皮效應的頻寬,於該處於導體外緣上的電流密度為最高。相反地,單獨使用鎳將因相同效應所致導致較高頻率的信號降級。如此,單獨使用鎳鍍覆的RJ45插座中可能無法達成較高速度。舉例言之,只以鎳鍍覆的針腳或線跡一旦信號進入GHz範圍可能其有用信號長度縮短高達三倍,雖然此處已經描述於銅路徑上方使用金鍍覆的若干好處,但可使用其它導電元素來鍍覆銅路徑。舉例言之,鉑也是非反應性但屬良好導體,可使用鉑替代金來鍍覆銅路徑。In all aspects of the present disclosure, the various pins and traces disclosed herein can be composed of any suitable conductive elements, such as gold, silver, or copper, or alloys and any combination of conductive elements. For example, the set of pins and plug connectors of the RJ45 socket 110 may include gold-plated copper pins or wires, and the set of traces of the flexible PCB 120 may include gold-plated copper paths. Gold plating is used to provide an anti-corrosion conductive layer on copper, which is usually a material that is easily oxidized. In addition, a layer of suitable barrier metal, such as nickel, can be deposited on the copper substrate before applying the gold plating. The nickel layer improves the wear resistance of gold plating by providing a mechanical backing to the gold layer. The nickel layer can also reduce the influence of the pore size that may be present in the gold layer. At higher frequencies, gold plating may not only reduce signal loss, but also increase the bandwidth from the skin effect, where the current density on the outer edge of the conductor is the highest. Conversely, the use of nickel alone will cause higher frequency signal degradation due to the same effect. As such, it may not be possible to achieve higher speeds in RJ45 sockets that use nickel plating alone. For example, a pin or trace that is only plated with nickel may shorten the useful signal length by as much as three times once the signal enters the GHz range. Although the benefits of using gold plating on the copper path have been described here, others can be used. Conductive elements to plate the copper path. For example, platinum is also non-reactive but a good conductor, and platinum can be used instead of gold to plate copper paths.

高速通訊插座的主要組件亦即,RJ45插座110、可撓性印刷電路板(PCB)120、及插座罩130各自將在討論此等組件如何互動以達成支援高速通訊之前在此提供簡單說明。The main components of the high-speed communication socket, namely, the RJ45 socket 110, the flexible printed circuit board (PCB) 120, and the socket cover 130 will each provide a brief description here before discussing how these components interact to support high-speed communication.

圖2例示圖1之RJ45插座110的前部之底視透視圖,於該處可見設有插頭開口230用於插入插頭(未顯示於圖中)。插頭開口230可經組配以接納插頭以將插頭上的接點耦合至RJ45插座110中之插頭接點之集合212。插頭可以是RJ45 8位置8接點(8P8C)模組式插頭。插頭接點之集合212係形成為經組配以附接至電路板上的通訊電路之針腳之集合210。舉例言之,RJ45插座110可透過一對柱220的使用而安裝至網路切換裝置的電路板,及然後針腳之集合210可焊接至裝置之電路板上的個別接觸襯墊。藉其自身,類似如圖2中例示的RJ45插座110之插座提供RJ45電纜之插頭與插座整合入其中的裝置之電路板間的基本連接性。然而,該插座並非設計來處理高速通訊需要的通訊頻率。如依據如於本文中描述的揭示辦法之各個面向組配的RJ45插座110可整合其它組件諸如插座罩130及可撓性PCB 120,使得其可使用來以較高速度通訊而不干擾瞬態信號。FIG. 2 illustrates a bottom perspective view of the front of the RJ45 socket 110 of FIG. 1, where it can be seen that there is a plug opening 230 for inserting a plug (not shown in the figure). The plug opening 230 can be configured to receive a plug to couple the contacts on the plug to the set 212 of plug contacts in the RJ45 socket 110. The plug can be a RJ45 8-position 8-contact (8P8C) modular plug. The set 212 of plug contacts is formed as a set 210 of pins assembled to attach to the communication circuit on the circuit board. For example, the RJ45 socket 110 can be mounted to the circuit board of the network switching device through the use of a pair of posts 220, and then the pin assembly 210 can be soldered to individual contact pads on the circuit board of the device. By itself, a socket similar to the RJ45 socket 110 illustrated in FIG. 2 provides basic connectivity between the plug of the RJ45 cable and the circuit board of the device into which the socket is integrated. However, the socket is not designed to handle the communication frequency required for high-speed communication. For example, the RJ45 socket 110 for assembly according to the disclosed method as described herein can integrate other components such as the socket cover 130 and the flexible PCB 120, so that it can be used to communicate at a higher speed without interfering with transient signals. .

圖3例示用來給RJ45插座110及可撓性PCB 120提供屏蔽的插座罩之底視及右側視圖。插座罩130包括頂部302、底部304、後部306、前部308、左側部(未顯示於圖中但實質上與右側部相同)及右側部310。為了提供期望的屏蔽性質,於本揭示之一個實施例中,插座罩130可包括導電材料,諸如,但非限制性,鋼、銅、或任何其它導電材料。在插座罩130的右側310及左側(未顯示於圖中)上接近底部304的一對凸耳320可使用來接地及固定插座罩130至裝置(未顯示於圖中)內部的電路板。舉例言之,於插座罩130上的該對凸耳320可插入電路板上一對匹配安裝孔徑內,及焊接其上。FIG. 3 illustrates the bottom and right side views of the socket cover used to provide shielding for the RJ45 socket 110 and the flexible PCB 120. The socket cover 130 includes a top 302, a bottom 304, a rear 306, a front 308, a left side (not shown in the figure but substantially the same as the right side), and a right side 310. In order to provide the desired shielding properties, in one embodiment of the present disclosure, the socket cover 130 may include a conductive material, such as, but not limited to, steel, copper, or any other conductive material. A pair of lugs 320 near the bottom 304 on the right side 310 and the left side (not shown in the figure) of the socket cover 130 can be used to ground and fix the socket cover 130 to the circuit board inside the device (not shown in the figure). For example, the pair of lugs 320 on the socket cover 130 can be inserted into a pair of matching mounting holes on the circuit board and soldered to it.

圖4A例示RJ45插座之PCB 120的前表面之頂視示意代表圖。PCB 120包括由結合帶-線彎曲或相當技術的介電材料製成的多層基體402。基體402邊緣環繞有保護層404。保護層404係由非導電材料製成,諸如,但非限制性,塑膠或可撓性焊罩。基體402的前表面包括製作成貫穿基體402的多數通孔406、408、410、412、414、416、418及420。各個通孔406、408、410、412、414、416、418及420貫穿通過基體402及其尺寸可容納針腳210。環繞各個通孔406、408、410、412、414、416、418及420區域係以導電材料被覆,諸如金。環繞各個通孔406、408、410、412、414、416、418及420的被覆可以是實質上方形或實質上矩形。於另一實施例中,於圖4B中描繪,環繞各個通孔406、408、410、412、414、416、418及420的被覆可以是實質上圓形。藉將被覆層製作成圓形,可減少相鄰通孔406、408、410、412、414、416、418及420間之干擾。FIG. 4A illustrates a schematic top view of the front surface of the PCB 120 of the RJ45 socket. The PCB 120 includes a multilayer substrate 402 made of a dielectric material combining strip-line bending or equivalent technology. A protective layer 404 surrounds the edge of the base 402. The protective layer 404 is made of a non-conductive material, such as, but not limited to, plastic or a flexible welding mask. The front surface of the base 402 includes a plurality of through holes 406, 408, 410, 412, 414, 416, 418 and 420 made through the base 402. Each through hole 406, 408, 410, 412, 414, 416, 418, and 420 penetrates through the base 402 and its size can accommodate the stitch 210. The area surrounding each through hole 406, 408, 410, 412, 414, 416, 418, and 420 is coated with a conductive material, such as gold. The coating surrounding each of the through holes 406, 408, 410, 412, 414, 416, 418, and 420 may be substantially square or substantially rectangular. In another embodiment, depicted in FIG. 4B, the coating surrounding each of the through holes 406, 408, 410, 412, 414, 416, 418, and 420 may be substantially circular. By making the covering layer into a circular shape, interference between adjacent through holes 406, 408, 410, 412, 414, 416, 418, and 420 can be reduced.

多個線跡422、424、426、428、430、432、434及436自各個通孔406、408、410、412、414、416、418及420朝向PCB 120一端延伸。各個線跡422、424、426、428、430、432、434及436係從包括銅或金的導電材料製成。於一個實施例中,鎳層係形成於基體402上,及金層係形成於鎳層上以形成各個線跡422、424、426、428、430、432、434及436。各個線跡422、424、426、428、430、432、434及436朝向PCB 120的一後端延伸直到該線跡422、424、426、428、430、432、434或436到達接近該PCB 120相對於通孔406、408、410、412、414、416、418及420的一緣之一屏蔽線跡層490為止。各個線跡422、424、426、428、430、432、434及436包括相鄰第二部分470、472、474、476、478、480、482及484的第一部分454、456、458、460、462、464、466及468,而各個第二部分470、472、474、476、478、480、482及484延伸至屏蔽線跡層490而不接觸屏蔽線跡層490。各個第一部分454、456、458、460、462、464、466及468從個別第二部分470、472、474、476、478、480、482及484朝向一個別通孔406、408、410、412、414、416、418或420呈錐形。各個第二部分470、472、474、476、478、480、482及484具有隨線跡422、424、426、428、430、432、434或436而改變的長度。A plurality of stitches 422, 424, 426, 428, 430, 432, 434, and 436 extend from the respective through holes 406, 408, 410, 412, 414, 416, 418, and 420 toward one end of the PCB 120. The individual traces 422, 424, 426, 428, 430, 432, 434, and 436 are made from conductive materials including copper or gold. In one embodiment, the nickel layer is formed on the substrate 402, and the gold layer is formed on the nickel layer to form the respective traces 422, 424, 426, 428, 430, 432, 434, and 436. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 extends toward a rear end of the PCB 120 until the trace 422, 424, 426, 428, 430, 432, 434, or 436 reaches close to the PCB 120 One edge of the through holes 406, 408, 410, 412, 414, 416, 418, and 420 is shielded to the trace layer 490. Each of the stitches 422, 424, 426, 428, 430, 432, 434, and 436 includes the first portions 454, 456, 458, 460, and 460 of the adjacent second portions 470, 472, 474, 476, 478, 480, 482, and 462, 464, 466, and 468, and the respective second portions 470, 472, 474, 476, 478, 480, 482, and 484 extend to the shielding trace layer 490 without contacting the shielding trace layer 490. The respective first portions 454, 456, 458, 460, 462, 464, 466, and 468 are directed from the respective second portions 470, 472, 474, 476, 478, 480, 482, and 484 to a separate through hole 406, 408, 410, 412 , 414, 416, 418 or 420 are tapered. Each of the second portions 470, 472, 474, 476, 478, 480, 482, and 484 has a length that changes with the stitches 422, 424, 426, 428, 430, 432, 434, or 436.

兩個屏蔽凸耳486及488係位在PCB 120的相對緣上。各個屏蔽凸耳486及488係由覆蓋於導電材料例如,金或銅中的基體製成。屏蔽凸耳486及488係在基體402上藉屏蔽線跡層490電氣連結,該屏蔽線跡層490係延伸於屏蔽凸耳486及488間且係位在各個線跡422、424、426、428、430、432、434及436之第二部分470、472、474、476、478、480、482及484與該PCB 120相對通孔406、408、410、412、414、416、418及420的該緣間。The two shielding lugs 486 and 488 are located on the opposite edges of the PCB 120. Each of the shielding lugs 486 and 488 is made of a substrate covered in a conductive material such as gold or copper. The shielding lugs 486 and 488 are electrically connected on the base 402 by a shielding trace layer 490, which extends between the shielding lugs 486 and 488 and is located on the respective traces 422, 424, 426, 428 The second parts 470, 472, 474, 476, 478, 480, 482, and 484 of 430, 432, 434, and 436 are opposite to the through holes 406, 408, 410, 412, 414, 416, 418, and 420 of the PCB 120 The margin.

圖5A例示圖4A之印刷電路板之後表面的頂視示意代表圖。後表面包括通孔406、408、410、412、414、416、418及420、屏蔽凸耳486及488、及延伸於各個屏蔽凸耳486及488的後表面間之屏蔽線跡層502。屏蔽線跡層502覆蓋PCB 120之後表面介於屏蔽凸耳486及488間之該部分。屏蔽凸耳486及488包括返回通孔504、506、508、510、512、514、516及518,其貫穿基體402通過連結屏蔽線跡層490與屏蔽線跡層502。圖5B描繪圖4B之印刷電路板之後表面的頂視圖之另一實施例。FIG. 5A illustrates a schematic top view representative view of the back surface of the printed circuit board of FIG. 4A. The back surface includes through holes 406, 408, 410, 412, 414, 416, 418, and 420, shielding lugs 486 and 488, and a shielding trace layer 502 extending between the back surfaces of the respective shielding lugs 486 and 488. The shielding trace layer 502 covers the part of the rear surface of the PCB 120 between the shielding lugs 486 and 488. The shielding lugs 486 and 488 include return through holes 504, 506, 508, 510, 512, 514, 516 and 518, which penetrate the substrate 402 by connecting the shielding trace layer 490 and the shielding trace layer 502. FIG. 5B depicts another embodiment of a top view of the back surface of the printed circuit board of FIG. 4B.

圖6A例示於PCB 120中之多層基體402沿圖4之線BB的剖面圖。多層基體402之第一層602包括由諸如PSR9000FST可撓性焊罩材料製成的焊罩部分。第二層604係形成於頂層下方及包括線跡422、424、426、428、430、432、434及436中之各者。各個線跡422、424、426、428、430、432、434及436具有長度(L)、高度(H)及寬度(W),且與相鄰線跡分開達距離(S)。各線跡之長度(L)為沿可撓性電路板120之表面自其個別通孔406、408、410、412、414、416、418及420邊緣至屏蔽線跡層490延伸的線跡之長度。FIG. 6A illustrates a cross-sectional view of the multilayer substrate 402 in the PCB 120 along the line BB of FIG. 4. The first layer 602 of the multilayer substrate 402 includes a welding shield portion made of a flexible welding shield material such as PSR9000FST. The second layer 604 is formed under the top layer and includes each of the stitches 422, 424, 426, 428, 430, 432, 434, and 436. Each of the stitches 422, 424, 426, 428, 430, 432, 434, and 436 has a length (L), a height (H), and a width (W), and is separated from an adjacent stitch by a distance (S). The length (L) of each trace is the length of the trace extending from the edge of the individual through holes 406, 408, 410, 412, 414, 416, 418, and 420 along the surface of the flexible circuit board 120 to the shielding trace layer 490 .

各個線跡422、424、426、428、430、432、434及436延伸貫穿第一層602使得各個線跡422、424、426、428、430、432、434及436不被可撓性焊罩遮蓋。屏蔽線跡層490也形成於第二層604之部分上方而屏蔽線跡層490延伸貫穿第一層602。第三介電層606形成於第二層604下方。第三層606具有約0.002密耳至約0.005密耳之深度(D),且係由具有介電常數大於3.0之材料製成,諸如,但非僅限於RO XT8100,羅傑森材料(Rogerson Material)或能隔離高頻電氣信號的任何其它材料。The stitches 422, 424, 426, 428, 430, 432, 434, and 436 extend through the first layer 602 so that the stitches 422, 424, 426, 428, 430, 432, 434, and 436 are not covered by flexible welding Cover up. The shielding trace layer 490 is also formed over a portion of the second layer 604 and the shielding trace layer 490 extends through the first layer 602. The third dielectric layer 606 is formed under the second layer 604. The third layer 606 has a depth (D) of about 0.002 mils to about 0.005 mils, and is made of materials with a dielectric constant greater than 3.0, such as, but not limited to, RO XT8100, Rogerson Material ) Or any other material that can isolate high-frequency electrical signals.

第四層608係形成於第三層606下方,而第四層608包括信號返回部及屏蔽線跡部502。信號返回部及屏蔽線跡部502兩者係由導電材料,較佳地為金或銅製成。第五層610係形成於第四層608上而第五層610具有可撓性焊罩部及屏蔽線跡層502部。可撓性焊罩部係由第一層602的可撓性焊罩部之相同材料製成。於替代釋例中,可撓性焊罩部係從與第一層602的可撓性焊罩部之不同材料製成。於替代釋例中,第二信號返回層(未顯示於圖中)可位在介電材料內。The fourth layer 608 is formed under the third layer 606, and the fourth layer 608 includes a signal return portion and a shielding trace portion 502. Both the signal return portion and the shielding trace portion 502 are made of conductive materials, preferably gold or copper. The fifth layer 610 is formed on the fourth layer 608 and the fifth layer 610 has a flexible solder mask portion and a shielding trace layer 502 portion. The flexible welding shield is made of the same material as the flexible welding shield of the first layer 602. In an alternative example, the flexible welding mask part is made of a different material from the flexible welding mask part of the first layer 602. In an alternative example, the second signal return layer (not shown in the figure) may be located in the dielectric material.

為了消除由相鄰線跡造成的串擾,各個線跡422、424、426、428、430、432、434及436係電氣耦合至相鄰線跡422、424、426、428、430、432、434及436。舉個例示釋例,線跡422可耦合至線跡424。於操作期間,第一信號發射傳過第一線跡,及具有相反極性的相同信號發射傳過匹配線跡,藉此將線跡差異地耦合在一起。因線跡被差異地耦合在一起,各線跡的阻抗決定了線跡被如何驅動。如此各集合之匹配線跡的阻抗須實質上相等。In order to eliminate the crosstalk caused by adjacent traces, each trace 422, 424, 426, 428, 430, 432, 434, and 436 are electrically coupled to adjacent traces 422, 424, 426, 428, 430, 432, 434 And 436. As an illustrative example, the trace 422 may be coupled to the trace 424. During operation, the first signal is transmitted through the first trace, and the same signal with the opposite polarity is transmitted through the matching trace, thereby differentially coupling the traces together. Because the traces are differentially coupled together, the impedance of each trace determines how the trace is driven. In this way, the impedances of the matching traces of each set must be substantially equal.

在一匹配集合之線跡中各個線跡422、424、426、428、430、432、434及436的物理特性係經調整以平衡用於發射的匹配線跡與透過各線跡發射的返回信號間之阻抗。各個線跡422、424、426、428、430、432、434及436之阻抗係藉由調整各個線跡之長度(L)、寬度(W)、高度(H)及針對透過各線跡422、424、426、428、430、432、434及436發射的各個信號的匹配線跡間之間隔(S)中之任一者或其組合而予調整。各個線跡422、424、426、428、430、432、434及436之高度(H)可以是約2密耳至約6密耳,及相鄰線跡422、424、426、428、430、432、434及436間之間隔(S)可以是約3密耳至約10密耳。The physical characteristics of each trace 422, 424, 426, 428, 430, 432, 434, and 436 in a matching set of traces are adjusted to balance the matching trace for transmission and the return signal transmitted through each trace的impedance. The impedance of each stitch 422, 424, 426, 428, 430, 432, 434, and 436 is adjusted by adjusting the length (L), width (W), height (H) of each stitch , 426, 428, 430, 432, 434, and 436 transmit each signal's matching line spacing (S) any one or a combination of them. The height (H) of each stitch 422, 424, 426, 428, 430, 432, 434, and 436 can be about 2 mils to about 6 mils, and adjacent stitches 422, 424, 426, 428, 430, The interval (S) between 432, 434, and 436 may be about 3 mils to about 10 mils.

回頭參考圖4,各個線跡具有於第一部分454、456、458、460、462、464、466及468中之可變寬度及於第二部分470、472、474、476、478、480、482及484中之實質恆定寬度。據此,各個線跡422、424、426、428、430、432、434及436之寬度係沿線跡422、424、426、428、430、432、434及436之高度H於第一部分454、456、458、460、462、464、466及468或第二部分470、472、474、476、478、480、482及484中經調整,或於第一部分454、456、458、460、462、464、466及468及第二部分470、472、474、476、478、480、482及484兩者中經調整,使得當匹配線跡分開距離S時於一匹配集合中之各個線跡具有實質上相同阻抗。Referring back to FIG. 4, each stitch has a variable width in the first part 454, 456, 458, 460, 462, 464, 466, and 468 and in the second part 470, 472, 474, 476, 478, 480, 482 And 484 have a substantially constant width. Accordingly, the width of each stitch 422, 424, 426, 428, 430, 432, 434, and 436 is along the height H of the stitch 422, 424, 426, 428, 430, 432, 434, and 436 in the first part 454, 456 , 458, 460, 462, 464, 466 and 468 or the second part 470, 472, 474, 476, 478, 480, 482 and 484 adjusted in the first part 454, 456, 458, 460, 462, 464 , 466 and 468 and the second parts 470, 472, 474, 476, 478, 480, 482, and 484 are adjusted so that when the matching traces are separated by a distance S, each trace in a matching set has substantially The same impedance.

因製造及材料上的不一致故,驅動通過各集合之差異匹配線跡422、424、426、428、430、432、434及436的信號可不相同,其造成一部分信號被反射回而引發共模干擾。為了消除共模干擾,於一匹配線跡集合中之各個線跡422、424、426、428、430、432、434或436包括共模濾波器,其係經調諧以消除於匹配集合中之任何共模干擾。各個濾波器包含由各個線跡422、424、426、428、430、432、434或436之通孔406、408、410、412、414、416、418或420及多層基體402之第四層608所形成的電容器。各個通孔406、408、410、412、414、416、418及420包括環繞基體402的第二層604及第四層608上的通孔406、408、410、412、414、416、418及420周邊形成的一層導電材料,諸如金或銅。第一層602上的導電材料係連結至與通孔406、408、410、412、414、416、418及420相關聯的線跡422、424、426、428、430、432、434及436,及第四層608上的導電材料係連結至第四層608的信號返回部。各個電容器之大小係由第二層604及第四層608上的導電材料間距決定。據此,調整相關於通孔406、408、410、412、414、416、418及420上的導電材料的第三層606之深度允許調整各個通孔406、408、410、412、414、416、418及420之電容效應。由通孔406、408、410、412、414、416、418及420及第四層608之返回部產生的電容器之大小為約0.1皮法拉第(pf)至約0.5 pf。基體402的頂面及底面可覆蓋於塑膠絕緣層中以進一步加強電路操作。Due to inconsistencies in manufacturing and materials, the signals driving through the different sets of matching traces 422, 424, 426, 428, 430, 432, 434, and 436 may be different, which causes part of the signal to be reflected back and cause common mode interference . In order to eliminate common mode interference, each trace 422, 424, 426, 428, 430, 432, 434, or 436 in a matching trace set includes a common mode filter, which is tuned to eliminate any in the matching set Common mode interference. Each filter includes a through hole 406, 408, 410, 412, 414, 416, 418, or 420 of each trace 422, 424, 426, 428, 430, 432, 434, or 436, and a fourth layer 608 of a multilayer substrate 402. The formed capacitor. Each of the through holes 406, 408, 410, 412, 414, 416, 418, and 420 includes through holes 406, 408, 410, 412, 414, 416, 418 and the through holes 406, 408, 410, 412, 414, 416, 418 surrounding the second layer 604 and the fourth layer 608 of the substrate 402. A layer of conductive material formed around the 420, such as gold or copper. The conductive material on the first layer 602 is connected to the traces 422, 424, 426, 428, 430, 432, 434, and 436 associated with the vias 406, 408, 410, 412, 414, 416, 418, and 420, And the conductive material on the fourth layer 608 is connected to the signal return part of the fourth layer 608. The size of each capacitor is determined by the distance between the conductive materials on the second layer 604 and the fourth layer 608. Accordingly, adjusting the depth of the third layer 606 of the conductive material on the vias 406, 408, 410, 412, 414, 416, 418, and 420 allows adjustment of the respective vias 406, 408, 410, 412, 414, 416 , 418 and 420 capacitance effect. The size of the capacitor generated by the through holes 406, 408, 410, 412, 414, 416, 418, and 420 and the return portion of the fourth layer 608 is about 0.1 picofarad (pf) to about 0.5 pf. The top and bottom surfaces of the base 402 can be covered in a plastic insulating layer to further enhance circuit operation.

於各個通孔406、408、410、412、414、416、418及420中產生的電容器與信號返回層之特性電感之組合對各個線跡422、424、426、428、430、432、434或436產生共模濾波器。藉由基於線跡422、424、426、428、430、432、434及436之阻抗調整各個電容器的電容值,共模雜訊大減,藉以改進於各線跡422、424、426、428、430、432、434及436上的信號通量。The combination of the characteristic inductance of the capacitor and the signal return layer generated in each of the through holes 406, 408, 410, 412, 414, 416, 418, and 420 affects each trace 422, 424, 426, 428, 430, 432, 434 or 436 generates a common mode filter. By adjusting the capacitance value of each capacitor based on the impedance of traces 422, 424, 426, 428, 430, 432, 434, and 436, the common mode noise is greatly reduced, thereby improving on the traces 422, 424, 426, 428, 430 , 432, 434, and 436.

圖6B例示通孔406、408、410、412、414、416、418或420之剖面圖的示意代表。各個通孔406、408、410、412、414、416、418及420形成貫穿第一層602、第二層604、第三層606、第四層608及第五層610。第二層604係由導電材料諸如金或銅製成及環繞各個通孔406、408、410、412、414、416、418及420周邊。第二層604也連結各個通孔406、408、410、412、414、416、418及420到其個別線跡422、424、426、428、430、432、434或436。第三層606作為如圖6A中描述的介電層。第四層608形成於第三層606中及作為信號返回層。第五層610也係由導電材料諸如金或銅製成,及也以第一層602之相同方式環繞通孔周邊。密封層(未顯示於圖中)也可形成於第五層610上方。FIG. 6B illustrates a schematic representation of a cross-sectional view of through holes 406, 408, 410, 412, 414, 416, 418, or 420. Each through hole 406, 408, 410, 412, 414, 416, 418 and 420 is formed to penetrate through the first layer 602, the second layer 604, the third layer 606, the fourth layer 608 and the fifth layer 610. The second layer 604 is made of a conductive material such as gold or copper and surrounds the periphery of each through hole 406, 408, 410, 412, 414, 416, 418, and 420. The second layer 604 also connects each via 406, 408, 410, 412, 414, 416, 418, and 420 to its individual traces 422, 424, 426, 428, 430, 432, 434, or 436. The third layer 606 serves as a dielectric layer as described in FIG. 6A. The fourth layer 608 is formed in the third layer 606 and serves as a signal return layer. The fifth layer 610 is also made of conductive material such as gold or copper, and also surrounds the periphery of the via in the same manner as the first layer 602. A sealing layer (not shown in the figure) can also be formed on the fifth layer 610.

第四層608與第二層604分開達距離D1及與610分開達距離D2。第二層604、第三介電層606、及第四返回信號層608的組合產生具有約0.1 pf至0.5 pf之電容值的電容器。藉由調整第四層608與第二層604的距離D1,通孔電容器之電容值係經調整。因通孔連結其相關聯的線跡與第四返回信號層608,故第二層604、第三介電層606、及第四返回信號層608的組合形成共模濾波器,其去除由因製程缺陷所導致的信號反射造成的任何干擾。藉著調整通孔電容器之電容值,共模濾波器可經調諧以消除發射信號或返回信號的反射所引發的實質上全部信號雜訊。The fourth layer 608 is separated from the second layer 604 by a distance D1 and from 610 by a distance D2. The combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 produces a capacitor having a capacitance value of about 0.1 pf to 0.5 pf. By adjusting the distance D1 between the fourth layer 608 and the second layer 604, the capacitance value of the through-hole capacitor is adjusted. Since the through hole connects its associated trace and the fourth return signal layer 608, the combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 forms a common mode filter, and its removal is caused by Any interference caused by signal reflection caused by process defects. By adjusting the capacitance value of the through-hole capacitor, the common mode filter can be tuned to eliminate substantially all signal noise caused by the reflection of the transmitted signal or the return signal.

圖6C例示通孔406、408、410、412、414、416、418及420之剖面圖的另一釋例。第二返回信號層612係加至第一返回信號層608與第五層610間之第三層606。第二返回信號層612平行於第一返回信號層608及提供共模濾波器的過濾效果。藉由調整第一返回信號層608與第二返回信號層612間之距離D3,於該通孔中產生了由第一返回信號層608、第三層606及第二返回信號層612所形成的第二電容器。藉由調整距離D3,第二通孔電容器之值可經調整以加強共模濾波器之操作。又復,如發明人已知,於通孔中形成第二電容器允許在PCB 102之分開端上的線跡匹配。至於替代釋例,線跡422可與線跡436匹配。據此,藉由形成第二電容器,可調整根據RJ45標準定位的成對信號線。FIG. 6C illustrates another example of the cross-sectional view of the through holes 406, 408, 410, 412, 414, 416, 418, and 420. The second return signal layer 612 is added to the third layer 606 between the first return signal layer 608 and the fifth layer 610. The second return signal layer 612 is parallel to the first return signal layer 608 and provides the filtering effect of a common mode filter. By adjusting the distance D3 between the first return signal layer 608 and the second return signal layer 612, the first return signal layer 608, the third layer 606, and the second return signal layer 612 are formed in the through hole. The second capacitor. By adjusting the distance D3, the value of the second via capacitor can be adjusted to enhance the operation of the common mode filter. Furthermore, as known by the inventor, forming a second capacitor in the through hole allows the traces on the divided ends of the PCB 102 to be matched. As for an alternative example, the stitch 422 may be matched with the stitch 436. Accordingly, by forming the second capacitor, the pair of signal lines positioned according to the RJ45 standard can be adjusted.

圖7例示具有匹配的發射線跡及接收線跡的RJ45插座之示意代表圖。藉由調整各個線跡422、424、426、428、430、432、434或436之高度H、寬度W、及長度L,發射線路與接收線路可以是阻抗匹配。為了加強插座的操作,具有相反極性的相同高頻信號沿各對發射。因匹配線跡透過護罩而耦合故,成對信號線作為彼此的共模濾波器。又,若一個信號無法被遞送,則對應的相反信號線將遞送相同信號。因匹配線跡作為耦合至護罩的濾波器故,由高頻寬傳輸造成的雜訊係從信號中被過濾出。又復,因發射線路匹配接收線路故,信號的過濾係以較高準確度進行,原因在於與接地連結相反地,濾波器的參考點為信號本身。Figure 7 illustrates a schematic representation of an RJ45 socket with matching transmit and receive traces. By adjusting the height H, width W, and length L of each trace 422, 424, 426, 428, 430, 432, 434, or 436, the transmitting line and the receiving line can be impedance matched. In order to enhance the operation of the socket, the same high frequency signal with opposite polarity is emitted along each pair. Because the matching traces are coupled through the shield, the paired signal lines act as common mode filters for each other. Also, if a signal cannot be delivered, the corresponding opposite signal line will deliver the same signal. Because the matching trace acts as a filter coupled to the shield, the noise caused by high-bandwidth transmission is filtered out of the signal. Furthermore, because the transmitting line matches the receiving line, the filtering of the signal is performed with higher accuracy. The reason is that, contrary to the ground connection, the reference point of the filter is the signal itself.

圖8例示差分平衡成對信號線之示意代表圖。如圖描繪,各線跡之特性係經調整使得第一線跡之阻抗使用先前討論方法匹配第二線跡之阻抗。又,形成於各個通孔中的電容器與嵌置於PCB 120中之返回信號線形成一共模濾波器。藉由於發射信號及回應信號兩者的發射期間差分平衡二線跡,達成全然平衡的雙向通訊電路。Fig. 8 illustrates a schematic representation diagram of differentially balanced paired signal lines. As depicted in the figure, the characteristics of each trace are adjusted so that the impedance of the first trace matches the impedance of the second trace using the method previously discussed. In addition, the capacitor formed in each through hole and the return signal line embedded in the PCB 120 form a common mode filter. By differentially balancing the two traces during the transmission period of both the transmission signal and the response signal, a fully balanced two-way communication circuit is achieved.

圖9例示針對發射信號及返回信號平衡匹配線跡之一方法的示意代表圖。於步驟902中,於匹配的一對線跡中各個線跡的物理特性係經調整使得線跡之阻抗為實質上相等。物理特性可包括於匹配線跡集合中各線跡的高度、長度及寬度及分開各線跡的距離。於步驟904中,具有第一極性的第一信號係沿匹配線跡集合中之第一線跡傳輸。第一信號可以是於大於10十億赫茲(GHz)之頻率操作的高頻通訊信號。於步驟906中,與第一信號實質上相同但具有第一信號的極性之相反極性的第二信號係與第一信號同時在該匹配線跡集合中之第二線跡上傳輸。於步驟908中,第一信號係於線跡的產生端及結束端量測,及二度量值經比較以決定沿線跡之長度的資料損耗量。於步驟910中,第一線跡或第二線跡的至少一個物理特性係基於量測得的信號損耗量加以調整。處理程序可返回步驟904直到信號損耗量小於約10分貝(db)為止。FIG. 9 illustrates a schematic representative diagram of a method of balancing and matching traces for the transmission signal and the return signal. In step 902, the physical characteristics of each trace in the matched pair of traces are adjusted so that the impedance of the traces is substantially equal. The physical characteristics may include the height, length, and width of each stitch in the matching stitch set and the distance separating each stitch. In step 904, the first signal with the first polarity is transmitted along the first trace in the set of matched traces. The first signal may be a high-frequency communication signal operating at a frequency greater than 10 gigahertz (GHz). In step 906, a second signal that is substantially the same as the first signal but has a polarity opposite to the polarity of the first signal is simultaneously transmitted on the second trace in the set of matched traces along with the first signal. In step 908, the first signal is measured at the origin and end of the trace, and the two metric values are compared to determine the amount of data loss along the length of the trace. In step 910, at least one physical characteristic of the first stitch or the second stitch is adjusted based on the measured signal loss. The processing procedure may return to step 904 until the signal loss is less than about 10 decibels (db).

於步驟912中,第三信號係在匹配線跡集合的第二線跡上傳輸。於步驟914中,實質上與第三信號相同但具有第三信號之相反極性的第四信號係在第一線跡上傳輸。於步驟916中,第三信號係在線跡的生成端及結束端上量測,及兩個度量經比較以決定沿線跡之長度的資料損耗量。於步驟918中,第一線跡或第二線跡的至少一個物理特性係基於量測得的信號損耗量加以調整。處理程序可返回步驟912直到信號損耗量小於約10分貝(db)為止。於另一釋例中,處理程序可返回步驟904以確定第三信號之損耗不受回應於第三信號之損耗所做調整的影響。In step 912, the third signal is transmitted on the second trace of the set of matched traces. In step 914, a fourth signal that is substantially the same as the third signal but has the opposite polarity of the third signal is transmitted on the first trace. In step 916, the third signal is measured at the generating and ending ends of the trace, and the two metrics are compared to determine the amount of data loss along the length of the trace. In step 918, at least one physical characteristic of the first stitch or the second stitch is adjusted based on the measured signal loss. The processing procedure may return to step 912 until the signal loss is less than about 10 decibels (db). In another example, the processing procedure may return to step 904 to determine that the loss of the third signal is not affected by adjustments made in response to the loss of the third signal.

圖10例示位在插座110中的PCB 120。PCB 120之基體402係自可撓性材料製成,其允許PCB 120之第一部分相對於PCB 120之第二部分定向達約90度角。據此,PCB 120彎曲使得通孔406、408、410、412、414、416、418及420位在插座中的針腳210上方,及線跡422、424、426、428、430、432、434及436自通孔406、408、410、412、414、416、418及420延伸至用於插座的接點襯墊。屏蔽凸耳486及488經彎曲使得其與PCB 120呈約90度角。屏蔽凸耳486及488沿插座側邊置放使得插座之插座罩130接合屏蔽凸耳486及488。FIG. 10 illustrates the PCB 120 located in the socket 110. The base 402 of the PCB 120 is made from a flexible material, which allows the first part of the PCB 120 to be oriented at an angle of about 90 degrees with respect to the second part of the PCB 120. Accordingly, the PCB 120 is bent so that the through holes 406, 408, 410, 412, 414, 416, 418, and 420 are located above the pins 210 in the socket, and the traces 422, 424, 426, 428, 430, 432, 434 and 436 extends from the through holes 406, 408, 410, 412, 414, 416, 418, and 420 to the contact pads for the socket. The shielding lugs 486 and 488 are bent so that they form an angle of about 90 degrees with the PCB 120. The shielding lugs 486 and 488 are placed along the sides of the socket so that the socket cover 130 of the socket engages the shielding lugs 486 and 488.

可撓性PCB 120可使用允許可撓性PCB 120彎曲的任何可撓性塑膠基體具體實施。如於本文中描述,可撓性PCB 120可以彎折或彎曲以隨形於RJ45插座110的現有形狀因數且由插座罩130屏蔽。舉例言之,可撓性PCB 120可附接至RJ45插座110,位在RJ45插座110與插座罩130間。可撓性PCB 120之屏蔽凸耳486及488可附接至插座罩130以提供共通連結至可撓性PCB 120上的可撓性電路。然後RJ45插座110之針腳之集合210可電氣耦合至於其中使用RJ45插座110的一裝置的電路板。The flexible PCB 120 can be implemented using any flexible plastic substrate that allows the flexible PCB 120 to be bent. As described herein, the flexible PCB 120 can be bent or bent to conform to the existing form factor of the RJ45 socket 110 and be shielded by the socket cover 130. For example, the flexible PCB 120 can be attached to the RJ45 socket 110 between the RJ45 socket 110 and the socket cover 130. The shielding lugs 486 and 488 of the flexible PCB 120 can be attached to the socket cover 130 to provide a flexible circuit commonly connected to the flexible PCB 120. The set 210 of pins of the RJ45 socket 110 can then be electrically coupled to a circuit board of a device in which the RJ45 socket 110 is used.

可撓性PCB 120可經組配以摺疊及隨形於RJ45插座110之形狀以便更佳地匹配現有殼體,諸如插座罩130。舉例言之,於揭示辦法之一個面向中,可撓性PCB 120以約90度角朝向可撓性PCB 120的中段彎曲,以摺疊成插座罩130。可撓性PCB 120之屏蔽凸耳486及488摺疊至插座罩130上且接觸插座罩130,及可經焊接以將可撓性PCB 120固定至插座罩130。熟諳技藝人士將瞭解插座罩130內部可撓性PCB 120相對於RJ45插座110的方向性可依據本揭示之各個面向改變。舉例言之,可撓性PCB 120可夠薄以彎折且摺疊至插座罩130的其它側邊。可撓性PCB 120可經成形而完全沿插座罩130的底部區段304平舖而無需彎折或彎曲入插座罩130內。The flexible PCB 120 can be assembled to fold and conform to the shape of the RJ45 socket 110 to better match the existing housing, such as the socket cover 130. For example, in one aspect of the disclosed method, the flexible PCB 120 is bent toward the middle section of the flexible PCB 120 at an angle of about 90 degrees to be folded into the socket cover 130. The shielding lugs 486 and 488 of the flexible PCB 120 are folded onto the socket cover 130 and contact the socket cover 130, and can be welded to fix the flexible PCB 120 to the socket cover 130. Those skilled in the art will understand that the directionality of the flexible PCB 120 inside the socket cover 130 relative to the RJ45 socket 110 can be changed according to various aspects of the present disclosure. For example, the flexible PCB 120 can be thin enough to be bent and folded to the other sides of the socket cover 130. The flexible PCB 120 can be formed to be completely flat along the bottom section 304 of the socket cover 130 without bending or bending into the socket cover 130.

前文詳細說明部分只是本揭示之若干釋例及實施例,及不背離其精義或範圍可根據本文揭示對揭示實施例做出眾多變化。因此,前文描述並不表示限制揭示範圍,反而給使用不當負擔來實施本發明的熟諳技藝人士提供充分揭示。The foregoing detailed description is only a few explanations and embodiments of the present disclosure, and many changes can be made to the disclosed embodiments based on the disclosure herein without departing from the spirit or scope thereof. Therefore, the foregoing description does not mean to limit the scope of disclosure, but to provide sufficient disclosure to those skilled in the invention who use undue burdens to implement the present invention.

圖11描繪含一剛性基體的高速通訊插座之一個實施例。高速通訊插座1100包括插座殼體1102,其係經組配以接納通訊插頭(未顯示於圖中)。基體1300置放於殼體之下表面上使得針腳1306從基體1300延伸用來與在設置時插座安裝其上的電路板接合。Figure 11 depicts an embodiment of a high-speed communication socket with a rigid base. The high-speed communication socket 1100 includes a socket housing 1102, which is assembled to receive a communication plug (not shown in the figure). The base 1300 is placed on the lower surface of the housing so that the pins 1306 extend from the base 1300 for engagement with the circuit board on which the socket is mounted during installation.

圖12描繪於剛性高速通訊插座中之各層的示意代表圖。基體1300包括含多數通孔(未顯示於圖中)其各自的尺寸可容納一針腳的一頂層1202,含如前文討論的多數阻抗匹配線跡之一第二層1204,及含通孔其係同心對齊第一層1202中之通孔的一第三層1206及第四層1208。第一層1202係藉非導電材料,諸如,但非限制性,羅傑士(Rogers)材料製成的第一中間層1210而與第二層1204分開。第二層1204係藉第二中間層1212與第三層1206分開,及第三層1206與第四層1208係藉第三中間層1214分開。頂焊罩層1216係形成於與第一中間層1210相對的第一層1202之該側上。於一個實施例中,第一層1202、第二層1204、第三層1206及第四層1208包含1/4盎司銅及1/4盎司精加工銀。於一個實施例中,第一中間層1210、第二中間層1212及第三中間層1214係自羅傑士R04003材料製成。於另一實施例中,第一層1202係藉黏著劑黏合至第一中間層1210,第二及第三層1204及1206係藉黏著劑黏合至第二中間層1212,及第三層1206及第四層1208係藉黏著劑黏合至第三中間層1214。Figure 12 depicts a schematic representation of each layer in a rigid high-speed communication socket. The base 1300 includes a top layer 1202 containing a plurality of through holes (not shown in the figure) each of which size can accommodate a pin, a second layer 1204 containing one of the plurality of impedance matching traces discussed above, and a series of through holes. A third layer 1206 and a fourth layer 1208 of the through holes in the first layer 1202 are concentrically aligned. The first layer 1202 is separated from the second layer 1204 by a non-conductive material, such as, but not limited to, a first intermediate layer 1210 made of Rogers material. The second layer 1204 is separated from the third layer 1206 by the second intermediate layer 1212, and the third layer 1206 and the fourth layer 1208 are separated by the third intermediate layer 1214. The top solder mask layer 1216 is formed on the side of the first layer 1202 opposite to the first intermediate layer 1210. In one embodiment, the first layer 1202, the second layer 1204, the third layer 1206, and the fourth layer 1208 include 1/4 ounce of copper and 1/4 ounce of finished silver. In one embodiment, the first intermediate layer 1210, the second intermediate layer 1212, and the third intermediate layer 1214 are made of Rogers R04003 material. In another embodiment, the first layer 1202 is bonded to the first intermediate layer 1210 by an adhesive, the second and third layers 1204 and 1206 are bonded to the second intermediate layer 1212 by an adhesive, and the third layer 1206 and The fourth layer 1208 is bonded to the third intermediate layer 1214 by an adhesive.

圖13A描繪高速通訊插座之側視圖。插座包括一剛性基體1300,剛性基體1300包括在基體1300底側上的第一集合之針腳1302及在基體1300頂側上的第二集合之針腳1304。圖13B描繪剛性基體1300之頂視圖。剛性基體1300包括延伸貫穿基體1300的多數第一通孔1306、1308、1310、1312、1314、1316、1318及1320,其接合在基體1300對側上的第一集合之針腳1302。第一集合之針腳1302係經組配以接合電路板上的通孔(未顯示於圖中)以提供插座與電路板間之通訊連結。第二集合之針腳1304中之各者接合定位在基體1300的與第一通孔1306、1308、1310、1312、1314、1316、1318及1320相對側上的第二通孔1322、1324、1326、1328、1330、1332、1334及1336。第二集合之針腳1304係經組配以當插頭插入插座內時接合插頭的對應針腳。Figure 13A depicts a side view of a high-speed communication socket. The socket includes a rigid base 1300 including a first set of pins 1302 on the bottom side of the base 1300 and a second set of pins 1304 on the top side of the base 1300. FIG. 13B depicts a top view of the rigid base 1300. As shown in FIG. The rigid base 1300 includes a plurality of first through holes 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 extending through the base 1300, which are joined to the first set of pins 1302 on opposite sides of the base 1300. The pins 1302 of the first set are assembled to engage through holes (not shown in the figure) on the circuit board to provide a communication link between the socket and the circuit board. Each of the stitches 1304 of the second set is engaged with the second through holes 1322, 1324, 1326, and the second through holes 1322, 1324, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326, 1326 of the opposite side of the base 1300. 1328, 1330, 1332, 1334, and 1336. The pins 1304 of the second set are assembled to engage the corresponding pins of the plug when the plug is inserted into the socket.

線跡1338係形成於基體1300之頂表面上及連結第二通孔1326至第一通孔1310,及線跡1340連結第二通孔1328至第一通孔1312。第一隔離區1342係形成於線跡1338與1340間以提供二線跡1338與1340間之隔離。線跡1344連結第二通孔1334至第一通孔1318,及線跡1346連結第二通孔1336至第一通孔1320。第二隔離區1348隔離線跡1340與線跡1344,及第三隔離區1350隔離線跡1344與線跡1346。隔離平面1352環繞第二通孔1322、1324、1326、1328、1330、1332、1334及1336與基體邊緣間,及線跡1338及1346與基體1302邊緣間之基體1302周邊延伸。於一個實施例中,隔離區及平面係由1/4盎司銅及1/4盎司銀之材料製成。藉由提供不同線跡間之隔離,線跡間之電氣干擾效應減低或消除。於一個實施例中,通孔形成於各個隔離區以連結隔離區到下方接地層。The stitch 1338 is formed on the top surface of the base 1300 and connects the second through hole 1326 to the first through hole 1310, and the stitch 1340 connects the second through hole 1328 to the first through hole 1312. The first isolation region 1342 is formed between the stitches 1338 and 1340 to provide isolation between the two stitches 1338 and 1340. The stitch 1344 connects the second through hole 1334 to the first through hole 1318, and the stitch 1346 connects the second through hole 1336 to the first through hole 1320. The second isolation region 1348 isolates the stitch 1340 and the stitch 1344, and the third isolation region 1350 isolates the stitch 1344 and the stitch 1346. The isolation plane 1352 extends around the periphery of the base 1302 between the second through holes 1322, 1324, 1326, 1328, 1330, 1332, 1334, and 1336 and the edge of the base, and between the stitches 1338 and 1346 and the edge of the base 1302. In one embodiment, the isolation region and the plane are made of 1/4 ounce copper and 1/4 ounce silver. By providing isolation between different traces, the effect of electrical interference between traces is reduced or eliminated. In one embodiment, through holes are formed in each isolation region to connect the isolation region to the ground layer below.

圖14A描述基體1300之地面層1400。地面層1400置放相鄰頂層1300。地面層1400包括接地平面1402。接地平面1402覆蓋地面層1400之表面但環繞第一通孔1306、1308、1310、1312、1314、1316、1318及1320及第二通孔1322、1324、1326、1328、1330、1332、1334及1336之周邊的該區域除外。地面層1400之表面被覆於導電材料以形成接地平面1402。於一個實施例中,該材料為1/4盎司銅及1/4盎司銀。Figure 14A depicts the ground layer 1400 of the base 1300. The ground floor 1400 is placed adjacent to the top floor 1300. The ground layer 1400 includes a ground plane 1402. The ground plane 1402 covers the surface of the ground layer 1400 but surrounds the first through holes 1306, 1308, 1310, 1312, 1314, 1316, 1318, and 1320 and the second through holes 1322, 1324, 1326, 1328, 1330, 1332, 1334, and 1336 Except for the area surrounding it. The surface of the ground layer 1400 is covered with a conductive material to form a ground plane 1402. In one embodiment, the material is 1/4 ounce of copper and 1/4 ounce of silver.

圖14B描繪基體1300之第二地面層1404。第二地面層1404係以導電材料覆蓋,其實質上覆蓋第二地面層1404之全體表面,但環繞第一通孔1306、1308、1310、1312、1314、1316、1318及1320及第二通孔1322、1324、1326、1328、1330、1332、1334及1336之周邊的該區域除外。於一個實施例中,覆蓋第二地面層1404的材料為1/4盎司銅及1/4盎司銀。FIG. 14B depicts the second ground layer 1404 of the base 1300. The second ground layer 1404 is covered with a conductive material, which substantially covers the entire surface of the second ground layer 1404, but surrounds the first through holes 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and the second through holes Except this area around 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336. In one embodiment, the material covering the second ground layer 1404 is 1/4 ounce of copper and 1/4 ounce of silver.

圖14C描繪基體1300之底層1406。底層1406包括第一通孔1306、1308、1310、1312、1314、1316、1318及1320及第二通孔1322、1324、1326、1328、1330、1332、1334及1336。線跡1408連結第二通孔1322與第一通孔1306,及線跡1410連結第二通孔1324與第一通孔1308。隔離區1412分開線跡1408與線跡1410。第二隔離區1418分開線跡1410與線跡1414,及第三隔離區1420分開線跡1414與線跡1416。隔離平面1422環繞第二通孔1322、1324、1326、1328、1330、1332、1334及1336與基體1302邊緣間,及線跡1408及1416與基體1302邊緣間之底層1406周邊延伸。FIG. 14C depicts the bottom layer 1406 of the substrate 1300. The bottom layer 1406 includes first through holes 1306, 1308, 1310, 1312, 1314, 1316, 1318, and 1320 and second through holes 1322, 1324, 1326, 1328, 1330, 1332, 1334, and 1336. The stitch 1408 connects the second through hole 1322 and the first through hole 1306, and the stitch 1410 connects the second through hole 1324 and the first through hole 1308. The isolation region 1412 separates the stitch 1408 and the stitch 1410. The second isolation region 1418 separates the stitch 1410 and the stitch 1414, and the third isolation region 1420 separates the stitch 1414 and the stitch 1416. The isolation plane 1422 extends around the periphery of the bottom layer 1406 between the second through holes 1322, 1324, 1326, 1328, 1330, 1332, 1334, and 1336 and the edge of the base 1302, and between the stitches 1408 and 1416 and the edge of the base 1302.

圖15A-15F描繪針對高速通訊插座之測試結果的線圖表示型態。圖15A顯示於正常操作期間插座之差分模式版本的插入損耗。如線圖顯示,於趨近2000 MHz之速度時,插入損耗為約1.8 db。圖15B及15C描繪於正常操作中針對插座之近場串擾的線圖表示型態。圖15D描繪於正常操作期間針對插座的返回損耗。線圖也顯示針對IEEE 40GBase-T標準的效能要求。如線圖指示,於趨近2000 MHz之速度時,插座的效能表現比IEEE 40GBase-T標準的效能要求更佳。圖15E描繪於正常操作期間針對插座之遠端串擾的線圖表示型態。線圖也顯示針對IEEE 40GBase-T標準的效能要求。如線圖指示,於趨近2000 MHz之速度時,插座的效能表現比IEEE 40GBase-T標準的效能要求更佳。圖15F描繪於正常操作期間針對插座之遠端串擾的另一幅線圖表示型態。Figures 15A-15F depict a line graph representation of the test results for high-speed communication sockets. Figure 15A shows the insertion loss of the differential mode version of the socket during normal operation. As the line graph shows, the insertion loss is about 1.8 db when approaching the speed of 2000 MHz. Figures 15B and 15C depict a line graph representation of the near-field crosstalk of the socket during normal operation. Figure 15D depicts the return loss for the socket during normal operation. The line graph also shows the performance requirements for the IEEE 40GBase-T standard. As indicated by the line graph, when approaching the speed of 2000 MHz, the performance of the socket is better than the performance requirements of the IEEE 40GBase-T standard. Figure 15E depicts a line graph representation of the far-end crosstalk of the socket during normal operation. The line graph also shows the performance requirements for the IEEE 40GBase-T standard. As indicated by the line graph, when approaching the speed of 2000 MHz, the performance of the socket is better than the performance requirements of the IEEE 40GBase-T standard. Figure 15F depicts another line graph representation of the far-end crosstalk of the socket during normal operation.

如圖15A-15F驗證,藉將線跡及接地平面連結基體1300上,插座能夠以極高速度發射資料而無干擾。又,藉配置基體之各層以提供多個接地層,基體上的線跡之分隔加大,進一步改良了插座的效能。As verified in Figures 15A-15F, by connecting the trace and the ground plane to the base 1300, the socket can transmit data at a very high speed without interference. In addition, by arranging the layers of the substrate to provide multiple grounding layers, the separation of the traces on the substrate is increased, which further improves the performance of the socket.

於本揭示中,用詞「一(a)」或「一(an)」係取作包括單數及複數兩者。相反地,若屬合宜,任何述及複數項目將包括單數。In this disclosure, the term "一(a)" or "一(an)" is taken to include both the singular and the plural. Conversely, if appropriate, any mention of plural items will include the singular.

須瞭解此處揭示之本較佳實施例之各項變化及修正將為熟諳技藝人士顯然易知。不背離本揭示之精髓及範圍且不減低預期的優點可做出變化及修正。因此預期此等變化及修正係由隨附之申請專利範圍涵蓋。It should be understood that the various changes and modifications of the preferred embodiment disclosed here will be obvious to those skilled in the art. Changes and modifications can be made without departing from the essence and scope of this disclosure and without reducing the expected advantages. Therefore, it is expected that these changes and amendments will be covered by the scope of the attached patent application.

110‧‧‧RJ45插座120‧‧‧可撓性印刷電路板(PCB)130‧‧‧插座罩210、1302、1304‧‧‧針腳之集合212‧‧‧插頭接點之集合220‧‧‧一對柱230‧‧‧插頭開口302‧‧‧頂部304‧‧‧底部306‧‧‧後部308‧‧‧前部310‧‧‧右側部320‧‧‧一對凸耳402、1300‧‧‧基體404‧‧‧保護層406、408、410、412、414、416、418、420‧‧‧通孔422、424、426、428、430、432、434、436、1338、1340、1344、1346、1408、1410、1414、1416‧‧‧線跡454、456、458、460、462、464、466、468‧‧‧第一部分470、472、474、476、478、480、482、484‧‧‧第二部分486、488‧‧‧屏蔽凸耳490、502‧‧‧屏蔽線跡層504、506、508、510、512、514、516、518‧‧‧返回通孔602、1202‧‧‧第一層604、1204‧‧‧第二層606、1206‧‧‧第三層608、1208‧‧‧第四層610‧‧‧第五層612‧‧‧第二返回信號層902-918‧‧‧步驟1100‧‧‧高速通訊插座1102‧‧‧插座殼體1202‧‧‧頂層1210‧‧‧第一中間層1212‧‧‧第二中間層1214‧‧‧第三中間層1216‧‧‧頂焊罩層1306、1308、1310、1312、1314、1316、1318、1320‧‧‧第一通孔1322、1324、1326、1328、1330、1332、1334、1336‧‧‧第二通孔1342、1412‧‧‧第一隔離區1348、1418‧‧‧第二隔離區1350、1420‧‧‧第三隔離區1352、1422‧‧‧隔離平面1400‧‧‧地面層1402‧‧‧接地平面1404‧‧‧第二地面層1406‧‧‧底層110‧‧‧RJ45 socket 120‧‧‧Flexible printed circuit board (PCB) 130‧‧‧Socket cover 210,1302,1304‧‧‧Pin collection 212‧‧‧Plug contact collection 220‧‧‧One Column 230‧‧‧Plug opening 302‧‧‧Top 304‧‧‧Bottom 306‧‧‧Back 308‧‧‧Front 310‧‧‧Right 320‧‧‧Pair of lugs 402,1300‧‧Base 404‧‧‧Protection layer 406, 408, 410, 412, 414, 416, 418, 420‧‧‧ Through holes 422, 424, 426, 428, 430, 432, 434, 436, 1338, 1340, 1344, 1346, 1408, 1410, 1414, 1416‧‧‧Stitch 454,456,458,460,462,464,466,468‧‧‧Part 470,472,474,476,478,480,482,484‧‧‧ The second part 486, 488‧‧‧shielding lugs 490, 502‧‧‧shielding trace layer 504, 506, 508, 510, 512, 514, 516, 518‧‧‧ return through hole 602, 1202‧‧ Floor 604, 1204‧‧‧Second floor 606, 1206‧‧‧ Third floor 608, 1208‧‧‧ Fourth floor 610‧‧‧Fifth floor 612‧‧‧Second return signal layer 902-918‧‧ ‧Step 1100‧‧‧High-speed communication socket 1102‧‧‧Socket housing 1202‧‧‧Top layer 1210‧‧‧First middle layer 1212‧‧‧Second middle layer 1214‧‧‧Third middle layer 1216‧‧‧Top Weld cover layer 1306, 1308, 1310, 1312, 1314, 1316, 1318, 1320‧‧‧ First through hole 1322, 1324, 1326, 1328, 1330, 1332, 1334, 1336‧‧‧ Second through hole 1342, 1412 ‧‧‧First isolation zone 1348, 1418‧‧‧Second isolation zone 1350, 1420‧‧‧ Third isolation zone 1352 ‧Second Ground Floor 1406‧‧‧Bottom Floor

圖1例示依據本揭示之各個面向的一個實施例組配的高速通訊插座其包括RJ45插座,Fig. 1 illustrates a high-speed communication socket assembled according to an embodiment of the various aspects of the present disclosure, which includes an RJ45 socket,

圖2例示圖1之RJ45插座110的左側部之底視透視圖,FIG. 2 illustrates a bottom perspective view of the left side of the RJ45 socket 110 of FIG. 1,

圖3例示用來給圖1之RJ45插座及可撓性印刷電路板提供屏蔽的插座罩之底視及右側視圖,Fig. 3 illustrates the bottom and right side views of the socket cover used to provide shielding for the RJ45 socket and flexible printed circuit board of Fig. 1,

圖4A例示圖1之印刷電路板的前表面之頂視示意代表圖,4A illustrates a schematic top view representative view of the front surface of the printed circuit board of FIG. 1,

圖4B例示圖1之印刷電路板的前表面之頂視示意代表圖的另一實施例,FIG. 4B illustrates another embodiment of the schematic representation of the top view of the front surface of the printed circuit board of FIG. 1,

圖5A例示圖4之印刷電路板的後表面之頂視示意代表圖,FIG. 5A illustrates a schematic top view representative view of the back surface of the printed circuit board of FIG. 4,

圖5B例示圖4之印刷電路板的前表面之頂視示意代表圖的另一實施例,FIG. 5B illustrates another embodiment of the top view schematic representation of the front surface of the printed circuit board of FIG. 4,

圖6A例示圖4之印刷電路板的基體沿線BB之剖面圖,6A illustrates a cross-sectional view of the substrate of the printed circuit board of FIG. 4 along line BB,

圖6B例示圖4之印刷電路板中一通孔之剖面圖,6B illustrates a cross-sectional view of a through hole in the printed circuit board of FIG. 4,

圖6C例示圖4之印刷電路板中一通孔的另一釋例之剖面圖,6C illustrates a cross-sectional view of another example of a through hole in the printed circuit board of FIG. 4,

圖7例示具有彼此匹配及平衡的發射及接收電纜對的RJ45插座之示意代表圖,Figure 7 illustrates a schematic representation of an RJ45 socket with matched and balanced transmitting and receiving cable pairs,

圖8例示一差分平衡對之信號線的示意代表圖,Figure 8 illustrates a schematic representation of the signal line of a differential balanced pair,

圖9例示使用來基於一第一信號及一第二信號差分平衡圖4中之二線跡的方法之示意代表圖,FIG. 9 illustrates a schematic representation of the method used to differentially balance the two traces in FIG. 4 based on a first signal and a second signal,

圖10A例示圖1之RJ45插座其罩被去除的後側透視圖;Figure 10A illustrates a rear perspective view of the RJ45 socket of Figure 1 with its cover removed;

圖10B例示圖1之RJ45插座其罩被去除的另一實施例之後側透視圖;FIG. 10B illustrates a rear perspective view of another embodiment of the RJ45 socket of FIG. 1 with its cover removed; FIG.

圖11描繪包括一剛性基體的高速通訊插座之一個實施例;Figure 11 depicts an embodiment of a high-speed communication socket including a rigid base;

圖12描繪於剛性高速通訊插座中之該等層的示意代表圖,Figure 12 depicts a schematic representation of the layers in a rigid high-speed communication socket,

圖13A描繪高速通訊插座之側視圖;Figure 13A depicts a side view of a high-speed communication socket;

圖13B描繪該剛性基體的頂視圖;Figure 13B depicts a top view of the rigid substrate;

圖14A描繪該基體之一地面層;Figure 14A depicts a ground layer of the substrate;

圖14B描繪該基體之一第二地面層;Figure 14B depicts a second ground layer of the substrate;

圖14C描繪該基體之一底層;Figure 14C depicts a bottom layer of the substrate;

圖14D描繪該剛性基體之一第四層;Figure 14D depicts a fourth layer of the rigid substrate;

圖15A顯示於正常操作期間插座之差分模式版本的插入損耗;Figure 15A shows the insertion loss of the differential mode version of the socket during normal operation;

圖15B描繪於正常操作中針對插座之近場串擾的線圖表示型態;Figure 15B depicts a line graph representation of the near-field crosstalk of the socket during normal operation;

圖15C描繪於正常操作中針對插座之近場串擾的線圖表示型態;Figure 15C depicts a line graph representation of the near-field crosstalk of the socket in normal operation;

圖15D描繪於正常操作期間針對插座之返回損耗;Figure 15D depicts the return loss for the socket during normal operation;

圖15E描繪於正常操作期間針對插座之遠端串擾的線圖表示型態;及Figure 15E depicts a line diagram representation of the far-end crosstalk of the socket during normal operation; and

圖15F描繪於正常操作期間針對插座之遠端串擾的另一線圖表示型態。Figure 15F depicts another line graph representation of the far-end crosstalk of the socket during normal operation.

110‧‧‧RJ45插座 110‧‧‧RJ45 socket

120‧‧‧可撓性PCB 120‧‧‧Flexible PCB

130‧‧‧插座罩 130‧‧‧Socket cover

Claims (8)

一種高速通訊插座,其包括:一殼體,該殼體包括用於接納一插頭的一埠口,該埠口包括各自連結至該插頭中之一對應信號線的多數針腳;包圍該殼體的一屏蔽外殼;於該殼體中之一電路板,該電路板具有一基體,延伸貫穿該基體的多數第一通孔而各個第一通孔係經組配以容納該殼體上的一針腳,延伸貫穿該基體的多數第二通孔而各個第二通孔係經組配以容納該殼體上的一針腳,於該基體之一頂層上的一第一集合之線跡,其連結至少一個第一通孔與至少一個對應第二通孔;於該基體中之該頂層之一第一側上的一第一屏蔽層;於該基體中相鄰該第一屏蔽層的一第二屏蔽層;及於該基體之與該頂層相對之一側上的一第二集合之線跡,其連結至少一個第一通孔與至少一個第二通孔,其中該第一集合之線跡中之各線跡係由頂面上的一第一集合之隔離區所間隔,以及該第二集合之線跡中之各線跡係由與該頂面相 對之表面上的一第二集合之隔離區所間隔。 A high-speed communication socket, comprising: a shell, the shell includes a port for receiving a plug, the port includes a plurality of pins each connected to a corresponding signal line in the plug; A shielding shell; a circuit board in the housing, the circuit board has a base, extending through the base of a plurality of first through holes, and each first through hole is assembled to accommodate a pin on the housing , A plurality of second through holes extending through the base body and each second through hole is assembled to accommodate a stitch on the housing, a first set of stitches on the top layer of the base body, which connect at least A first through hole and at least one corresponding second through hole; a first shielding layer on a first side of the top layer in the substrate; a second shielding adjacent to the first shielding layer in the substrate Layer; and a second set of stitches on the side of the substrate opposite to the top layer, which connects at least one first through hole and at least one second through hole, wherein one of the first set of stitches Each stitch is separated by an isolation area of a first set on the top surface, and each stitch in the second set of stitches is separated from the top surface It is separated by a second set of isolation regions on the surface of the pair. 如請求項1之插座,其中該第二集合之線跡連結不同通孔而該等通孔連結至該頂面上。 Such as the socket of claim 1, wherein the stitches of the second set connect different through holes and the through holes are connected to the top surface. 如請求項1之插座,其中該第一屏蔽層係被覆蓋於一導電材料中。 Such as the socket of claim 1, wherein the first shielding layer is covered in a conductive material. 如請求項3之插座,其中該導電材料不覆蓋環繞該等第一通孔及第二通孔之周邊的一區。 Such as the socket of claim 3, wherein the conductive material does not cover an area surrounding the peripheries of the first through holes and the second through holes. 如請求項1之插座,其中該第二屏蔽層係被覆蓋於一導電材料中。 Such as the socket of claim 1, wherein the second shielding layer is covered in a conductive material. 如請求項5之插座,其中該導電材料不覆蓋環繞該等第一通孔及第二通孔之周邊的一區。 Such as the socket of claim 5, wherein the conductive material does not cover an area surrounding the peripheries of the first through holes and the second through holes. 如請求項3之插座,其中該導電材料係包含銅及精加工銀。 Such as the socket of claim 3, wherein the conductive material includes copper and refined silver. 如請求項5之插座,其中該導電材料係包含銅及精加工銀。 Such as the socket of claim 5, wherein the conductive material includes copper and refined silver.
TW106114632A 2016-05-04 2017-05-03 High speed communication jack TWI743118B (en)

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