JP2019519068A - High-speed communication jack - Google Patents

Abstract

Receiving the plug and forming a housing having a port having a plurality of pins respectively connected to corresponding signal lines of the plug, a first shield layer on the top layer of the substrate, the first side of the top layer of the substrate And forming a second shield layer adjacent to the first shield layer of the substrate, forming a bottom layer adjacent to the second shield layer, and each first via receiving the pin on the housing Forming a plurality of first vias through the substrate, and a plurality of second through holes through the substrate, each second via being configured to receive a pin on the housing Forming a via in the method of manufacturing a high speed jack.
[Selected figure] Figure 1

Description

[Cross-reference to related applications]
The present disclosure claims the benefit of US Provisional Patent Application No. 61 / 598,288, filed Feb. 13, 2012, and claims priority to the provisional US patent application, and is hereby incorporated by reference into the present US Patent No. 8,858. U.S. Pat. No. 6,798,200, which is a continuation-in-part of U.S. patent application Ser. No. 13 / 739,214, filed Jan. 11, 2011, and claims priority to such U.S. patent application, filed on Jan. 11, 2011; No. 337,592, which is a continuation-in-part of U.S. Patent Application No. 14 / 504,088, filed Oct. 1, 2014, and claiming priority to such U.S. Patent Application; No. 627,816, which is a PCT application of US patent application Ser. No. 15/146019, filed May 4, 2016. All of these U.S. patents and U.S. patent applications are hereby incorporated by reference in their entirety.

  The present disclosure relates to a network connection jack used to connect a network cable to a device.

  As telecommunications equipment and related applications of telecommunications equipment become more sophisticated and powerful, the ability of telecommunications equipment to collect information and share information with other equipment also becomes more important. The proliferation of these intelligent network-to-network devices makes it necessary to increase the data processing capacity on the network to which these devices are connected and to provide the improved data rates needed to meet this demand. . As a result, existing communication protocol standards are constantly improved or new standards are being created. Nearly all of these standards require or benefit significantly from the communication of high definition signals directly or indirectly through a wired network. The transmission of these high definition signals may have higher bandwidth and correspondingly higher frequency requirements and needs to be supported in a consistent manner. However, even though newer versions of the various standards provide theoretically higher data rates or data rates, these high definition signals are still subject to speed limitations due to the current design of certain physical components . Unfortunately, the design of such physical components is faced with difficulties by not being understood what is needed to achieve consistent signal quality at multi-gigahertz and higher frequencies.

  For example, communication jacks are used in communication equipment and devices that connect or connect cables used to transmit and receive electrical signals representing the data being communicated. Registered Jack (RJ) is a standardized physical interface used to connect telecommunications and data devices. The RJ standardized physical interface has both a jack structure and a wiring pattern. The RJ standardized physical interface commonly used for data devices is the RJ45 physical network interface, also called RJ45 jack. RJ45 jacks are widely used in local area networks, such as networks implementing the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet protocol. RJ45 jacks are described in various standards, including those published by the American National Standards Institute (ANSI) / American Telecommunications Industry Association (TIA) in ANSI / TIA-1096-A.

  All electrical interface components such as cables and jacks, including RJ45 jacks, not only resist the initial flow of current, but also counter any change in current. This characteristic is called reactance. The two relevant types of reactance are inductive reactance and capacitive reactance. Inductive reactance may occur, for example, based on the movement of current flowing through the cable to create a resistance, causing a magnetic field to induce a voltage in the cable. On the other hand, capacitive reactance is generated by the charge that appears when the electrons from two opposing surfaces approach each other.

  Preferably, the various components of the communication circuit have a matching impedance so as to reduce or avoid any degradation of the transmitted signal. Otherwise, a load having one impedance value will reflect or echo a portion of the signal carried by the cable having different impedance levels, causing a signal failure. For this reason, designers and manufacturers of data communication equipment, such as cable builders and the like, must verify that their impedance values and their resistance and capacitance levels meet certain performance parameters. Design and test cables. Also, while RJ45 jacks are an important component in almost all communication circuits, jack manufacturers have not paid the same attention to jack performance. Thus, although the problems with the existing RJ45 jacks are well-proven in testing and the adverse effects of the existing RJ45 jacks on high frequency signal lines are understood, the industry is concerned with this important component of the physical layer It does not seem ambitious to deal with. As a result, there is a need for an improved high speed communication jack.

One embodiment of the present invention is
A housing having a port for receiving a plug and having a plurality of pins respectively connected to corresponding signal lines of the plug;
A shield case surrounding the housing;
A circuit board in said housing,
A substrate,
A plurality of first vias through the substrate, wherein each first via is configured to receive a pin on the housing;
A plurality of second vias through the substrate, each second via being configured to receive a pin on the housing;
A first set of traces in the top layer of the substrate connecting at least one first via to at least one corresponding second via;
A first shield layer on a first side of the top layer of the substrate;
A second shield layer adjacent to the first shield layer of the substrate;
A second set of traces on the opposite side of the top layer of the substrate connecting at least one first via to at least one second via;
With a circuit board,
Including a high speed communication jack.

  In another embodiment, the second set of traces connect vias different from the vias connected at the top surface.

  In another embodiment, the jack has a first isolation area between the first set of traces on the top surface.

  In another embodiment, the jack has a second isolation region between the second set of traces on the top surface.

  In another embodiment, the first shield layer is coated with a conductive material.

  In another embodiment, the conductive material does not cover an area around the periphery of the first via and the second via.

  In another embodiment, the second shield layer is coated with a conductive material.

  In another embodiment, the conductive material does not cover an area around the periphery of the first via and the second via.

  In another embodiment, the conductive material is comprised of copper and finished silver.

  In another embodiment, the conductive material is comprised of copper and finish silver.

Another embodiment of the invention is
Receiving the plug and forming a housing having a port having a plurality of pins respectively connected to corresponding signal lines of the plug;
Forming a shield case surrounding the housing;
Forming a top layer of the substrate, a first shield layer on a first side of the top layer of the substrate, and a second shield layer adjacent to the first shield layer of the substrate;
Forming a bottom layer adjacent to the second shield layer;
Forming a plurality of first vias through the substrate, wherein each first via is configured to receive a pin on the housing;
Forming a plurality of second vias through the substrate, wherein each second via is configured to receive a pin on the housing;
Forming a first set of traces in the top layer of the substrate connecting at least one first via with at least one corresponding second via;
Forming a second set of traces on the opposite side of the top layer of the substrate, connecting at least one first via to at least one second via;
Including methods of manufacturing high speed jacks.

  In another embodiment, the second set of traces connect vias different from the vias connected at the top surface.

  In another embodiment, the method includes forming a first isolation region between the first set of traces on the top surface.

  In another embodiment, the method includes forming a second isolation region between the second set of traces on the top surface.

  In another embodiment, the first shield layer is coated with a conductive material.

  In another embodiment, the conductive material does not cover an area around the periphery of the first via and the second via.

  In another embodiment, the second shield layer is coated with a conductive material.

  In another embodiment, the conductive material does not cover an area around the periphery of the first via and the second via.

  In another embodiment, the conductive material is comprised of copper and finish silver.

  In another embodiment, the conductive material is comprised of copper and finish silver.

FIG. 7 illustrates a high speed communication jack comprising an RJ45 jack configured in accordance with an embodiment of various aspects of the present disclosure. It is a figure of the lower surface isometric view part of the left side part of RJ45 jack of FIG. FIG. 2 is a bottom and right side view of a jack shield providing a shield for the RJ45 jack and flexible printed circuit board of FIG. 1; It is the plane schematic of the front surface of the printed circuit board of FIG. FIG. 5 is a schematic plan view of the front side of another embodiment of the printed circuit board of FIG. 1; FIG. 5 is a schematic plan view of the back surface of the printed circuit board of FIG. 4; FIG. 5 is a schematic plan view of the back side of another embodiment of the printed circuit board of FIG. 4; 5 is a cross-sectional view of the substrate of the printed circuit board of FIG. 4 taken along line BB. FIG. 5 is a cross-sectional view of a via in the printed circuit board of FIG. 4; FIG. 5 is a cross-sectional view of another example of a via in the printed circuit board of FIG. 4; FIG. 7 is a schematic diagram of an RJ45 jack with transmit and receive cable pairs aligned and balanced with one another. FIG. 5 is a schematic view of a pair of differentially balanced signal lines. FIG. 5 is a schematic diagram of a process used to differentially balance the two traces in FIG. 4 based on the first and second signals. FIG. 7 is a rear perspective view of the RJ45 jack of FIG. 1 with the shield removed; FIG. 7 is a rear perspective view of another embodiment of the RJ45 jack of FIG. 1 with the shield removed. FIG. 5 illustrates one embodiment of a high speed communication jack with a rigid board. FIG. 2 is a schematic view of the layers in a rigid high speed communication jack. It is a side view of the jack for high-speed communication. It is a top view of a rigid board. It is a figure which shows the ground layer of a board | substrate. Fig. 2 shows a second ground layer of the substrate; It is a figure which shows the lowest layer of a board | substrate. It is a figure which shows the 4th layer of a rigid board | substrate. FIG. 7 illustrates the insertion loss of the differential mode version of the jack during normal operation. FIG. 7 is a graph of the near field cross talk of the jack during normal operation. FIG. 5 is a graph of the near-field crosstalk of the jack during normal operation. It is a figure which shows the reflective loss of the jack in normal operation. FIG. 7 is a graphical representation of the far-end crosstalk of the jack during normal operation. FIG. 7 is another graphical illustration of the far-end crosstalk of the jack during normal operation.

  FIG. 1 illustrates a high speed communication jack configured in accordance with an embodiment of various aspects of the present disclosure. The high-speed communication jack includes an RJ45 jack 110, a flexible printed circuit board (PCB) 120, and a jack shield 130. As described herein, according to various aspects of the present disclosure, the flexible PCB 120 provides a balanced radio frequency tuning circuit that can be soldered directly to each pin of the RJ45 jack 110. On the other hand, the jack shield 130 provides a shield for the RJ45 jack 110 and the flexible PCB 120 and functions as a chassis ground. The RJ 45 jack 110, the flexible PCB 120, and the jack shield 130, when combined, may provide similar functionality as a tuning waveguide and a tube through which communication signals can be transmitted. In this case, the energy portion of the communication signal travels through the jack shield 130 outside the tube and the information portion of the communication signal travels along the non-resistant gold wire in the tube. This makes it possible to obtain high data rates. For example, it is envisioned that data rates of 40 gigabits (Gbs) or higher can be supported.

  Although an RJ45 communication jack is used below, the communication jack is not limited to the RJ45 communication jack, and may be used in any type of high-speed communication jack. As jacks for high-speed communication, all types of modular RJ type connectors, universal serial bus (USB) connectors and jacks, firewire (1394) connectors and jacks, HDMI (high-definition multimedia interface) connectors and jacks, D-subminiature Examples include type connectors and jacks, ribbon type connectors or jacks, or any other connector or jack that receives high speed communication signals.

  In various aspects of the present disclosure, the various pins and traces disclosed herein are a combination of any suitable conductive element and any suitable conductive element such as gold, silver or copper, or an alloy. May be composed of For example, one set of pins and plug contacts of RJ45 jack 110 may include gold plated copper pins or copper wires. On the other hand, one set of traces on flexible PCB 120 may include gold plated copper vias. Gold plating is used to apply a corrosion resistant conductive layer to copper, a material that is usually susceptible to oxidation. Alternatively, a suitable barrier metal layer such as nickel may be deposited on the copper substrate prior to gold plating. The nickel layer can improve the wear resistance of the gold plating by providing a mechanical backing to the gold layer. Also, the nickel layer can reduce the effects of pores that may be present in the gold layer. At higher frequencies, gold plating can not only reduce signal loss, but can also increase bandwidth by the skin effect where the current density is highest on the outer edge of the conductor. In contrast, using nickel alone causes signal degradation at higher frequencies due to the same effect. Thus, higher speeds may not be achieved with RJ45 jacks that use nickel plating alone. For example, a nickel only plated pin or trace may have its own useful signal length reduced by a factor of three when the signal is in the GHz range. Although some benefits of using gold plating on the surface of copper pathways are described herein, other conductive elements may be used to plate copper pathways. For example, instead of gold, platinum, which is also a non-reactive but good conductor, may be used to plate the copper path.

  Each of the major components of the high speed communication jacks, namely RJ45 jack 110, flexible printed circuit board (PCB) 120 and jack shield 130, which these components achieve support for high speed communication Before providing a discussion of how to work together, it will be briefly described herein.

  FIG. 2 shows a bottom perspective view of the front of the RJ45 jack 110 of FIG. Here, it can be seen that a plug opening 230 is provided for inserting a plug (not shown). The plug opening 230 may be configured to receive the plug and couple the contacts on the plug to a set of plug contacts 212 on the RJ45 jack 110. The plug may be an RJ45 8-pole 8-core (8P8C) modular plug. The set of plug contacts 212 is formed into a set of pins 210 configured to be attached to communication circuitry on the circuit board. For example, RJ45 jack 110 may be attached to the circuit board of the network switch device by the use of a pair of posts 220. Thereafter, a set of pins 210 may be soldered to respective contact pads on the circuit board of the device. A jack similar to the RJ45 jack 110 as shown in FIG. 2 alone provides basic connectivity between the plug of the RJ45 cable and the circuit board of the device into which the jack is integrated. However, the jack is not designed to handle the communication frequency required for high speed communication. The RJ45 jack 110 configured in accordance with various aspects of the disclosed approach described herein may be integrated with other components such as the jack shield 130 and the flexible PCB 120, thereby making the RJ45 jack 110 It can be used to communicate at higher speeds without interference from the transition signal.

  FIG. 3 shows a bottom and right side view of a jack shield that provides a shield for the RJ45 jack 110 and the flexible PCB 120. The jack shield 130 has an upper portion 302, a lower portion 304, a rear portion 306, a front portion 308, a left side (not shown but substantially the same as the right side), and a right side 310. In one embodiment of the present disclosure, jack shield 130 may comprise a conductive material, such as, but not limited to, steel, copper, or any other conductive material to provide the desired shielding properties. With both the right side 310 and the left side (not shown) of the jack shield 130, using a pair of tabs 320 near the lower portion 304, the jack shield 130 is grounded and the circuit board in the device (not shown) It may be fixed to For example, the pair of tabs 320 on the jack shield 130 may be inserted into a pair of matching mounting holes on the circuit board and soldered to the circuit board.

  FIG. 4A shows a top schematic view of the front of the PCB 120 of the RJ45 jack. The PCB 120 includes a multi-layer substrate 402 made of dielectric material incorporating stripline flex or similar technology. The edge of the substrate 402 is surrounded by a protective layer 404. Protective layer 404 is made of a non-conductive material such as, but not limited to, a plastic or flexible solder mask. The front side of the substrate 402 has a plurality of vias 406, 408, 410, 412, 414, 416, 418 and 420 created through the substrate 402. Each via 406, 408, 410, 412, 414, 416, 418, and 420 passes through the substrate 402 and is sized to receive the pin 210. The area surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 is coated with a conductive material such as gold. The coating surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 can be substantially square or substantially rectangular. In another embodiment shown in FIG. 4B, the coating surrounding each via 406, 408, 410, 412, 414, 416, 418, and 420 can be substantially circular. Making the coating circular reduces interference between adjacent vias 406, 408, 410, 412, 414, 416, 418 and 420.

  A plurality of traces 422, 424, 426, 428, 430, 432, 434 and 436 extend from each via 406, 408, 410, 412, 414, 416, 418 and 420 towards the end of the PCB 120. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 is made of a conductive material including copper or gold. In one embodiment, a nickel layer is formed on the substrate 402 and a gold layer is formed on the nickel layer to form each trace 422, 424, 426, 428, 430, 432, 434, and 436. Each trace 422, 424, 426, 428, 430, 432, 434 and 436 is a trace 422, 424, 426, 428, 430, 432, 434 or 436 is a via 406, 408, 410, 412, 414, It extends towards the back end of the PCB 120 until it reaches the shield trace layer 490 near the edge of the PCB 120 opposite to 416, 418 and 420. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 has a first portion 454, 456, 458, 460, 462, 464, 466, and 468, the first portion being Adjacent to the second portions 470, 472, 474, 476, 478, 480, 482 and 484. Each second portion 470, 472, 474, 476, 478, 480, 482, and 484 extends into shield trace layer 490 without contacting shield trace layer 490. Each of the first portions 454, 456, 458, 460, 462, 464, 466, and 468 are from respective vias 406 from the respective second portions 470, 472, 474, 476, 478, 480, 482, and 484. , 408, 410, 412, 414, 416, 418 or 420, respectively. Each second portion 470, 472, 474, 476, 478, 480, 482, and 484 has a length that varies in response to the traces 422, 424, 426, 428, 430, 432, 434, or 436.

  Two shield tabs 486 and 488 are positioned on opposite edges of the PCB 120. Each shield tab 486 and 488 is made of a substrate coated with a conductive material, such as gold or copper. Shield tabs 486 and 488 are electrically connected by shield trace layer 490 on substrate 402. The shield trace layer 490 extends between the shield tabs 486 and 488, and the second portions 470, 472, 474, 476, 478, of each trace 422, 424, 426, 428, 430, 432, 434, and 436. Positioned between 480, 482 and 484 and the edge of the PCB 120 opposite the vias 406, 408, 410, 412, 414, 416, 418 and 420.

  FIG. 5A shows a plan schematic view of the back surface of the printed circuit board of FIG. 4A. The back surface includes vias 406, 408, 410, 412, 414, 416, 418, and 420, shield tabs 486 and 488, and a shield trace layer 502 extending between the back surface of each shield tab 486 and the back surface of 488. Have. Shield trace layer 502 covers the portion of the back surface of PCB 120 between shield tabs 486 and 488. Shielding tabs 486 and 488 have return vias 504, 506, 508, 510, 512, 514, 516, and 518 connecting shield trace layer 490 and shield trace layer 502 through substrate 402. FIG. 5B shows a plan view of the back of another embodiment of the printed circuit board of FIG. 4B.

  FIG. 6A shows a cross-sectional view of multilayer substrate 402 of PCB 120 along line BB of FIG. The first layer 602 of the multilayer substrate 402 has a solder mask portion made of a material such as PSR 9000 FST flexible solder mask. A second layer 604 is formed below the top layer and includes traces 422, 424, 426, 428, 430, 432, 434, and 436, respectively. Each trace 422, 424, 426, 428, 430, 432, 434, and 436 has a length (L), a height (H) and a width (W) and is a distance (S) from the adjacent trace It is separated. The length (L) of each trace is from the edge of each of the vias 406, 408, 410, 412, 414, 416, 418, and 420 of the flexible circuit board 120 along the surface of the flexible circuit board 120. It is a length extending to the shield trace layer 490.

  Each trace 422, 424, 426, 428, 430, 432, 434, and 436 is a first such that each trace 422, 424, 426, 428, 430, 432, 434, and 436 is not covered by the flexible solder mask. Extending through the layer 602 of Also, a shield trace layer 490 is formed on a portion of the second layer 604, and the shield trace layer 490 extends through the first layer 602. A third dielectric layer 606 is formed below the second layer 604. The third layer 606 is made of a material having a depth (D) of about 0.002 mils to about 0.005 mils and having a dielectric constant greater than 3.0. This material may be, but is not limited to Rogerson Material RO XT 8100 or any other material capable of isolating high frequency electrical signals.

  A fourth layer 608 is formed below the third layer 606. The fourth layer 608 includes signal return and shield trace portions 502. Both the signal return and the shield trace 502 are made of a conductive material, preferably gold or copper. A fifth layer 610 is formed on the fourth layer 608. The fifth layer 610 has a flexible solder mask portion and a shield trace layer 502 portion. The flexible solder mask portion is made of the same material as the flexible solder mask portion of the first layer 602. In an alternative example, the flexible solder mask portion is made of a different material than the flexible solder mask of the first layer 602. In an alternative example, the second signal return layer (not shown) may be positioned on the dielectric material.

  Each trace 422, 424, 426, 428, 430, 432, 434, and 436 may be adjacent to the trace 422, 424, 426, 428, 430, 432, 434 to eliminate crosstalk caused by the adjacent trace. And 436 electrically. As an illustrative example, trace 422 may be coupled to trace 424. In operation, a first signal is transmitted along the first trace and an identical signal with reverse polarity is transmitted along the matching trace so that the traces are differentially coupled together. Because the traces are differentially coupled together, the impedance of each trace determines how the traces are driven. Correspondingly, the impedances of each set of matching traces should be approximately equal.

  The physical properties of each trace 422, 424, 426, 428, 430, 432, 434, and 436 in the matched set of traces are between the matched traces for transmit and return signals transmitted through each trace. It is adjusted to balance the impedance. The impedance of each trace 422, 424, 426, 428, 430, 432, 434, and 436 is for each signal transmitted through each trace 422, 424, 426, 428, 430, 432, 434, and 436, Adjustment is made by adjusting any one or a combination of the length (L), width (W), height (H), and spacing (S) between matching traces of each trace. The height (H) of each trace 422, 424, 426, 428, 430, 432, 434, and 436 may be approximately 2 mils to approximately 6 mils, and adjacent traces 422, 424, 426, 428, 430, The spacing (S) between 432, 434 and 436 may be approximately 3 mils to approximately 10 mils.

  Returning to FIG. 4, each trace has a variable width in the first portions 454, 456, 458, 460, 462, 464, 466, and 468 and a second portion 470, 472, 474, 476, 478, And a substantially constant width at 480 and 482. Accordingly, the width of each trace 422, 424, 426, 428, 430, 432, 434, and 436 is either the first portion 454, 456, 458, 460, 462, 464, 466, or 468 or the second Or any of the first portions 454, 456, 458, 460, 462, 464, 466, and 468 and the second portions 470, 472 and 464, 476, 478, 480, and 482, respectively. The height (H) of the traces 422, 424, 426, 428, 430, 432, 434 and 436 is adjusted at both 472, 474, 476, 478, 480 and 482. Thereby, each trace in the matching set has substantially the same impedance when the matching traces are separated by a distance (S).

  Due to manufacturing and material inconsistencies, the signals driven through each set of differentially matched traces 422, 424, 426, 428, 430, 432, 434 and 436 may not be identical , Thereby reflecting part of the signal back, causing common mode interference. To eliminate any common mode interference, each trace 422, 424, 426, 428, 430, 432, 434, or 436 in the matched set of traces is adjusted to eliminate any common mode interference in the matched set It has a common mode filter. Each filter comprises a via 406, 408, 410, 412, 414, 416, 418 or 420 of each trace 422, 424, 426, 428, 430, 432, 434 or 436 and a fourth layer of the multilayer substrate 402 And 608 is formed of a capacitor. A second layer 604 of the substrate 402 around the perimeter of each of the vias 406, 408, 410, 412, 414, 416, 418, and 420 is a via 402, 408, 410, 412, 414, 416, 418, and 420. And a conductive material layer such as gold or copper formed on the fourth layer 608. The conductive material on the first layer 602 is in the traces 422, 424, 426, 428, 430, 432, 434 or 436 corresponding to the vias 406, 408, 410, 412, 414, 416, 418 and 420. Connected, the conductive material on the fourth layer 608 is connected to the signal return of the fourth layer 608. The size of each capacitor is determined by the distance between the conductive materials on the second layer 604 and the fourth layer 608. Correspondingly, by adjusting the depth of the third layer 606 to the conductive material on the vias 406, 408, 410, 412, 414, 416, 418 and 420, each via 406, 408, 410 , 412, 414, 416, 418, and 420 can be adjusted. The capacitor produced by the vias 406, 408, 410, 412, 414, 416, 418 and 420 and the return of the fourth layer 608 has a size of approximately 0.1 picofarads (pf) to approximately 0.5 pf It is. The top and bottom surfaces of the substrate 402 may be coated with a plastic insulating layer to further enhance the operation of the circuit.

  The combination of the capacitor created in each via 406, 408, 410, 412, 414, 416, 418 and 420 and the characteristic inductance of the signal return layer results in each trace 422, 424, 426, 428, 430, 432 , 434, or 436 are created. By adjusting the capacitance value of each capacitor based on the impedance of traces 422, 424, 426, 428, 430, 432, 434, and 436, common mode noise is significantly reduced, thereby reducing each trace 422, Signal processing on 424, 426, 428, 430, 432, 434 and 436 is improved.

  FIG. 6B shows a cross-sectional schematic of the vias 406, 408, 410, 412, 414, 416, 418 or 420. Each of the vias 406, 408, 410, 412, 414, 416, 418, and 420 is a first layer 602, a second layer 604, a third layer 606, a fourth layer 608, and a fifth layer 610. Formed through. The second layer 604 is made of a conductive material such as gold or copper and surrounds the perimeter of each via 406, 408, 410, 412, 414, 416, 418 and 420. Also, the second layer 604 may include each via 406, 408, 410, 412, 414, 416, 418, and 420 as a trace 422, 424, 426, 428, 430, 432, 434 of the second layer 604, respectively. Or connect to 436. The third layer 606 functions as a dielectric layer as described in FIG. 6A. The fourth layer 608 is formed on the third layer 606 and functions as a signal return layer. The fifth layer 610 is likewise made of a conductive material such as copper or gold and, like the second layer 602, likewise surrounds the outer periphery of the via. A sealing layer (not shown) may also be formed on the fifth layer 610.

  The fourth layer 608 is separated from the second layer 604 by a distance D 1 and from the fifth layer 610 by a second distance D 2. The combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 creates a capacitor having a capacitance value of approximately 0.1 pf to 0.5 pf. By adjusting the distance D1 of the fourth layer 608 to the second layer 604, the capacitance value of the via capacitor is adjusted. The combination of the second layer 604, the third dielectric layer 606, and the fourth return signal layer 608 allows the common mode filter to be implemented as the via connects its associated trace to the fourth return signal layer 608. It is formed. This common mode filter removes any interference caused by signal reflections resulting from manufacturing process failure. By adjusting the capacitance value of the via capacitors, the common mode filter may be adjusted to eliminate nearly all signal noise caused by reflection of the transmit or return signal.

  FIG. 6C shows another example of a cross-sectional view of the vias 406, 408, 410, 412, 414, 416, 418 and 420. A second return signal layer 612 is added to the third layer 606 between the first return signal layer 608 and the fifth layer 610. The second return signal layer 612 extends parallel to the first signal layer 608 to enhance the filtering effect of the common mode filter. By adjusting the distance D3 between the first return signal layer 608 and the second return signal layer 612, the first return signal layer 608, the third layer 606, and the second return signal layer 612 can be obtained. And a second capacitor formed by and is created in the via. By adjusting the distance D3, the value of the second via capacitor may be adjusted to improve the operation of the common mode filter. Furthermore, as we have identified, forming a second capacitor in the via allows the traces to be aligned on the spaced ends of the PCB 102. As an illustrative example, trace 422 may be matched to trace 436. Accordingly, by forming the second capacitor, multiple pairs of signal lines positioned according to the RJ45 standard can be realized.

  FIG. 7 shows a schematic diagram of an RJ45 jack with matching transmit and receive traces. Impedance match the transmit and receive lines by adjusting the height (H), width (W), and length (L) of each trace 422, 424, 426, 428, 430, 432, 434, or 436 It can be done. The same high frequency signal with opposite polarity is transmitted along each pair to improve the operation of the jack. Because the matching traces are coupled through a shield, these pairs function as a common mode filter for each other. Also, even if one signal can not be transmitted, the corresponding reverse signal line transmits the same signal. Because the matched traces act as a filter coupled to the shield, the noise caused by the high bandwidth transmission is filtered out of the signal. Furthermore, since the transmission line is aligned with the reception line, filtering of the signal is performed with higher accuracy. Because the reference point of the filter is not the ground connection but the signal itself.

  FIG. 8 shows a schematic of a differentially balanced pair of signal lines. As the figure shows, the characteristics of each trace are adjusted to match the impedance of the first trace to the impedance of the second trace using the method described above. Furthermore, the capacitors formed in each via form a common mode filter in which return signal lines are embedded in the PCB 120. By differentially balancing the two traces during transmission of both the transmit signal and the response signal, a well-balanced bi-directional communication circuit is achieved.

  FIG. 9 shows a schematic of a method of balancing matching traces for transmit and return signals. At step 902, the physical properties of each trace in the matched pair of traces are adjusted so that the impedances of the traces are approximately equal. This physical property may include the height, length, and width of each trace, as well as the distance separating each trace in the matched set of traces. At step 904, a first signal having a first polarity is transmitted along the first trace in the matched set of traces. The first signal may be a high frequency communication signal operating at a frequency (positive) greater than 10 gigahertz ("GHz"). At step 906, a second signal substantially identical to the first signal and having a polarity opposite to the polarity of the first signal is simultaneously applied to the first signal and on the second trace of the matched set. Send to At step 908, a first signal is measured at the beginning and end of the trace and these two measurements are compared to determine the amount of data lost along the length of the trace. At step 910, at least one physical property of the first trace or the second trace is adjusted based on the measured amount of signal loss. This process may return to step 904 until the amount of signal loss is less than approximately 10 decibels ("db").

  At step 912, a third signal is sent on the second trace of the matched set of traces. At step 914, a fourth signal substantially identical to the third signal but having the opposite polarity to the third signal is transmitted on the first trace. At step 916, a third signal is measured at the beginning and end of the trace, and the two measurements are compared to determine the amount of data lost along the length of the trace. At step 918, at least one physical property of the first trace or the second trace is adjusted based on the measured amount of signal loss. This process may return to step 912 until the amount of signal loss is less than approximately 10 decibels ("db"). In another example, the process may return to step 904 to ensure that the signal loss of the first signal is not affected by the adjustment made in response to the third signal loss.

  FIG. 10 shows the PCB 120 being positioned at the jack 110. The substrate 402 of the PCB 120 is made of a flexible material that allows the first portion of the PCB 120 to face the second portion of the PCB 120 at an angle of approximately 90 degrees. Accordingly, the PCB 120 is positioned with the vias 406, 408, 410, 412, 414, 416, 418, and 420 on the pins 210 of the jack, and the traces 422, 424, 426, 428, 430, 432, 434, and 436 are bent to extend from the vias 406, 408, 410, 412, 414, 416, 418 and 420 to the contact pads for the jacks. Shield tabs 486 and 488 are bent to be approximately 90 degrees to PCB 120. Shield tabs 486 and 488 are positioned along the sides of the jack such that the jack shield 130 of the jack engages the shield tabs 486 and 488.

  Flexible PCB 120 may be implemented using any flexible plastic substrate that allows flexing of flexible PCB 120. As described herein, the flexible PCB 120 may be flexed or bent to conform to the existing form factor of the RJ45 jack 110 and to be shielded by the jack shield 130. For example, the flexible PCB 120 may be disposed between the RJ45 jack 110 and the jack shield 130 and attached to the RJ45 jack 110. Shield tabs 486 and 488 of flexible PCB 120 may be attached to jack shield 130 to provide a common connection to the flex circuit on flexible PCB 120. In that case, the set of pins 210 of the RJ45 jack 110 may be electrically coupled to the circuit board of the device in which the RJ45 jack 110 is used.

  The flexible PCB 120 may be configured to be folded to conform to the shape of the RJ45 jack 110 to better fit into existing enclosures such as the jack shield 130. For example, in one aspect of the disclosed approach, the flexible PCB 120 bends toward the middle section of the flexible PCB 120 at an angle of approximately 90 degrees and is bent into the jack shield 130. The shield tabs 486 and 488 of the flexible PCB 120 will be folded into contact on the jack shield 130 and may be soldered to secure the flexible PCB 120 to the jack shield 130. Those skilled in the art will recognize that the orientation of flexible PCB 120 relative to RJ45 jack 110 within jack shield 130 may vary according to various aspects of the present disclosure. For example, the flexible PCB 120 may be thin enough to flex and fold into the other side of the jack shield 130. The flexible PCB 120 may be shaped to generally follow the lower section 304 of the jack shield 130. At this time, bending or bending into the jack shield 130 is not required.

  The foregoing detailed description is merely some examples and embodiments of the present disclosure and deviating from the spirit or scope of the present disclosure herein, numerous modifications to the disclosed (positive) disclosed embodiments. It can be done according to the present disclosure without Accordingly, the above description is not intended to limit the scope of the present disclosure, but rather to provide a disclosure sufficient to enable one skilled in the art to practice the present invention without undue burden. There is.

  FIG. 11 illustrates one embodiment of a high speed communication jack with a rigid board. The high speed communication jack 1100 comprises a jack housing 1102 configured to receive a communication plug (not shown). The substrate 1300 is positioned on the lower surface of the housing, and thus, when installed, the pins 1306 extend from the substrate 1300 to engage the circuit board to which the jack is attached.

  FIG. 12 shows a schematic view of the layers in a rigid high speed communication jack. Substrate 1300 includes a top layer 1202 having a plurality of vias (not shown) each sized to receive a pin, a second layer 1204 having a plurality of impedance matching traces as described above, and the vias of the first layer 1202. A third layer 1206 and a fourth layer 1208 having concentrically aligned vias are provided. The first layer 1202 is separated from the second layer 1204 by a first intermediate layer 1210 made of a non-conductive material such as, but not limited to, the Rogers company. The second layer 1204 is separated from the third layer 1206 by the second intermediate layer 1212, and the third layer 1206 and the fourth layer 1208 are separated by the third intermediate layer 1214. The top solder mask layer 1216 is formed on the side opposite to the first intermediate layer 1210 of the first layer 1202. In one embodiment, the first layer 1202, the second layer 1204, the third layer 1206 and the fourth layer 1208 are composed of 1/4 oz copper and 1/4 oz finished silver. In one embodiment, the first middle layer 1210, the second middle layer 1212 and the third middle layer 1214 are made of Rogers R04003 material. In another embodiment, the first layer 1202 is adhered to the first middle layer 1210 by an adhesive, and the second layer 1204 and the third layer 1206 are adhered to the second middle layer 1212 by an adhesive. The third layer 1206 and the fourth layer 1208 are adhered to the third intermediate layer 1214 by an adhesive.

  FIG. 13A shows a side view of the high-speed communication jack. The jack comprises a rigid substrate 1300, which has a first set of pins 1302 on the lower side of the substrate 1300 and a second set of pins 1304 on the upper side of the substrate 1300. FIG. 13B shows a top view of the rigid substrate 1300. The rigid substrate 1300 engages a plurality of first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 through the substrate 1300 which engage with the first set of pins 1302 on the opposite side of the substrate 1300. Have. The first set of pins 1302 are configured to engage vias (not shown) on the circuit board to communicatively connect the jack and the circuit board. Each of the second set of pins 1304 is a second via 1322, 1324, 1326 located opposite the first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 of the substrate 1300. , 1328, 1330, 1332, 1334 and 1336, respectively. The second set of pins 1304 are configured to engage corresponding pins of the plug when the plug is inserted into the jack.

  A trace 1338 is formed on the top surface of the substrate 1300, the trace 1338 connects the second via 1326 to the first via 1310, and the trace 1340 connects the second via 1328 to the first via 1312 . A first isolation region 1342 is formed between trace 1338 and trace 1340 and isolation between these two traces 1338 and 1340 is provided. Trace 1344 connects second via 1334 to first via 1318, and trace 1346 connects second via 1336 to first via 1320. A second isolation region 1348 isolates trace 1340 from trace 1344 and a third isolation region 1350 isolates trace 1344 from trace 1346. The isolation surface 1352 is between the second vias 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336 and the edge of the substrate and the edges of the traces 1338 and 1346 and the substrate 1302 around the periphery of the substrate 1302. It extends between the parts. In one embodiment, the isolation area and the isolation surface are made of a material that is 1/4 oz copper and 1/4 oz silver. By isolating the different traces, the effects of electrical interference between the traces are reduced or eliminated. In one embodiment, a via is formed in each isolation region to connect the isolation region to the lower ground layer.

  FIG. 14A shows the ground layer 1400 of the substrate 1300. The ground layer 1400 is disposed adjacent to the top layer 1300. The ground layer 1400 has a ground plane 1402. The ground plane 1402 is an area around the periphery of the first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and the second vias 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336. To cover the surface of the ground layer 1400. The surface of the ground layer 1400 is coated with a conductive material to form a ground plane 1402. In one embodiment, the material is 1/4 oz copper and 1/4 oz silver.

  FIG. 14B shows the second ground layer 1404 of the substrate 1300. The second ground layer 1404 is coated with a conductive material, the coating comprising the first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and the second vias 1322, 1324, 1326, 1328, It covers substantially the entire surface of the second ground layer 1404 except for the area around 1330, 1332, 1334 and 1336. In one embodiment, the material covering the second layer 1404 is 1/4 oz copper and 1/4 oz silver.

  FIG. 14C shows the bottom layer 1406 of the substrate 1300. The lowermost layer 1406 includes first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and second vias 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336. Trace 1408 connects second via 1322 to first via 1306, and trace 1410 connects second via 1324 to first via 1308. Isolation region 1412 isolates trace 1408 from trace 1410. A second isolation region 1418 isolates trace 1410 from trace 1414 and a third isolation region 1420 isolates trace 1414 from trace 1416. The isolation surface 1422 is between the second via 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336 and the edge of the substrate 1302 around the periphery of the bottom layer 1406 and the traces 1408 and 1416 and the substrate 1302 Extends between the edge of the

  15A-15F show graphs of test results of the high-speed communication jack. FIG. 15A shows the insertion loss of the differential mode version of the jack during normal operation. As the graph shows, at speeds approaching 2000 MHz, the insertion loss is approximately 1.8 db. Figures 15B and 15C show graphs of the near-field crosstalk of the jack during normal operation. FIG. 15D shows the reflection loss of the jack during normal operation. This graph also shows the performance requirements of the IEEE 40 GBase-T standard. As the graph shows, at speeds approaching 2000 MHz, Jack performs better than the requirements of the IEEE 40 GBase-T standard. FIG. 15E shows a graphical representation of the far-end crosstalk of the jack during normal operation. This graph also shows the performance requirements of the IEEE 40 GBase-T standard. As the graph shows, at speeds approaching 2000 MHz, Jack performs better than the requirements of the IEEE 40 GBase-T standard. FIG. 15F shows another graphical representation of the far-end crosstalk of the jack during normal operation.

  By arranging and connecting traces and ground planes on the substrate 1300, as shown in FIGS. 15A-15F, this jack can transmit data at very high speed without interference. is there. Furthermore, arranging the layers of the substrate to provide multiple ground layers improves the isolation of traces on the substrate and further improves the performance of the jack.

  In the present disclosure, terms which do not specify a quantity should be construed to include both singular and plural. Conversely, any reference to more than one element is intended to include the singular as appropriate.

It should be understood that various changes and modifications to the preferred embodiments of the invention disclosed herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present disclosure and without diminishing its intended advantages. Accordingly, such changes and modifications are to be construed as being included within the scope of the appended claims.

Claims (20)

A housing having a port for receiving a plug and having a plurality of pins respectively connected to corresponding signal lines of the plug;
A shield case surrounding the housing;
A circuit board in said housing,
A substrate,
A plurality of first vias through the substrate, wherein each first via is configured to receive a pin on the housing;
A plurality of second vias through the substrate, each second via being configured to receive a pin on the housing;
A first set of traces in the top layer of the substrate connecting at least one first via to at least one corresponding second via;
A first shield layer on a first side of the top layer of the substrate;
A second shield layer adjacent to the first shield layer of the substrate;
A second set of traces on the opposite side of the top layer of the substrate connecting at least one first via to at least one second via;
With a circuit board,
Equipped with a high-speed communication jack.   The jack of claim 1, wherein the second set of traces connect vias different from the vias connected at the top surface.   The jack of claim 1, having a first isolation area between the first set of traces on the top surface.   The jack of claim 1, having a second isolation region between the second set of traces on the top surface.   The jack according to claim 1, wherein the first shield layer is coated with a conductive material.   6. The jack according to claim 5, wherein the conductive material does not cover an area around the periphery of the first via and the second via.   The jack according to claim 1, wherein the second shield layer is coated with a conductive material.   The jack according to claim 7, wherein the conductive material does not cover an area around the periphery of the first via and the second via.   The jack of claim 5, wherein the conductive material is comprised of copper and finish silver.   The jack of claim 7, wherein the conductive material is comprised of copper and finished silver. Receiving the plug and forming a housing having a port having a plurality of pins respectively connected to corresponding signal lines of the plug;
Forming a shield case surrounding the housing;
Forming a top layer of the substrate, a first shield layer on a first side of the top layer of the substrate, and a second shield layer adjacent to the first shield layer of the substrate;
Forming a bottom layer adjacent to the second shield layer;
Forming a plurality of first vias through the substrate, wherein each first via is configured to receive a pin on the housing;
Forming a plurality of second vias through the substrate, wherein each second via is configured to receive a pin on the housing;
Forming a first set of traces in the top layer of the substrate connecting at least one first via with at least one corresponding second via;
Forming a second set of traces on the opposite side of the top layer of the substrate, connecting at least one first via to at least one second via;
How to manufacture high speed jacks, including:   The method of claim 11, wherein the second set of traces connect vias different from the vias connected at the top surface.   The method of claim 11, comprising forming a first isolation region between the first set of traces on the top surface.   The method of claim 11, comprising forming a second isolation region between the second set of traces on the top surface.   The method according to claim 11, wherein the first shield layer is coated with a conductive material.   16. The method of claim 15, wherein the conductive material does not cover an area around the perimeter of the first via and the second via.   The method according to claim 11, wherein the second shield layer is coated with a conductive material.   18. The method of claim 17, wherein the conductive material does not cover an area around the perimeter of the first via and the second via.   16. The method of claim 15, wherein the conductive material is comprised of copper and finish silver. 18. The method of claim 17, wherein the conductive material is comprised of copper and finish silver.

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