IL262491A - High speed communication jack - Google Patents
High speed communication jackInfo
- Publication number
- IL262491A IL262491A IL262491A IL26249118A IL262491A IL 262491 A IL262491 A IL 262491A IL 262491 A IL262491 A IL 262491A IL 26249118 A IL26249118 A IL 26249118A IL 262491 A IL262491 A IL 262491A
- Authority
- IL
- Israel
- Prior art keywords
- layer
- jack
- substrate
- vias
- traces
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
- H01R13/6464—Means for preventing cross-talk by adding capacitive elements
- H01R13/6466—Means for preventing cross-talk by adding capacitive elements on substrates, e.g. printed circuit boards [PCB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6473—Impedance matching
- H01R13/6474—Impedance matching by variation of conductive properties, e.g. by dimension variations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding
- H01R13/658—High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse]
- H01R13/6581—Shield structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/66—Structural association with built-in electrical component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/66—Structural association with built-in electrical component
- H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
- H01R13/6658—Structural association with built-in electrical component with built-in electronic circuit on printed circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
- H01R24/60—Contacts spaced along planar side wall transverse to longitudinal axis of engagement
- H01R24/62—Sliding engagements with one side only, e.g. modular jack coupling devices
- H01R24/64—Sliding engagements with one side only, e.g. modular jack coupling devices for high frequency, e.g. RJ 45
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0277—Bendability or stretchability details
- H05K1/028—Bending or folding regions of flexible printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R2107/00—Four or more poles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/05—Flexible printed circuits [FPCs]
- H05K2201/056—Folded around rigid support or component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09336—Signal conductors in same plane as power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10295—Metallic connector elements partly mounted in a hole of the PCB
- H05K2201/10303—Pin-in-hole mounted pins
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Description
HIGH SPEED COMMUNICATION JACK
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present disclosure is a PCT of U.S. Patent Application No. 15/146,019, filed on
May 4, 2016, now U.S. Patent No. 9,627,816, which is a continuation-in-part of and claims
priority to U.S. Patent App. No. 14/504,088, filed on October 1, 2014, now U.S. Patent No.
9,337,592, which is a continuation-in-part and claims priority to U.S. Patent Application No.
13/739,214, filed on January 11, 2011, now U.S. Patent No. 8,858,266, which claims the benefit
of and priority to U.S. Provisional Patent Application No. 61/598,288 filed on February 13,
2012, all of which are incorporated by reference herein in their entirety.
FIELD OF THE DISCLOSURE
[0002] The present disclosure relates to a network connection jack used to connect a network
cable to a device.
BACKGROUND OF THE DISCLOSURE
[0003] As electrical communication devices and their associated applications become more
sophisticated and powerful, their ability to gather and share information with other devices also
becomes more important. The proliferation of these intelligent, inter networked devices has
resulted in a need for increasing data throughput capacity on the networks to which they are
connected to provide the improved data rates necessary to satisfy this demand. As a result,
existing communication protocol standards are constantly improved or new ones created. Nearly
all of these standards require or significantly benefit, directly or indirectly, from the
communication of high-definition signals over wired networks. Transmission of these high
definition signals, which may have more bandwidth and, commensurately, higher frequency
requirements, need to be supported in a consistent fashion. However, even as more recent
1WO 2017/192800
versions of various standards provide for theoretically higher data rates or speeds, they are still
speed limited by the current designs of certain physical components. Unfortunately, the design
of such physical components is plagued by a lack of understanding of what is necessary to
achieve consistent signal quality at multi-gigahertz and higher frequencies.
[0004] For example, communication jacks are used in communication devices and equipment
for the connection or coupling of cables that are used to transmit and receive the electrical signals
that represent the data being communicated. A registered jack (RJ) is a standardized physical
interface for connecting telecommunications and data equipment. The RJ standardized physical
interface includes both jack construction and wiring pattern. A commonly used RJ standardized
physical interface for data equipment is the RJ45 physical network interface, also referred to as
an RJ45 jack. The RJ45 jack is widely used for local area networks such as those implementing
the Institute of Electrical and Electronic Engineers (IEEE) 802.3 Ethernet protocol. The RJ45
jack is described in various standards, including one that is promulgated by the American
National Standards Institute (ANSI)/Telecommunications Industry' Association (TIA) in
ANSI/TIA-1096-A.
!0005] All electrical interface components, such as cables and jacks, including the RJ45 jack,
not only resist the initial flow׳ of electrical current, but also oppose any change to it. This property
is referred to as reactance. Two relevant types of reactance are inductive reactance and
capacitive reactance. Inductive reactance may be created, for example, based on a movement of
current through a cable that resists, which causes a magnetic field that induces a voltage in the
cable. Capacitive reactance, on the other hand, is created by an electrostatic charge that appears
when electrons from two opposing surfaces are placed close together.WO 2017/192800 PCT/US2017/030968
[0006ן To reduce or avoid any degradation of transmitted signals, the various components of
a communications circuit preferably have matching impedances. If not, a load with one
impedance value will reflect or echo part of a signal being carried by a cable with a different
impedance level, causing signal failures. For this reason, data communication equipment
designers and manufacturers, such as cable vendors, design and test their cables to verify that
impedance values, as well as resistance and capacitance levels, of the cables comply with certain
performance parameters. The RJ45 jack is also a significant component in nearly every
communications circuit, however, jack manufacturers have not provided the same level of
attention to its performance. Thus, although problems related to existing RJ45 jacks are well
documented in tests and their negative impact on high frequency signal lines is understood, the
industry seems reluctant to address the issues for this important component of the physical layer.
Consequently, there is a need for an improved high speed communications jack.
BRIEF SUMMARY OF THE DISCLOSURE
[0007] One embodiment of the present invention includes a high speed communication jack
including a housing including a port for accepting a plug, the port including a plurality of pins
each connected to a corresponding signal line in the plug, a shielding case surrounding the
housing, a circuit board in the housing havinga substrate, a plurality of first vias extending
through the substrate with each first via being configured to accommodate a pin on the housing,
a plurality of second vias extending through the substrate with each second via being configured
to accommodate a pin on the housing, a first set of traces on a top layer of the substrate that
connects at least one first via with at least one corresponding second via, a first shielding layer
on a first side of the top layer in the substrate, a second shielding layer adjacent the firstWO 2017/192800 PCT/US2017/030968
shielding layer in the substrate and a second set of traces on a side of the substrate opposite the
top layer that connects at least one first via with at least one second via.
[0008] In another embodiment, the second set of traces connect different vias that the vias
connected on the top surface.
[0009] In another embodiment, the jack includes a first isolation region on the top surface
between the first set of traces.
[0010[ In another embodiment, the jack includes a second isolation region on the top surface
between a second set of traces.
[0011[ In another embodiment, the first shielding layer is covered in a conductive material.
[0012[ In another embodiment, the conductive material does not cover an area around the
periphery of the first vias and second vias.
[0013] In another embodiment, the second shielding layer is covered in a conductive
material.
[0014[ In another embodiment, the conductive material does not cover an area around the
periphery׳ of the first vias and second vias.
[0015[ In another embodiment, the conductive material is comprised of copper and finished
silver.
[0016[ In another embodiment, the conductive material is comprised of copper and finished
silver,
[00171 Another embodiment of the present invention includes a method of manufacturing a
high speed jack, the method including the steps of forming a housing including a port for
accepting a plug, the port including a plurality of pins each connected to a corresponding signal
line in the plug, forming a shielding case surrounding the housing, forming a top !aver of aWO 2017/192800 PCT/US2017/030968
substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding
layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the
second shielding layer, forming a plurality of first vias extending through the substrate with each
first via being configured to accommodate a pin on the housing, forming a plurality of second
vias extending through the substrate with each second via being configured to accommodate a
pin on the housing, forming a first set of traces on a top layer of the substrate that connects at
least one first via with at least one corresponding second via, forming a second set of traces on a
side of the substrate opposite the top layer that connects at least one first via with at least one
second via.
[0018] In another embodiment, the second set of traces connect different vias that the vias
connected on the top surface.
[0019] In another embodiment, the method includes the step of forming a first isolation
region on the top surface between the first set of traces.
[0020] In another embodiment, the method includes the step of forming a second isolation
region on the top surface between a second set of traces.
[0021] In another embodiment, the first shielding layer is covered in a conductive material.
[0022] In another embodiment, the conductive material does not cover an area around the
periphery of the first vias and second vias.
[0023] In another embodiment, the second shielding layer is covered in a conductive
material.
[0024] In another embodiment, the conductive materia! does not cover an area around the
periphery of the first vias and second vias.
5WO 2017/192800 PCT/US2017/030968
[0025] In another embodiment, the conductive material is comprised of copper and finished
silver.
[0026] In another embodiment, the conductive material is comprised of copper and finished
silver.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027! FIG. 1 illustrates a high speed communications jack configured in accordance with
one embodiment of the various aspects of the present disclosure that includes an RJ45 jack,
[0028] FIG. 2 illustrates a bottom perspective portion of a left side portion of the RJ45 jack
of FIG. 1,
[0029[ FIG. 3 illustrates a bottom and right side view of a jack shield for providing shielding
for the RJ45 jack and the flexible printed circuit board of FIG. 1,
[0030[ FIG. 4A illustrates a schematic representation of a top view of the front surface of the
printed circuit board of FIG. I,
10031J FIG. 4B illustrates another embodiment of a schematic representation of a top view of
the front surface of the printed circuit board of FIG. 1
[0032] FIG. 5 A illustrates a schematic representation of a top view of the back surface of the
printed circuit board of FIG. 4,
[0033[ FIG. 5B illustrates another embodiment of a schematic representation of a top view of
the back surface of the printed circuit board of FIG. 4
[0034] FIG. 6A illustrates a cross sectional view of the substrate of the printed circuit board
of FIG. 4 along line BB,
[0035[ FIG. 6B illustrates a cross sectional view of a via in the printed circuit board of FIG.
4,
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[0036] FIG. 6C illustrates a cross sectional view of another example of a via in the printed
circuit board of FIG. 4.
[0037] FIG. 7 illustrates a schematic representation an RJ45 jack having transmit and
receiving cable pairs matched and balanced to one another,
[0038[ FIG. 8 illustrates a schematic representation of a differentially balanced pair of signal
lines,
[0039] FIG. 9 illustrates a schematic representation of the process used to differentially
balance two traces in FIG. 4 based on a first signal and a second signal,
[0040] FIG. 10A illustrates a rear perspective view of the RJ45 jack of FIG. 1 with the shield
removed:
[00411 FIG. 10B illustrates a rear perspective view of another embodiment of the RJ45 jack
of FIG. 1 with the shield removed;
[0042] FIG. II depicts one embodiment of a high speed communication jack including a
rigid substrate;
[0043] FIG. 12 depicts a schematic representation of the layers in a rigid high speed
communication jack;
|0044] FIG. 13A depicts a side view of the high speed communication jack;
[0045[ FIG. 13B depicts a top view of the rigid substrate;
10046] FIG. 14A depicts a ground layer of the substrate;
[0047[ FIG. 14B depicts a second ground layer of the substrate
]0048] FIG. 14C depicts a bottom layer of the substrate;
|0049] FIG. 14D depicts a fourth layer of the rigid substrate;
7WO 2017/192800 PCT/US2017/030968
[0050] FIG. 15A shows the insertion loss of a differential mode version of the jack during
normal operation;
[0051] FIGS. 15B depicts a graphical representation of near field cross talk for the jack in
normal operation;
[0052] FIGS. 15C depicts a graphical representation of near field cross talk for the jack in
normal operation;
[0053] FIG. 15D depicts the return loss for the jack during normal operation;
[0054] FIG. 15E depicts a graphical representation of far end cross talk for the jack during
normal operation; and
[0055] FIG. 15F depicts another graphical representation of far end cross talk for the jack
during normal operation.
DETAILED DESCRIPTION OF THE DISCLOSURE
[0056] FIG. I illustrates a high speed communications jack configured in accordance with
one embodiment of the various aspects of the present disclosure that includes an RJ45 jack 110, a
flexible printed circuit board (PCB) 120, and a jack shield 130. As described herein, in
accordance with various aspects of this disclosure, the flexible PCB 120 provides a balanced,
radio frequency tuned circuit that may be directly soldered onto each pin of the RJ45 jack 110,
while the jack shield 130 provides shielding for the RJ45 jack 110 and the flexible PCB 120, as
well as functioning as a chassis ground. In combination, the RJ45 jack 110, the flexible PCB
120, and the jack shield 130 may provide functionality similar to a tuned waveguide and a tube
through which communication signals may be transmitted, where an energy portion of the
communication signal travels outside the tube through jack shield 130; and an information
portion of the communication signal travels within the tube along the non-resistive gold wire;
8WO 2017/192800
PCT/U S2017/030968
thereby allowing for high speed data signal speeds to be obtained. For example, it is envisioned
that data speeds of 40 gigabits (Gbs) and beyond may be supported.
!0057] Although an RJ 45 communication jack is used below, the present communication
jack is not limited to RJ 45 communication jacks and may be used in any type of high speed
communication jack including, all class of modular RJ type connectors, Universal Serial Bus
(USB) connectors and jacks, Firewire (1394) connectors and jacks, HDMI (High-Definition
Multimedia Interface) connectors and jacks, D-subminiature type connectors and jacks, ribbon
type connectors or jacks, or any other connector or jack receiving a high speed communication
signal.
[0058] In various aspects of this disclosure, the various pins and traces disclosed herein may
be composed of any suitable conductive elements such as gold, silver, or copper, or alloys and
combinations of any suitable conductive elements. For example, the set of pins and plug
contacts of the RJ45 jack 110 may include gold-plated copper pins or wires, while the set of
traces of the flexible PCB 120 may include gold-plated copper paths. The gold plating is used to
provide a corrosion-resistant electrically conductive layer on copper, which is normally a
material that oxidizes easily. Alternatively, a layer of a suitable barrier metal, such as nickel,
may be deposited on the copper substrate before the gold plating is applied. The layer of nickel
may improve the wear resistance of the gold plating by providing mechanical backing for the
gold layer. The layer of nickel may also reduce the impact of pores that may be present in the
gold layer. At higher frequencies, gold plating may not only reduce signal loss, but may also
increase the bandwidth from the skin effect where current density is highest on the outside edges
of a conductor. In contrast, use of nickel alone will result in signal degradation at higher
frequencies due to the same effect. Thus, higher speeds may not be achieved in RJ45 jacks that
9WO 2017/192800
use nickel plating alone. For example, a pin or trace plated only in nickel may have its useful
signal length shortened as much as three times once signals enter the GHz range although some
benefits of using gold plating over the copper path has been described herein, other conductive
elements may be used to plate the copper paths. For example, platinum, which is also non-
reactive but a good conductor, may be used instead of gold to plate the copper paths.
[0059] Each of the major components of the high speed communications jack, namely the
RJ45 jack 110, the flexible printed circuit board (PCB) 120, and the jack shield 130 will be
described briefly herein before a discussion of how these components interoperate to achieve
support for high speed communications is provided.
[0060[ FIG. 2 illustrates a bottom perspective view of a front portion of the RJ45 jack 1 10 of
FIG. 1, where it may be seen that a plug opening 230 is provided for inserting a plug (not
shown). The plug opening 230 may be configured to receive the plug to couple contacts on the
plug to a set of plug contacts 212 in the RJ45 jack 110. The plug may be an RJ45 8 Position 8
Contact (8P8C) modular plug. The set of plug contacts 212 are formed into a set of pins 210
configured to be attached to a communication circuit on a circuit board. For example, the RJ45
jack 110 may be mounted to a circuit board of a network switch device through the use of a pair
of posts 220, and then the set of pins 210 may be soldered onto respective contact pads on the
circuit board of the device. By itself, ajack similar to the RJ45 jack 110 as illustrated in FIG. 2
provides basic connectivity between a plug of an RJ45 cable and the circuit board of a device
into which the jack is integrated. However, that jack is not designed to handle communication
frequencies needed for high speed communications. The RJ45 jack 110, as configured in
accordance with various aspects of the disclosed approach as described herein, may be integrated
10WO 2017/192800 PCT/US2017/030968
with other components such as the jack shielding 130 and the flexible PCB 120 so that it may be
used to communicate at higher speeds without interference from transient signals.
[0061] FIG. 3 illustrates a bottom and right side view of a jack shield for providing shielding
for the RJ45 jack 110 and the flexible PCB 120. The jack shield 130 includes a top portion 302,
a bottom portion 304, a back portion 306, a front portion 308, a left side portion (not shown but
substantially identical to the right side portion) and a right side portion 310. In order to provide
desired shielding properties, in one embodiment of the present disclosure the jack shield 130
may include a conductive material such as, but not limited to, steel, copper, or any other
conductive material. A pair of tabs 320 on both the right side 3 10 and the left side (not shown)
of the jack shield 130, near the bottom portion 304, may be used to ground and secure the jack
shield 130 to a circuit board within a device (not shown). For example, the pair of tabs 320 on
the jack shield 130 may be inserted into a pair of matched mounting holes on the circuit board,
and soldered thereon.
[0062[ FIG. 4A illustrates a schematic representation of a top view of the front surface of the
PCB 120 of the RJ45 jack. The PCB 120 includes a multi-layer substrate 402 made of a
dielectric material incorporating strip-line flex or equivalent technology. The edge of the
substrate 402 is surrounded by a protective layer 404. The protective layer 404 is made of a non-
conducting material such as, but not limited to, plastic or a flexible solder mask. The front
surface of the substrate 402 includes a plurality of vias 406, 408, 410, 412, 414, 416, 418 and
420 made through the substrate 402. Each via 406, 408, 410, 412, 414, 416, 418 and 420 passes
through the substrate 402 and is sized to accommodate a pin 2 10. The area surrounding each via
406, 408, 410, 412, 414, 416, 418 and 420 is coated w׳ith a conductive material, such as gold.
The coating surrounding each via 406, 408, 410, 412, 414, 416, 418 and 420 may beWO 2017/192800
substantially square shaped or substantially rectangular shaped. In another embodiment,
depicted in FIG. 4B, the coating surrounding each via 406, 408, 410, 412, 414, 416, 418 and 420
may be substantially circular shaped. By making the coating circular shaped, the interference
between adjacent vias 406, 408, 410, 412, 414, 416, 418 and 420 is reduced.
[0063] A plurality of traces 422, 424, 426, 428, 430, 432, 434 and 436 extend from each via
406, 408, 410, 412, 414, 416, 418 and 420 towards an end of the PCB 120. Each trace 422, 424,
426, 428, 430, 432, 434 and 436 is made from a conductive material including copper or gold.
In one embodiment, a nickel layer is formed on the substrate 402 and a gold layer is formed on
the nickel layer to form each trace 422, 424, 426, 428, 430, 432, 434 and 436. Each trace 422,
424, 426, 428, 430, 432, 434 and 436 extends towards a back end of the PCB 120 until the trace
422, 424, 426, 428, 430, 432, 434 or 436 reaches a shielding trace layer 490 near an edge of the
PCB 120 opposite the vias 406, 408, 410, 412, 414, 416, 418 and 420. Each trace 422, 424, 426,
428, 430, 432, 434 and 436 includes a first portion 454, 456, 458, 460, 462, 464, 466 and 468
adjacent to a second portion 470, 472, 474, 476, 478, 480, 482 and 484 with each second portion
470, 472, 474, 476, 478, 480, 482 and 484 extending to the shielding trace layer 490 without
contacting the shielding trace layer 490. Each first portion 454, 456, 458, 460, 462, 464, 466 and
468 tapers from the respective second portion 470, 472, 474, 476, 478, 480, 482 and 484 towards
a respective via 406, 408, 410, 412, 414, 416, 418 or 420. Each second portion 470, 472, 474,
476, 478, 480, 482 and 484 has a length that varies depending on the trace 422, 424, 426, 428,
430, 432, 434 01־436.
[0064[ Two shielding tabs 486 and 488 are positioned on opposite edges of the PCB 120.
Each shielding tab 486 and 488 is made of a substrate covered in a conductive material for
example, gold or copper. The shielding tabs 486 and 488 are electrically connected by the shield
12WO 2017/192800 PCT/US2017/030968
trace layer 490 on the substrate 402 that extends between the shielding tabs 486 and 488 and is
positioned between the second portions 470, 472, 474, 476, 478, 480, 482 and 484 of each trace
422, 424, 426, 428, 430, 432, 434 and 436 and the edge of the PCB 120 opposite the vias 406,
408, 410, 412, 414, 416, 418 and 420.
|0065] FIG. 5A illustrates a schematic representation of a top view of the back surface of the
printed circuit board of FIG. 4A. The back surface includes the vias 406, 408, 410, 412, 414,
416, 418 and 420, the shielding tabs 486 and 488, and a shielding trace layer 502 extending
between the back surfaces of each shielding tab 486 and 488. The shielding trace layer 502
covers the portion of the back surface of the PCB 120 between the shielding tabs 486 and 488.
The shielding tabs 486 and 488 include return vias 504, 506, 508, 510, 512, 514, 516 and 518
which pass through the substrate 402 connecting the shielding trace layer 490 and the shielding
trace layer 502. FIG. 5B depicts another embodiment of a. top view of the back surface of the
printed circuit board of FIG. 4B.
[0066] FIG. 6A illustrates a cross-section view of the multi-layer substrate 402 in the PCB
120 along line BB of FIG. 4. A first layer 602 of the multi-layer substrate 402 includes a solder
mask portion, made from a material such as PSR9000FST Flexible Solder Mask. A second layer
604 is formed under the top layer and includes each of the traces 422, 424, 426, 428, 430, 432,
434 and 436. Each trace 422, 424, 426, 428, 430, 432, 434 and 436 has a length (L), a height (II)
and a width (W), and is separated from an adjacent trace by a distance (S). The length (L) of
each trace is the length the trace extends along the surface of the flexible circuit board 120 from
the edge of its respective via 406, 408, 410, 412, 414, 416, 418 and 420 to shielding trace layer
490.WO 2017/192800 PCT/US2017/030968
[0067] Each trace 422, 424, 426, 428, 430, 432, 434 and 436 extends through the first layer
602 such that each trace 422, 424, 426, 428, 430, 432, 434 and 436 is not covered by the flexible
solder mask. Shield trace layer 490 is also formed over a portion of the second layer 604 with
the shield trace layer 490 extending through the first layer 602. A third dielectric layer 606 is
formed below the second layer 604 The third layer 606 has a depth (D) of between
approximately 0.002 mils to approximately 0.005 mils, and is made from a material having a
dielectric constant greater than 3.0 such as, but not limited to RO XT8100, Rogerson Material, or
any other material capable of isolating a high frequency electrical signal.
[0068] A fourth layer 608 is formed below the third layer 606 with the fourth layer 608
including a signal return portion and a shield trace portion 502. Both the signal return portion
and the shield trace portion 502 are made of a conductive material, preferably gold or copper. A
fifth layer 610 is formed on the forth layer 608 with the fifth layer 610 having a flexible solder
mask portion and a shielding trace layer 502 portion. The flexible solder mask portion is
manufactured of the same material as the flexible solder mask portion of the first layer 602. In
an alternate example, the flexible solder mask portion is made from a different material than the
flexible solder mask in the first layer 602. In an alternate example, a second signal return layer
(not shown) may be positioned in the dielectric material.
[0069] To eliminate crosstalk caused by adjacent traces, each trace 422, 424, 426, 428, 430,
432, 434 and 436 is electrically coupled to an adjacent trace 422, 424, 426, 428, 430, 432, 434
and 436. As an illustrative example, trace 422 may be coupled to trace 424. During operation, a
first signal is transmitted down a first trace and an identical signal having an opposite polarity is
transmitted down the matched trace thereby differentially coupling the traces together. Because
the traces are differentially coupled together, the impedance of each trace determines how the
14WO 2017/192800 PCT/US2017/030968
trace is driven. Accordingly, the impedance of each set of matched trace should be substantially
equal.
[0070] The physical characteristics of each trace 422, 424, 426, 428, 430, 432, 434 and 436
in a matched set of traces are adjusted to balance the impedance between the matched traces for
the transmission and return signals transmitted over each trace. The impedance of each trace
422, 424, 426, 428, 430, 432, 434 and 436 is adjusted by adjusting any one or a combination of
the length (L), width (W), height (H) of each trace and the spacing (S) between the matched
traces for each signal transmitted through each trace 422, 424, 426, 428, 430, 432, 434 and 436.
The height (H) of each trace 422, 424, 426, 428, 430, 432, 434 and 436 may be between
approximately 2 mils and approximately 6 mils, and the spacing (S) between adjacent traces 422,
424, 426, 428, 430, 432, 434 and 436 may be between approximately 3 mils and approximately
mils.
[0071] Returning to FIG. 4, each trace has a variable width in the first portion 454, 456, 458,
460, 462, 464, 466 and 468 and a substantially constant width in the second portion 470, 472,
474, 476, 478, 480 and 482. Accordingly, the width of each trace 422, 424, 426, 428, 430, 432,
434 and 436 is adjusted in either the first portion 454, 456, 458, 460, 462, 464, 466 and 468 or
the second portion 470, 472, 474, 476, 478, 480 and 482, or in both the first portion 454, 456,
458, 460, 462, 464, 466 and 468 and the second portion to 470, 472, 474, 476, 478, 480 and 482
along with the height H of the trace 422, 424, 426, 428, 430, 432, 434 and 436, such that each
trace in a matched set has substantially the same impedance when the matched traces are
separated by a distance S.
[0072[ Due to inconsistencies in manufacturing and materials, the signal driven through each
set of differentially matched traces 422, 424, 426, 428, 430, 432, 434 and 436 may not be
15WO 2017/192800
identical, which causes a portion of the signal to reflect back causing common mode
interference. To eliminate any common mode interference, each trace 422, 424, 426, 428, 430,
432, 434 or 436 in a matched set of traces includes a common mode filter that is tuned to
eliminate any common mode interference in the matched set. Each filter is comprised of a
capacitor formed by the via 406, 408, 410, 412, 414, 416, 418 or 420 of each trace 422, 424, 426,
428, 430, 432, 434 or 436 and the fourth layer 608 of the multi-layer substrate 402. Each via
406, 408, 410, 412, 414, 416, 418 and 420 includes a layer of conductive material, such as gold
or copper, formed around the periphery the via 406, 408, 410, 412, 414, 416, 418 and 420 on the
second layer 604 and fourth layer 608 of the substrate 402. The conductive material on the first
layer 602 is connected to the trace 422, 424, 426, 428, 430, 432, 434 or 436 associated with the
via 406, 408, 410, 412, 414, 416, 418 and 420 and the conductive material on the fourth layer
608 is connected to the signal return portion of the fourth layer 608. The size of each capacitor is
determined by the distance between the conductive material on the second layer 604 and the
fourth layer 608. Accordingly, adjusting the depth of the third layer 606 in relation to the
conductive material on the vias 406, 408, 410, 412, 414, 416, 418 and 420, allows for the
capacitive effect of each via 406, 408, 410, 412, 414, 416, 418 and 420 to be adjusted. The
capacitors created by the via 406, 408, 410, 412, 414, 416, 418 and 420 and return portion of the
fourth layer 608 are sized between approximately 0.1 picofarads (pf) to approximately 0.5pf.
The top and bottom surfaces of the substrate 402 may be covered in a plastic insulating layer to
further enhance the operation of the circuit.
[0073! The combination of the capacitor created in each via 406, 408, 410, 412, 414, 416,
418 and 420 and the characteristic inductance of the signal return layer creates a common mode
filter for each trace 422, 424, 426, 428, 430, 432, 434 or 436. By adjusting the capacitive value
16WO 2017/192800 PCT/US2017/030968
of each capacitor based on the impedance of the trace 422, 424, 426, 428, 430, 432, 434 and 436,
common mode noise is greater reduced, thereby improving the signal throughput on each trace
422, 424, 426, 428, 430, 432, 434 and 436.
[0074] FIG. 6B illustrates a schematic representation of a cross sectional view of a via 406,
408, 410, 412, 414, 416, 418 or 420. Each via 406, 408, 410, 412, 414, 416, 418 and 420 is
formed through the first layer 602, second layer, 604, third layer 606, fourth layer 608 and fifth
layer 610. The second layer 604 is made of a conductive material, such as gold or copper and
surrounds the circumference of each via 406, 408, 410, 412, 414, 416, 418 and 420. The second
layer 604 also connects each via 406, 408, 410, 412, 414, 416, 418 and 420 to its respective trace
422, 424, 426, 428, 430, 432, 434 or 436. The third layer 606 acts as a dielectric layer as
described in FIG. 6A. The fourth layer 608 is formed in the third layer 606 and acts as a signal
return layer. The fifth layer 610 is also made from a conductive material such as copper or gold,
and also surrounds the circumference of the via in the same manner as the second layer 602. A
sealing layer (not shown) may also be formed over the fifth layer 610.
[0075] The fourth layer 608 is separated from the second layer 604 by a distance D1 and
from the fifth layer 610 by a second distance D2. The combination of the second layer 604, third
dielectric layer 606, and the fourth return signal layer 608 creates a capacitor having a capacitive
value of between approximately 0.1 pf and 0.5pf. By adjusting the distance D1 of the fourth
layer 608 from the second layer 604, the capacitive value of the via capacitor is adjusted.
Because the via connects its associated trace with the fourth return signal layer 608, the
combination of second layer 604, the third dielectric layer 606, and the fourth return signal layer
608 forms a common mode filter that removes any interference caused by signal reflection
resulting from imperfections in the manufacturing process. By adjusting the capacitive value of
17WO 2017/192800 PCT/US2017/030968
the via capacitor the common mode filter may be tuned to eliminate substantially all signal noise
caused by reflection of the transmission or return signal.
[0076! FIG. 6C illustrates another example of cross sectional view of a via 406, 408, 410,
412, 414, 416, 418 and 420. A second return signal layer 612 is added to the third layer 606
between the first return signal layer 608 and the fifth layer 610. The second return signal layer
612 runs parallel to the first signal layer 608 and enhances the filtering effect of the common
mode filter. By adjusting a distance D3 between the first return signal layer 608 and the second
return signal layer 612, a second capacitor formed by the first return signal layer 608, third layer
606 and second return signal layer 612 is created in the via. By adjusting the distance D3, the
value of the second via capacitor may be adjusted to enhance the operation of the common mode
filter. Further, as the inventors have learned, forming a second capacitor in the via allows for
matching of traces on separate ends of the PCB 102. As an illustrative example, trace 422 may
be matched with trace 436. Accordingly, by forming the second capacitor, pairs of signal lines
positioned in accordance with the RJ 45 standard can be achieved.
[0077] FIG. 7 illustrates a schematic representation an RJ 45 jack having matched transmit
and receive traces. By adjusting the height H, width W, and length L of each trace 422, 424, 426,
428, 430, 432, 434 or 436 transmit and a receive lines can be impedance matched. To enhance
the operation of the jack, identical high frequency signals having opposite polarities are
transmitted down each pair. Because the matched traces are coupled via the shield, the pairs act
as common mode filters for each other. Also, if one signal cannot be delivered, the
corresponding opposite signal line will deliver the identical signal. Because the matched traces
act as filters coupled to the shield, noise caused by high bandwidth transmission are filtered out
from the signal. Further, because the transmit line is matched with the receive line, filtering of
18WO 2017/192800
the signal is performed with greater accuracy because the reference point for the filters is the
signal itself, opposed to being a ground connection.
[0078] FIG. 8 illustrates a schematic representation of a differentially balanced pair of signal
lines. As the figure depicts, the characteristics of each trace is adjusted such that the impedance
of a first trace is matched to the impedance of the second trace using the methods previously
discussed. Further, the capacitors formed in each via form a common mode filter with a return
signal line embedded in the PCB 120. By differentially balancing two traces during transmission
of both the transmission and response signals, a fully balanced two way communication circuit is
achieved.
[0079] FIG. 9 illustrates a schematic representation of a method of balancing matched traces
for a transmission and return signal. In step 902, physical characteristics of each trace in a
matched pair of traces are adjusted such that the impedance of the traces are substantially equal.
The physical characteristics may include the height, length and width of each trace and the
distance separating each trace in the matched set of traces. In step 904, a first signal having a
first polarity is transmitted down the first trace in the match set traces. The first signal may be a
high frequency communication signal operating at a frequency greater then 10 gigahertz
(“GHz”). In step 906, a second signal substantially identical to the first signal and having a
polarity opposite to the polarity of the first signal is transmitted on the second trace of the match
set of traces simultaneously with the first signal. In step 908, the first signal is measured at the
generation and termination end of the trace, and the two measurements are compared to
determine the amount of data lost along the length of the trace. In step 910, at least one physical
characteristic of the first trace or second trace is adjusted based on the amount of signal loss
19WO 2017/102800
measured. The process may return to step 904 until the amount of signal loss is less than
approximately 10 decibels (“db”).
[0080] In step 912, a third signal is transmitted on the second trace of the matched set of
traces. In step 914, a fourth signal substantially identical to the third signal but having a polarity
opposite the polarity of the third signal is transmitted on the first trace. In step 916, the third
signal is measured at the generation and termination end of the trace, and the two measurements
are compared to determine the amount of data lost along the length of the trace. In step 918, at
least one physical characteristic of the first trace or second trace is adjusted based on the amount
of signal loss measured. The process may return to step 912 until the amount of signal loss is less
than approximately 10 decibels (“db”). In another example, the process may return to step 904
to confirm the signal loss of the first signal is not affected by the adjustments made in response
to the third signal loss.
[0081] FIG. 10 illustrates the PCB 120 positioned in the jack 110. The substrate 402 of the
PCB 120 is made from a flexible material that allows a first portion of the PCB 120 to be
oriented to a second portion of the PCB 120 by approximately a 90 degree angle. Accordingly,
the PCB 120 is bent such that the vias 406, 408, 410, 412, 414, 416, 418 and 420 are positioned
over the pins 210 in the jack, and the traces 422, 424, 426, 428, 430, 432, 434 and 436 extend
from the vias 406, 408, 410, 412, 414, 416, 418 and 420 to the contact pads for the jack. The
shielding tabs 486 and 488 are bent such that they are at approximately a 90 degree angle from
the PCB 120. The shielding tabs 486 and 488 are positioned along the side of the jack such that
the jack shield 130 of the jack engages the shielding tabs 486 and 488.
[0082] The flexible PCB 120 may be implemented using any flexible plastic substrates that
enable the flexible PCB 120 to bend. As described herein, the flexible PCB 120 may flex or
20WO 2017/192800
bend to conform to the existing form factor of the RJ45 jack 110 and be shielded by the jack
shielding 130. For example, the flexible PCB 120 may be attached to the RJ45 jack 110, placed
between the RJ45 jack 110 and the jack shield 130. The flexible PCB 120 shielding tabs 486 and
488 may be attached to the jack shield 130 to provide a common connection to the flex circuit on
the flexible PCB 120. The set of pins 210 of the RJ45 jack 110 may then be electrically coupled
to a circuit board of a device in which the RJ45 jack 110 is used.
[0083] The flexible PCB 120 may be configured to fold and conform to the shape of the
RJ45 jack 110 for better fit into an existing enclosure such as the jack shield 130. For example,
in one aspect of the disclosed approach, the flexible PCB 120 bends at an approximately 90
degree angle towards a middle section of the flexible PCB 120, to fold into the jack shield 130.
The shielding tabs 486 and 488 of the flexible PCB 120 are folded onto and contacting the jack
shield 130, may be soldered to secure the flexible PCB 120 to the jack shield 130. Those skilled
in the art will recognize that the orientation of the flexible PCB 120 with respect to the RJ45 jack
110 within the jack shield 130 may vary in accordance with various aspects of the disclosure.
For example, the flexible PCB 120 may be sufficiently thin to flex and fold into other sides of
the jack shield 130. The flexible PCB 120 may be shaped to lie entirely along the bottom section
304 of the jack shield 130 without needing to flex or bend into the jack shield 130.
[0084] The preceding detailed description is merely some examples and embodiments of the
present disclosure and that numerous changes to the disclose embodiments can be made in
accordance with the disclosure herein without departing from its spirit or scope. The preceding
description, therefore, is not meant to limit the scope of the disclosure but to provide sufficient
disclosure to one of ordinary skill in the art to practice the invention with undue burden.
21WO 2017/192800 PCT/US2017/030968
[0085] FIG. 11 depicts one embodiment of a high speed communication jack including a
rigid substrate. The high speed communication jack 1100 includes a jack housing 1102 that is
configured to accept a communication plug (not shown). A substrate 1300 is positioned on the
lower surface of the housing such that pins 1306 extend from the substrate 1300 for engagement
with a circuit board which the jack mounts onto when installed.
[0086[ FIG. 12 depicts a schematic representation of the layers in a rigid high speed
communication jack. The substrate 1300 includes a top layer 1202 including a plurality of vias
(not shown) that are each sized to accommodate a pin, a second layer 1204 including a plurality
of impedance match traces as discussed above, and a third layer 1206 and fourth layer 1208
including vias that are concentrically aligned with the vias in the first layer 1202. The first layer
1202 is separated from the second layer 1204 by a first intermediate layer 1210 made of a non
conducting material such as, but not limited to, Rogers material. The second layer 1204 is
separated from the third layer 1206 by a second intermediate layer 1212, and the third layer 1206
and fourth layer 1208 are separated by a third intermediate layer 1214. A top soldermask layer
1216 is formed on the side of first layer 1202 opposite the first intermediate layer 1210. In one
embodiment, the first layer 1202, second layer 1204, third layer 1206 and fourth layer 1208 are
comprised of Vi oz Copper and Vi oz finished silver. In one embodiment, the first intermediate
layer 1210, second intermediate layer 1212 and third intermediate layer 1214 are made of Rogers
R04003 material. In another embodiment, the first layer 1202 is adhered to the first intermediate
layer 1210 by an adhesive, the second and third layers 1204 and 1206 are adhered to the second
intermediate layer 1212 by an adhesive and the third layer 1206 and fourth layer 1208 are
adhered to the third intermediate layer 1214 by an adhesive.WO 2017/192800 PCT/US2017/030968
[0087] FIG. 13A depicts a side view of the high speed communication jack. The jack
includes a rigid substrate 1300 including a first set of pins 1302 on a lower side of the substrate
1300 and a second set of pins 1304 on an upper side of the substrate 1300. FIG. 13B depicts a
top view of the rigid substrate 1300. The rigid substrate 1300 includes a plurality of first vias
1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 extending through the substrate 1300 that
engage the first set of pins 1302 on the opposite side of the substrate 1300. The first set of pins
1302 are configured to engage vias (not shown) on a circuit board to provide a communicative
connection between the jack and the circuit board. Each of the second set of pins 1304 engage
second vias 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336 located on a side of the
substrate 1300 opposite the first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320. The
second set of pins 1304 are configured to engage corresponding pins in a plug when the plug is
inserted into the jack.
[0088] Trace 1338 is formed on the top surface of the substrate 1300 and connects second via
1326 to first via 1310 and trace 1340 connects second via 1328 to first via 1312. A first isolation
region 1342 is formed between the traces 1338 and 1340 to provide isolation between the two
traces 1338 and 1340. Trace 1344 connects second via 1334 to first via 1318 and trace 1346
connects second via 1336 to first via 1320. Second isolation region 1348 isolates trace 1340
from trace 1344 and third isolation region 1350 isolates trace 1344 from trace 1346. Isolation
plane 1352 extends around the periphery of the substrate 1302 between the second vias 1322,
1324, 1326, 1328, 1330, 1332, 1334 and 1336 and the edge of the substrate and the traces 1338
and 1346 and the edge of the substrate 1302. In one embodiment, the isolation regions and
planes are made of a material that is '4 oz copper and '4׳ oz silver. By providing isolation
between the different traces, the effects of electrical interference between traces is reduced orWO 2017/192800 PCT/US2017/030968
eliminated. In one embodiment, vias are formed in each isolation region to connect the isolation
regions to the lower grounding layers.
[0089] FIG. 14A depicts a ground layer 1400 of the substrate 1300. The ground layer 1400
is positioned adjacent to the top layer 1300. The ground layer 1400 includes grounding plane
1402. The grounding plane 1402 covers the surface of the ground layer 1400 excluding the area
around the periphery of the first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and
second vias 1322, 1324, 1326, 1328, 1330, 1332, 1334 and 1336. The surface of ground layer
1400 is coated in a conductive material to form the grounding plane 1402. In one embodiment,
the material is V4 oz copper and V4 oz silver.
[0090] FTG. 14B depicts a second ground layer 1404 of the substrate 1300. The second
ground layer 1404 is covered with a conductive material that covers substantially the entire
surface of the second ground layer 1404 excluding the area around the first vias 1306, 1308,
1310, 1312, 1314, 1316, 1318 and 1320 and second vias 1322, 1324, 1326, 1328, 1330, 1332,
1334 and 1336. In one embodiment, the material covering the second layer 1404 is A oz copper
and 14 oz silver.
[0091] FIG. 14C depicts a bottom layer 1406 of the substrate 1300. The bottom layer 1406
includes first vias 1306, 1308, 1310, 1312, 1314, 1316, 1318 and 1320 and second vias 1322,
1324, 1326, 1328, 1330, 1332, 1334 and 1336. Trace 1408 connects second via 1322 with first
via 1306 and trace 1410 connects second via 1324 with first via 1308. Isolation region 1412
separates trace 1408 from trace 1410 Second isolation region 1418 separates trace 1410 from
trace 1414 and third isolation region 1420 separates trace 1414 from trace 1416. Isolation plane
1422 extends around the periphery of the bottom layer 1406 between the second vias 1322, 1324,
24WO 2017/1 ‘>2800 PCT/US2017/030968
1326, 1328, 1330, 1332, 1334 and 1336 and the edge of the substrate 1302 and the traces 1408
and 1416 and the edge of the substrate 1302.
[0092| FIGS. 15A-15F depicts a graphical representation of test results for the high speed
communication jack. FIG. 15A shows the insertion loss of a differential mode version of the
jack during normal operation. As the graph shows, at speeds approaching 2000 MHz, the
insertion loss is approximately 1.8 db. FIGS. I5B and 15C depict a graphical representation of
near field cross talk for the jack in normal operation. FIG. 15D depicts the return loss for the jack
during normal operation. The graph also shows the performance requirements for the IEEE
40GBase-T standard. As the graph indicates, at speeds approaching 2000 MFIz, the jack
performs better than the requirements of the IEEE 40GBase-T standard. FIG, 15E depicts a
graphical representation of far end cross talk for the jack during normal operation. The graph
also shows the performance requirement for the IEEE 40GBase-T standard. As the graph
indicates, at speeds approaching 2000 MHz, the jack performs better than the requirements of the
IEEE 40GBase-T standard. FIG. 15F depicts another graphical representation of far end cross
talk for the jack during normal operation.
[0093] As FIGS. 15A-15F demonstrate, by arranging and connecting the traces and ground
planes on the substrate 1300, the jack is capable of transmitting data at a very high speed without
interference. Further, by arranging the layers of the substrate to provide multiple grounding
layers, the isolation of the traces on the substrate is increased further improving the performance
of the jack.
[0094[ In the present disclosure, the words ־־a’: or ־־an" are to be taken to include both the
singular and the plural. Conversely, any reference to plural items shall, where appropriate,
include the singular.WO 2017/192800
[0095] It should be understood that various changes and modifications to the presently
preferred embodiments disclosed herein will be apparent to those skilled in the art. Such
changes and modifications can be made without departing from the spirit and scope of the
present disclosure and without diminishing its intended advantages. It is therefore intended that
such changes and modifications be covered by the appended claims.262491/2
Claims (20)
1. A high speed communication jack including: a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug; a shielding case surrounding the housing; a circuit board in the housing having a substrate, a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing, a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via; a first shielding layer on a first side of the top layer in the substrate; a second shielding layer adjacent the first shielding layer in the substrate; and a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.
2. The jack of claim 1 wherein the second set of traces connect different vias that the vias connected on the top surface.
3. The jack of claim 1 including a first isolation region on the top surface between the first set of traces.
4. The jack of claim 1 including a second isolation region on the top surface between a second set of traces.
5. The jack of claim 1 wherein the first shielding layer is covered in a conductive material.
6. The jack of claim 5 wherein the conductive material does not cover an area 27 262491/2 around the periphery of the first vias and second vias.
7. The jack of claim 5 wherein the conductive material is comprised of copper and finished silver.
8. The jack of claim 1 wherein the second shielding layer is covered in a conductive material.
9. The jack of claim 8 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.
10. The jack of claim 8 wherein the conductive material is comprised of copper and finished silver.
11. A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug; forming a shielding case surrounding the housing; forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate; a second shielding layer adjacent the first shielding layer in the substrate; and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing, forming a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via; forming a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.
12. The method of claim 11, wherein the second set of traces connect different vias that the vias connected on the top surface. 28 262491/2
13. The method of claim 11 including the step of forming a first isolation region on the top surface between the first set of traces.
14. The method of claim 11 including the step of forming a second isolation region on the top surface between a second set of traces.
15. The method of claim 11 wherein the first shielding layer is covered in a conductive material.
16. The method of claim 15 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.
17. The method of claim 15 wherein the conductive material is comprised of copper and finished silver.
18. The method of claim 11 wherein the second shielding layer is covered in a conductive material.
19. The method of claim 18 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.
20. The method of claim 18 wherein the conductive material is comprised of copper and finished silver. Agent for the Applicant, Korakh & Co. Lilach Goldman Patent Attorney 29
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/146,019 US9627816B2 (en) | 2012-02-13 | 2016-05-04 | High speed grounded communication jack |
PCT/US2017/030968 WO2017192800A1 (en) | 2016-05-04 | 2017-05-04 | High speed grounded communication jack |
Publications (2)
Publication Number | Publication Date |
---|---|
IL262491A true IL262491A (en) | 2018-12-31 |
IL262491B IL262491B (en) | 2022-04-01 |
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Application Number | Title | Priority Date | Filing Date |
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IL262491A IL262491B (en) | 2016-05-04 | 2018-10-21 | High speed communication jack |
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EP (1) | EP3453081A4 (en) |
JP (1) | JP7339734B2 (en) |
KR (1) | KR102318866B1 (en) |
CN (1) | CN109478747B (en) |
AU (1) | AU2017260462B2 (en) |
BR (1) | BR112018071868A2 (en) |
CA (1) | CA3022689A1 (en) |
IL (1) | IL262491B (en) |
MX (1) | MX2018013320A (en) |
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RU (1) | RU2713644C1 (en) |
TW (1) | TWI743118B (en) |
WO (1) | WO2017192800A1 (en) |
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JP2023028712A (en) * | 2021-08-20 | 2023-03-03 | 日本航空電子工業株式会社 | connector assembly |
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DE69421798T2 (en) * | 1994-03-26 | 2004-07-15 | Molex Inc., Lisle | Modular Jack connector |
JP2003224408A (en) * | 2002-01-30 | 2003-08-08 | Kyocera Corp | High-frequency wiring board |
US6769937B1 (en) * | 2003-05-13 | 2004-08-03 | Molex Incorporated | Modular jack assembly for jack plugs with varying numbers of wires |
US7182649B2 (en) * | 2003-12-22 | 2007-02-27 | Panduit Corp. | Inductive and capacitive coupling balancing electrical connector |
EP1774625B1 (en) * | 2004-07-13 | 2014-06-25 | Panduit Corporation | Communications connector with flexible printed circuit board |
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-
2017
- 2017-05-03 TW TW106114632A patent/TWI743118B/en active
- 2017-05-04 WO PCT/US2017/030968 patent/WO2017192800A1/en unknown
- 2017-05-04 MX MX2018013320A patent/MX2018013320A/en unknown
- 2017-05-04 JP JP2018557872A patent/JP7339734B2/en active Active
- 2017-05-04 RU RU2018138613A patent/RU2713644C1/en active
- 2017-05-04 EP EP17793306.6A patent/EP3453081A4/en active Pending
- 2017-05-04 BR BR112018071868-8A patent/BR112018071868A2/en not_active Application Discontinuation
- 2017-05-04 CN CN201780027344.3A patent/CN109478747B/en active Active
- 2017-05-04 CA CA3022689A patent/CA3022689A1/en not_active Abandoned
- 2017-05-04 KR KR1020187031440A patent/KR102318866B1/en active IP Right Grant
- 2017-05-04 AU AU2017260462A patent/AU2017260462B2/en not_active Ceased
-
2018
- 2018-10-21 IL IL262491A patent/IL262491B/en unknown
- 2018-10-26 PH PH12018502285A patent/PH12018502285A1/en unknown
Also Published As
Publication number | Publication date |
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TWI743118B (en) | 2021-10-21 |
IL262491B (en) | 2022-04-01 |
BR112018071868A2 (en) | 2019-02-19 |
RU2713644C1 (en) | 2020-02-05 |
MX2018013320A (en) | 2019-03-01 |
KR20190000888A (en) | 2019-01-03 |
JP2019519068A (en) | 2019-07-04 |
AU2017260462A1 (en) | 2018-11-15 |
EP3453081A1 (en) | 2019-03-13 |
CA3022689A1 (en) | 2017-11-09 |
TW201813215A (en) | 2018-04-01 |
CN109478747A (en) | 2019-03-15 |
WO2017192800A1 (en) | 2017-11-09 |
CN109478747B (en) | 2021-03-05 |
KR102318866B1 (en) | 2021-10-28 |
JP7339734B2 (en) | 2023-09-06 |
EP3453081A4 (en) | 2020-01-22 |
PH12018502285A1 (en) | 2019-07-15 |
AU2017260462B2 (en) | 2021-05-20 |
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