WO2019127337A1 - 一种半导体芯片的封装结构及其封装方法 - Google Patents

一种半导体芯片的封装结构及其封装方法 Download PDF

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WO2019127337A1
WO2019127337A1 PCT/CN2017/119763 CN2017119763W WO2019127337A1 WO 2019127337 A1 WO2019127337 A1 WO 2019127337A1 CN 2017119763 W CN2017119763 W CN 2017119763W WO 2019127337 A1 WO2019127337 A1 WO 2019127337A1
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layer
metal
silicon
rewiring
semiconductor chip
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PCT/CN2017/119763
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English (en)
French (fr)
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张黎
赖志明
陈锦辉
陈栋
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江阴长电先进封装有限公司
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Publication of WO2019127337A1 publication Critical patent/WO2019127337A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the invention relates to a package structure of a semiconductor chip and a packaging method thereof, and belongs to the technical field of semiconductor chip packaging.
  • the wafer level chip size package is an advanced packaging method, which is a package method in which a whole wafer is first packaged and then cut into a single chip.
  • the chip size is required to be smaller and the thickness is thinner.
  • the product is not only easy to be damaged during the packaging process; but also the product failure occurs in the back-end application process, so it is necessary to provide sufficient protection for the six sides of the chip. To meet the increasingly demanding requirements.
  • the conventional package structure as shown in FIG. 1, is directly connected to the copper post and the solder ball is disposed at the top end of the copper post, and the electrical signal of the chip electrode is conducted outward through the copper post. Since the solder ball is positioned at the top of the copper post, it is inevitable that the solder ball stress acts directly on the chip through the copper post, resulting in a decrease in reliability.
  • the solder ball Since the solder ball is connected to the chip electrode through the copper post, the solder ball needs to have enough solder to ensure connection with the substrate such as the PCB, and thus, conversely, the copper post is not too thin, and the chip electrode cannot be too small, that is, the chip Can not be too small, does not meet the miniaturization requirements of chip size.
  • the object of the present invention is to overcome the deficiencies of the conventional package structure, and to provide a package structure of a semiconductor chip and a package method thereof to improve the reliability of the package structure.
  • a semiconductor chip package structure includes a silicon base body having a passivation layer on a front surface thereof and a chip electrode embedded therein, wherein the passivation layer opening exposes an upper surface of the chip electrode, wherein
  • a rewiring metal layer I is disposed above the silicon base body and a plurality of input/output terminals I are disposed, the rewiring metal layer I is fixed to the chip electrode, and a metal pillar is disposed at the input/output terminal I.
  • the height of the metal column is >40 microns
  • the invention further includes an encapsulation layer, a dielectric layer and a protective layer, the encapsulation layer wrapping the exposed surface of the metal pillar and the rewiring metal layer I and the sidewall of the silicon basic body, and exposing the upper surface of the metal pillar,
  • the dielectric layer is disposed on the upper surface of the encapsulation layer, and the dielectric layer is opened to expose the upper surface of the metal pillar.
  • the upper surface of the dielectric layer is provided with a rewiring metal layer II and an input/output terminal II.
  • the rewiring metal layer II is fixed to the metal pillar through a dielectric layer opening, and the input/output terminal II is disposed on the metal pillar Outside the vertical area,
  • the protective layer filling the exposed surface of the rewiring metal layer II and the dielectric layer and exposing the upper surface of the connecting member;
  • the thickness of the encapsulation layer from the silicon base body to the dielectric layer is H>40 ⁇ m;
  • a back surface protective layer is provided on the back surface of the silicon base body.
  • a back metal layer is disposed between the back surface of the silicon base body and the back surface protective layer.
  • the connector is a solder ball, solder bump or pad structure.
  • the pad structure is a Ni/Au layer.
  • the pad structure is a Cu/Sn layer.
  • the invention also provides a packaging method of a semiconductor chip package structure, and the implementation steps are as follows:
  • Step 1 providing a silicon-based wafer having a passivation layer on the front surface and a chip electrode embedded therein, the opening of the passivation layer exposing the upper surface of the chip electrode (the passivation layer, the chip electrode, and the passivation layer opening are not shown), There is also a cutting track.
  • the silicon-based wafer is etched along the dicing street by a dry etching method to form a trench, the trench does not penetrate the silicon-based wafer, the back surface of the silicon-based wafer is still connected, and the blade can be directly cut to form a trench;
  • Step 2 sequentially forming a rewiring metal layer I and an input/output terminal I on the front side of the silicon-based wafer by sputtering, photolithography, and electroplating;
  • Step 3 forming a metal pillar having a height greater than micrometer by sputtering, photolithography, or electroplating on the upper surface of the rewiring metal layer I, and the metal pillar is fixedly connected to the input/output terminal I;
  • Step 4 encapsulating the metal pillar by lamination, re-wiring the metal layer I and the trench and the bare portion of the silicon-based wafer to form an encapsulation layer;
  • Step 5 grinding the encapsulation layer to expose the upper surface of the metal pillar
  • Step 6 Cover the dielectric layer on the encapsulation layer and form a dielectric layer opening to expose the upper surface of the metal pillar.
  • Step 7 Forming a rewiring metal layer II and an input/output terminal II on the upper surface of the dielectric layer by sputtering, photolithography, and electroplating;
  • Step 8 The protective layer is used to protect the bare portion of the rewiring metal layer II and the dielectric layer by lamination, and the protective layer opening is formed to expose the input/output terminal II, and the solder ball is formed at the input/output terminal II to complete the silicon-based crystal. Round front encapsulation process;
  • Step 9 Grinding and thinning the back surface of the silicon-based wafer, thinning to expose the bottom of the trench, and etching the back side of the thinned silicon-based wafer with a strong acid such as nitric acid or hydrofluoric acid, and then using a weak base
  • a strong acid such as nitric acid or hydrofluoric acid
  • Step ten attaching a backing film on the back surface of the back surface to form a back protective layer
  • Step 11 performing cutting to form a single semiconductor chip package structure.
  • the rewiring metal layer I is multilayer rewiring.
  • the metal pillar is made of copper, tin, or nickel.
  • step 10 a plurality of layers of metal are sequentially deposited on the back surface pretreatment surface 13 to form a back metal layer.
  • the invention realizes the complete coating of the chip, and the chip is properly protected without physical defects such as chipping and cracking;
  • the invention realizes electrical signal connection and stress structure design through metal column and rewiring, and the position of the solder ball is not above the metal column, thereby effectively preventing the stress of the solder ball from directly acting on the chip through the copper column, thereby improving reliability;
  • the metal column can effectively transfer the stress generated by the product in the rewiring or bump process, thereby effectively protecting the area such as the chip pad and improving the mechanical properties of the product; and the module has a short interconnect transmission path. Guaranteed excellent electrical performance of the product;
  • the semiconductor chip package structure of the present invention provides a dielectric layer between the rewiring metal layer and the coating resin, thereby solving the problem that the rewiring metal layer directly adheres to the coating resin and has poor adhesion, thereby improving reliability.
  • FIG. 1 is a schematic cross-sectional view showing a conventional semiconductor chip package structure
  • FIGS. 2A and 2B are schematic cross-sectional views showing an embodiment of a semiconductor chip package structure according to the present invention.
  • FIGS. 2A-2L are schematic diagrams showing a process flow of a packaging method of a semiconductor chip package structure according to the present invention.
  • a semiconductor chip package structure of the present invention as shown in FIG. 2 and FIG. 3, a front surface of the silicon base body 10 is provided with a passivation layer and a chip electrode is embedded, and the passivation layer opening exposes the upper surface of the chip electrode, and the passivation The layers, chip electrodes, and passivation layer openings are not shown.
  • a rewiring metal layer I14 is disposed above the silicon base body and a plurality of input/output terminals I141 are disposed, the rewiring metal layer I14 is fixed to the chip electrode, and a metal pillar 20 is disposed at the input/output terminal I141, The height of the metal post 20 is > 40 microns.
  • the encapsulation layer 40 wraps the exposed surface of the metal post 20 and the rewiring metal layer I14 and the sidewall of the silicon base 10, and exposes the upper surface of the metal post 20.
  • a dielectric layer 50 is disposed on the upper surface of the encapsulation layer 40, and a dielectric layer opening 501 is formed to expose the upper surface of the metal pillar 20.
  • a rewiring metal layer II30 and an input/output terminal II31 are disposed on the upper surface of the dielectric layer 50, and the rewiring metal layer II30 is fixed to the metal post 20 through the dielectric layer opening 501, and the input/output terminal II31 is disposed at Outside the vertical area of the metal post 20.
  • a connector 60 is provided at the input/output terminal II31, and the connector 60 is a solder ball, a solder bump or a Ni/Au layer pad structure, and a Cu/Sn layer pad structure.
  • the connector 60 is arranged in a display, as shown in FIG. 3, and is a 2*2 matrix.
  • the protective layer 70 fills the exposed side of the rewiring metal layer II30 and the dielectric layer 50 and exposes the upper surface of the connector 60.
  • the encapsulation layer 40 has a thickness H>40 micrometers from the silicon base body 10 to the dielectric layer 50.
  • the encapsulation layer 40 has good strength and thickness, and effectively buffers stress from the solder balls.
  • a back surface protective layer 18 is directly disposed on the back surface of the silicon base body 10. It is also possible to provide a back metal layer 16 and a back surface protective layer 18 on the back surface of the silicon substrate 10.
  • the dielectric layer 50 has a good bonding force with the coating resin of the encapsulation layer 40 and the rewiring metal layer II30, and solves the direct bonding adhesion between the rewiring metal layer II30 and the coating resin. Poor question.
  • a method for packaging a semiconductor chip package structure of the present invention the implementation steps of which:
  • a silicon-based wafer 100 which has a passivation layer on the front side and a chip electrode embedded therein, and a passivation layer opening is provided at the metal pad to expose the upper surface of the chip electrode (the above blunt The layer, the chip electrode, and the passivation layer opening are not shown), and a scribe line 107 is provided.
  • the trenches 109 are formed by etching the silicon-based wafer 100 along the scribe line 107 by a dry etching method. The trenches 109 do not penetrate the silicon-based wafer 100, and the back surface of the silicon-based wafer 100 is still connected.
  • the cut groove 109 can also be formed by cutting directly with a blade.
  • Step 2 as shown in FIG. 4C, a rewiring metal layer I14 and an input/output terminal I141 are sequentially formed on the front surface of the silicon-based wafer 100 by sputtering, photolithography, and electroplating. Multiple wiring can be performed as needed to form multilayer rewiring.
  • Step 3 As shown in FIG. 4D, the re-wiring metal layer I14 is formed on the upper surface by sputtering, photolithography, and electroplating to form a metal pillar 20 having a certain height, and the metal pillar 20 is fixed to the input/output terminal I141.
  • the metal pillar 20 may be made of a metal such as copper, tin or nickel, and has a height of more than 40 micrometers.
  • the metal post 20 draws an electrical signal from the chip electrode through the rewiring metal layer I14.
  • Step 4 as shown in FIG. 4E, the metal pillar 20, the re-wiring metal layer I14 and the trench 109, and the bare portion of the silicon-based wafer 100 are encapsulated by lamination with an encapsulant to form an encapsulation layer 40.
  • Step 5 the abrasive encapsulation layer 40 exposes the upper surface of the metal post 20.
  • Step 6 As shown in FIG. 4F, the dielectric layer 50 is covered on the encapsulation layer 40, and a dielectric layer opening 501 is formed to expose the upper surface of the metal pillar 20.
  • Step 8 as shown in FIG. 4H, the bare portion of the rewiring metal layer II30 and the dielectric layer 50 is protected by lamination by the protective layer 70, and the protective layer opening 701 is formed to expose the input/output terminal II31 at the input/output end.
  • II31 forms solder balls 60 to complete the encapsulation process on the front side of the silicon-based wafer 100.
  • Step IX As shown in FIG. 4I, the back surface of the silicon-based wafer 100 is ground and thinned, thinned to expose the bottom of the trench 109, and the back surface of the thinned silicon-based wafer 100 is made of nitric acid and hydrofluoric acid. These strong acids are corroded, and then weakly alkaline cleaning method is formed to form a back surface pretreatment surface 13 which is more favorable for the back gold layer to bond tightly;
  • Step 10 as shown in FIG. 4J and FIG. 4K, a plurality of layers of metal may be sequentially deposited on the back surface pretreatment surface 13 to form the back metal layer 16, and then a backing film is pasted on the back surface of the back metal layer 16 to form a back surface protective layer 18. . It is also possible to apply a backing film to the back surface 13 to form a back surface protective layer 18 to protect the back surface of the silicon-based wafer 100 and to enhance reliability.
  • Step 11 As shown in FIG. 4L, a laser or a blade method is used to perform cutting to form a single semiconductor chip package structure.

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Abstract

一种半导体芯片封装结构及其封装方法，该半导体芯片封装结构包括硅基本体（10），硅基本体（10）的上方设置再布线金属层Ⅰ（14），在输入/输出端Ⅰ（141）设置金属柱（20），包封层（40）包裹金属柱（20）和再布线金属层Ⅰ（14）的裸露面以及硅基本体（10）的侧壁，并露出金属柱（20）的上表面，介电层（50）设置在包封层（40）的上表面，并开设介电层开口（501）露出金属柱（20）的上表面，介电层（50）的上表面设置再布线金属层Ⅱ（30），再布线金属层Ⅱ（30）通过介电层开口（501）与金属柱（20）固连，输入/输出端Ⅱ（31）设置在金属柱（20）的垂直区域之外，保护层（70）填充再布线金属层Ⅱ（30）和介电层（50）的裸露面并露出连接件（60）的上表面；包封层（40）于硅基本体（10）至介电层（50）的厚度H＞40微米。该半导体芯片封装结构及其封装方法能够有效保护芯片。

Description

一种半导体芯片的封装结构及其封装方法 技术领域
本发明涉及一种半导体芯片的封装结构及其封装方法，属于半导体芯片封装技术领域。
背景技术
在当前的半导体封装技术中，晶圆级芯片尺寸封装是一种先进封装方法，它是先将整片晶圆进行封装，再切割得到单颗芯片的封装方法。随着电子产品的发展，要求芯片尺寸更小、厚度越薄，产品不仅在封装过程中容易损伤；而且在后端应用过程中也易出现产品失效，因此需要对芯片六个面提供足够的保护，以满足日益苛刻的要求。
传统的封装结构，如图1所示，芯片电极与铜柱直接连接，焊球设置在铜柱的顶端，芯片电极的电信号通过铜柱向外传导。由于焊球位置在铜柱的顶端，不可避免将焊球应力直接通过铜柱作用到芯片上，导致了可靠性的降低。
因焊球通过铜柱与芯片电极连接，焊球需要有足够的焊料来保证与PCB等基板的连接，因而，反过来约束了铜柱不能太细，芯片电极不能太小，也就是说，芯片不能太小，不符合芯片尺寸的小型化发展要求。
发明内容
本发明的目的在于克服传统的封装结构的不足，提供一种半导体芯片的封装结构及其封装方法，以提高封装结构的可靠性。
本发明的目的是这样实现的：
本发明一种半导体芯片封装结构，其包括硅基本体，所述硅基本体的正面设有钝化层并嵌有芯片电极，其钝化层开口露出芯片电极的上表面，其特征在于，
在所述硅基本体的上方设置再布线金属层Ⅰ并设置若干个输入/输出端Ⅰ，所述再布线金属层Ⅰ与芯片电极固连，在所述输入/输出端Ⅰ设置金属柱，所述金属柱的高度＞40微米，
还包括包封层、介电层和保护层，所述包封层包裹金属柱和再布线金属层Ⅰ的裸露面以及硅基本体的侧壁，并露出金属柱的上表面，
所述介电层设置在包封层的上表面，并开设介电层开口露出金属柱的上表面，
所述介电层的上表面设置再布线金属层Ⅱ和输入/输出端Ⅱ，所述再布线金属层Ⅱ通过介电层开口与金属柱固连，所述输入/输出端Ⅱ设置在金属柱的垂直区域之外，
在所述输入/输出端Ⅱ设置连接件，所述保护层填充再布线金属层Ⅱ和介电层的裸露面并露出连接件的上表面；
所述包封层于硅基本体至介电层的厚度H＞40微米；
所述硅基本体的背面设置背面保护层。
可选地所述硅基本体的背面与背面保护层之间设置背面金属层。
可选地所述连接件为焊球、焊块或焊盘结构。
可选地所述焊盘结构为Ni/Au层。
可选地所述焊盘结构为Cu/Sn层。
本发明还提供了一种半导体芯片封装结构的封装方法，其实施步骤如下：
步骤一、提供硅基晶圆，其正面有钝化层并嵌有芯片电极，钝化层开口露出芯片电极的上表面(上述钝化层、芯片电极、钝化层开口均未示出)，并设有切割道。通过干法刻蚀方法沿切割道刻蚀硅基晶圆形成沟槽，沟槽不穿透硅基晶圆，硅基晶圆的背面仍旧连接，亦可用刀片直接切割形成沟槽；
步骤二、在硅基晶圆正面依次通过溅射、光刻、电镀制作再布线金属层Ⅰ和输入/输出端Ⅰ；
步骤三、在再布线金属层Ⅰ的上表面依次通过溅射、光刻、电镀方式形成高度大于微米的金属柱，所述金属柱与输入/输出端Ⅰ固连；
步骤四、用包封料通过层压方式包封金属柱、再布线金属层Ⅰ和沟槽以及硅基晶圆的裸露部分，形成包封层；
步骤五、研磨包封层露出金属柱的上表面；
步骤六、在上述包封层上覆盖介电层，并形成介电层开口，露出金属柱的上表面。
步骤七、在介电层的上表面依次通过溅射、光刻、电镀形成再布线金属层Ⅱ和输入/输出端Ⅱ；
步骤八、用保护层通过层压方式保护再布线金属层Ⅱ和介电层的裸露部分，并形成保护层开口露出输入/输出端Ⅱ，在输入/输出端Ⅱ形成焊球，完成硅基晶 圆正面的包封工艺；
步骤九、对硅基晶圆背面进行研磨减薄，减薄至露出沟槽的底部，并对减薄后的硅基晶圆的背面用硝酸、氢氟酸这些强酸进行腐蚀，再用弱碱性清洁的方法，形成较利于背金层粘结紧密的背面预处理面；
步骤十、在背面预处理面贴上背胶膜形成背面保护层；
步骤十一、进行切割形成单颗半导体芯片封装结构。
可选地，所述再布线金属层Ⅰ为多层再布线。
可选地，所述金属柱的材质为铜、锡、镍。
可选地，在步骤十中、在背面预处理面13依次蒸镀若干层金属形成背面金属层。
本发明的技术方案具有以下优点：
1)本发明实现了芯片的全面包覆，芯片得到了妥善保护，不会产生崩边，开裂等物理缺陷；
2)本发明是通过金属柱和再布线实现电信号连接与应力结构设计，焊球位置不在金属柱的上面，有效的避免了焊球应力直接通过铜柱作用到芯片上，提升了可靠性；该金属柱可以有效的将产品在再布线或凸块工艺中产生的应力进行转移，从而有效的保护芯片焊盘等区域，提升了产品的力学性能；同时该模块由于较短的互联传输路径，保证了产品极佳的电学性能；
3)不需要考虑铜柱的截面与焊球的尺寸的匹配，有效地缩小了铜柱的直径，有利于芯片尺寸的小型化发展；本发明采用扇入结构，芯片尺寸与封装尺寸几乎等当大小；
4)本发明半导体芯片封装结构，其在再布线金属层与包覆树脂之间设置介电层，解决了再布线金属层与包覆树脂直接结合黏附力差的问题，提升了可靠性。
附图说明
图1为传统半导体芯片封装结构的剖面示意图；
图2A和2B为本实用新型一种半导体芯片封装结构的实施例的剖面示意图；
图2A-图2L为本发明一种半导体芯片封装结构的封装方法的工艺流程的示意图；
图中：
硅基本体10
再布线金属层Ⅰ14
输入/输出端Ⅰ141
背面预处理面13
背面金属层16
背面保护层18
金属柱20
包封层40
再布线金属层Ⅱ30
输入/输出端Ⅱ31
介电层50
介电层开口501
连接件60。
具体实施方式
下面结合附图对本发明的具体实施方式进行详细说明。
实施例
本发明一种半导体芯片封装结构，如图2和图3所示，其硅基本体10的正面设有钝化层并嵌有芯片电极，钝化层开口露出芯片电极的上表面，上述钝化层、芯片电极、钝化层开口均未示出。
在所述硅基本体的上方设置再布线金属层Ⅰ14并设置若干个输入/输出端Ⅰ141，所述再布线金属层Ⅰ14与芯片电极固连，在所述输入/输出端Ⅰ141设置金属柱20，所述金属柱20的高度＞40微米。包封层40包裹金属柱20和再布线金属层Ⅰ14的裸露面以及硅基本体10的侧壁，并露出金属柱20的上表面。
在包封层40的上表面设置介电层50，并开设介电层开口501露出金属柱20的上表面。在介电层50的上表面设置再布线金属层Ⅱ30和输入/输出端Ⅱ31，所述再布线金属层Ⅱ30通过介电层开口501与金属柱20固连，所述输入/输出端Ⅱ31设置在金属柱20的垂直区域之外。
在所述输入/输出端Ⅱ31设置连接件60，所述连接件60为焊球、焊块或Ni/Au 层焊盘结构、Cu/Sn层焊盘结构。连接件60呈陈列排布，如图3所示，为2*2的矩阵。所述保护层70填充再布线金属层Ⅱ30和介电层50的裸露面并露出连接件60的上表面。
所述包封层40于硅基本体10至介电层50的厚度H＞40微米，包封层40有很好的强度和厚度，有效的缓冲来自焊球的应力。
所述硅基本体10的背面直接设置背面保护层18。也可以在硅基本体10的背面先设置背面金属层16再设置背面保护层18。
本发明的半导体芯片封装结构，该介电层50具有与包封层40的包覆树脂和再布线金属层Ⅱ30很好的结合力，解决了再布线金属层Ⅱ30与包覆树脂直接结合黏附力差的问题。
本发明一种半导体芯片封装结构的封装方法，其实施步骤：
步骤一、如图4A和4B所示，提供硅基晶圆100，其正面有钝化层并嵌有芯片电极，在金属焊盘处设有钝化层开口露出芯片电极的上表面(上述钝化层、芯片电极、钝化层开口均未示出)，并设有切割道107。一般地，在切割道107内若有无效的钝化层或金属焊盘，可用激光切割去除。通过干法刻蚀方法沿切割道107刻蚀硅基晶圆100形成沟槽109，沟槽109不穿透硅基晶圆100，硅基晶圆100的背面仍旧连接。亦可用刀片直接切割形成切割后的沟槽109。
步骤二、如图4C所示，在硅基晶圆100正面依次通过溅射、光刻、电镀制作再布线金属层Ⅰ14和输入/输出端Ⅰ141。根据需要可以多次布线，形成多层再布线。
步骤三、如图4D所示，在再布线金属层Ⅰ14是上表面依次通过溅射、光刻、电镀方式形成一定高度的金属柱20，所述金属柱20与输入/输出端Ⅰ141固连。该金属柱20的材质可为铜、锡、镍等金属，其高度大于40微米。该金属柱20将电信号从芯片电极通过再布线金属层Ⅰ14引出。
步骤四、如图4E所示，用包封料通过层压方式包封金属柱20、再布线金属层Ⅰ14和沟槽109以及硅基晶圆100的裸露部分，形成包封层40。
步骤五、研磨包封层40露出金属柱20的上表面。
步骤六、如图4F所示，在上述包封层40上覆盖介电层50，并形成介电层开口501，露出金属柱20的上表面。
步骤七、如图4G所示，在介电层50的上表面依次通过溅射、光刻、电镀形成再布线金属层Ⅱ30和输入/输出端Ⅱ31；所述再布线金属层Ⅱ30为多层再布线。
步骤八、如图4H所示，用保护层70通过层压方式保护再布线金属层Ⅱ30和介电层50的裸露部分，并形成保护层开口701露出输入/输出端Ⅱ31，在输入/输出端Ⅱ31形成焊球60，完成硅基晶圆100正面的包封工艺。
步骤九、如图4I所示，对硅基晶圆100背面进行研磨减薄，减薄至露出沟槽109的底部，并对减薄后的硅基晶圆100的背面用硝酸、氢氟酸这些强酸进行腐蚀，再用弱碱性清洁的方法，形成较利于背金层粘结紧密的背面预处理面13；
步骤十、如图4J和图4K所示，可以在背面预处理面13依次蒸镀若干层金属形成背面金属层16，之后再在背面金属层16的背面贴上背胶膜形成背面保护层18。也可以在背面预处理面13贴上背胶膜形成背面保护层18，以保护硅基晶圆100的背面，并加强可靠性。
步骤十一、如图4L所示，采用激光或刀片方式，进行切割形成单颗半导体芯片封装结构。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步地详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围。凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种半导体芯片封装结构，其特征在于，其包括硅基本体，所述硅基本体的正面设有钝化层并嵌有芯片电极，其钝化层开口露出芯片电极的上表面，其特征在于，
    在所述硅基本体的上方设置再布线金属层Ⅰ并设置若干个输入/输出端Ⅰ，所述再布线金属层Ⅰ与芯片电极固连，在所述输入/输出端Ⅰ设置金属柱，所述金属柱的高度＞40微米，
    还包括包封层、介电层和保护层，所述包封层包裹金属柱和再布线金属层Ⅰ的裸露面以及硅基本体的侧壁，并露出金属柱的上表面，
    所述介电层设置在包封层的上表面，并开设介电层开口露出金属柱的上表面，
    所述介电层的上表面设置再布线金属层Ⅱ和输入/输出端Ⅱ，所述再布线金属层Ⅱ通过介电层开口与金属柱固连，所述输入/输出端Ⅱ设置在金属柱的垂直区域之外，
    在所述输入/输出端Ⅱ设置连接件，所述保护层填充再布线金属层Ⅱ和介电层的裸露面并露出连接件的上表面；
    所述包封层于硅基本体至介电层的厚度H＞40微米；
    所述硅基本体的背面设置背面保护层。
  2. 根据权利要求1所述的半导体芯片封装结构，其特征在于，所述硅基本体的背面与背面保护层之间设置背面金属层。
  3. 根据权利要求1所述的半导体芯片封装结构，其特征在于，所述连接件为焊球、焊块或焊盘结构。
  4. 根据权利要求3所述的半导体芯片封装结构，其特征在于，所述焊盘结构为Ni/Au层。
  5. 根据权利要求3所述的半导体芯片封装结构，其特征在于，所述焊盘结构为Cu/Sn层。
  6. 一种半导体芯片封装结构的封装方法，其实施步骤如下：
    步骤一、提供硅基晶圆，其正面有钝化层并嵌有芯片电极，钝化层开口露出芯片电极的上表面(上述钝化层、芯片电极、钝化层开口均未示出)，并设有切割道。通过干法刻蚀方法沿切割道刻蚀硅基晶圆形成沟槽，沟槽不穿透硅基晶圆， 硅基晶圆的背面仍旧连接，亦可用刀片直接切割形成沟槽；
    步骤二、在硅基晶圆正面依次通过溅射、光刻、电镀制作再布线金属层Ⅰ和输入/输出端Ⅰ；
    步骤三、在再布线金属层Ⅰ的上表面依次通过溅射、光刻、电镀方式形成高度大于40微米的金属柱，所述金属柱与输入/输出端Ⅰ固连；
    步骤四、用包封料通过层压方式包封金属柱、再布线金属层Ⅰ和沟槽以及硅基晶圆的裸露部分，形成包封层；
    步骤五、研磨包封层露出金属柱的上表面；
    步骤六、在上述包封层上覆盖介电层，并形成介电层开口，露出金属柱的上表面。
    步骤七、在介电层的上表面依次通过溅射、光刻、电镀形成再布线金属层Ⅱ和输入/输出端Ⅱ；
    步骤八、用保护层通过层压方式保护再布线金属层Ⅱ和介电层的裸露部分，并形成保护层开口露出输入/输出端Ⅱ，在输入/输出端Ⅱ形成焊球，完成硅基晶圆正面的包封工艺；
    步骤九、对硅基晶圆背面进行研磨减薄，减薄至露出沟槽的底部，并对减薄后的硅基晶圆的背面用硝酸、氢氟酸这些强酸进行腐蚀，再用弱碱性清洁的方法，形成较利于背金层粘结紧密的背面预处理面；
    步骤十、在背面预处理面贴上背胶膜形成背面保护层；
    步骤十一、进行切割形成单颗半导体芯片封装结构。
  7. 根据权利要求6所述的半导体芯片封装结构的封装方法，其特征在于，所述再布线金属层Ⅰ为多层再布线。
  8. 根据权利要求6所述的半导体芯片封装结构的封装方法，其特征在于，所述金属柱的材质为铜、锡、镍。
  9. 根据权利要求6所述的半导体芯片封装结构的封装方法，其特征在于，在步骤十中、在背面预处理面依次蒸镀若干层金属形成背面金属层。
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