CN107527885A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN107527885A
CN107527885A CN201710416609.0A CN201710416609A CN107527885A CN 107527885 A CN107527885 A CN 107527885A CN 201710416609 A CN201710416609 A CN 201710416609A CN 107527885 A CN107527885 A CN 107527885A
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semiconductor chip
semiconductor
extension
chip
semiconductor device
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CN201710416609.0A
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CN107527885B (zh
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张元基
李东沅
姜明成
刘惠仁
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
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Abstract

一种制造半导体装置的方法包括：在封装衬底上堆叠第一半导体芯片。第一半导体芯片中的每一个包括第一粘合膜。所述方法包括在第一半导体芯片上分别堆叠第二半导体芯片。第二半导体芯片中的每一个包括第二粘合膜。所述方法包括挤压第一粘合膜及第二粘合膜以形成粘合结构。粘合结构包括设置在第一半导体芯片的侧壁上及第二半导体芯片的侧壁上的延伸部。所述方法包括移除延伸部。所述方法包括形成实质上覆盖第一半导体芯片及第二半导体芯片的第一模制层。所述方法包括对第一半导体芯片之间与第二半导体芯片之间的封装衬底执行切割工艺，以形成多个半导体封装。所述制造半导体装置的方法可有效地移除覆盖半导体芯片的粘合结构的延伸部。

Description

制造半导体装置的方法
[相关申请的交叉参考]
本申请主张在2016年6月15日提出申请的第10-2016-0074740号韩国专利申请的优先权，所述韩国专利申请的公开内容全文以引用的方式并入本案。
技术领域
本发明概念的示例性实施例涉及一种半导体装置，且更具体来说，涉及一种具有堆叠半导体芯片的半导体装置及其制作方法。
背景技术
半导体装置可具有相对高的容量，且可相对薄并相对小。各种封装技术中的一种方式是垂直堆叠多个半导体芯片以形成相对高密度的半导体芯片封装的封装技术。可将具有各种功能的堆叠半导体芯片集成在相对小的面积中。
发明内容
本发明概念的一个或多个示例性实施例提供一种具有相对高的机械耐用性的半导体装置。根据本发明概念的一个或多个示例性实施例的半导体装置可包括用作底部填充物(under-fill)的粘合结构。
本发明概念的一个或多个示例性实施例提供一种制作半导体装置的方法，所述方法可消除用于覆盖所述半导体装置中的堆叠半导体芯片的粘合结构的延伸部。
根据本发明概念的一个或多个示例性实施例，一种制造半导体装置的方法包括：在封装衬底上堆叠水平相互间隔开的第一半导体芯片。所述第一半导体芯片中的每一个包括面对所述封装衬底的第一粘合膜(adhesive film)。所述方法包括在所述第一半导体芯片上分别堆叠水平相互间隔开的第二半导体芯片。所述第二半导体芯片中的每一个包括面对所述第一半导体芯片的第二粘合膜。所述方法包括挤压所述第一粘合膜及所述第二粘合膜以形成粘合结构。所述粘合结构包括设置在所述第一半导体芯片的侧壁上及所述第二半导体芯片的侧壁上的延伸部。所述方法包括从所述第二半导体芯片的所述侧壁移除所述延伸部。所述方法包括形成实质上覆盖所述第一半导体芯片及所述第二半导体芯片的第一模制层(molding layer)。所述方法包括对所述第一半导体芯片之间与所述第二半导体芯片之间的所述封装衬底执行切割工艺，以形成多个半导体封装，所述多个半导体封装各自包括所述第一半导体芯片中的至少一个及所述第二半导体芯片中的至少一个。
根据本发明概念的一个或多个示例性实施例，一种制造半导体装置的方法包括：在封装衬底上形成水平相互间隔开的多个堆叠结构，所述堆叠结构中的每一个包括垂直堆叠的多个半导体芯片。所述方法包括形成分别填充所述多个堆叠结构中毗邻的堆叠结构之间的空间的粘合结构。所述方法包括移除所述毗邻的堆叠结构之间的所述粘合结构的至少一部分。形成所述堆叠结构及所述粘合结构包括对所述多个半导体芯片依序进行堆叠及挤压，所述多个半导体芯片各自包括设置在所述半导体芯片的面对所述封装衬底的表面上的粘合膜。
根据本发明概念的一个或多个示例性实施例，一种制造半导体装置的方法，包括以下步骤。在封装衬底上堆叠多个第一半导体芯片，其中所述多个第一半导体芯片在所述封装衬底上相互间隔开，且其中所述多个第一半导体芯片中的每一个包括第一粘合膜。将多个第二半导体芯片中的第二半导体芯片分别堆叠在所述多个第一半导体芯片中的对应一个第一半导体芯片上，其中所述多个第二半导体芯片中的每一个包括第二粘合膜。将多个第三半导体芯片中的第三半导体芯片分别堆叠在所述多个第二半导体芯片中的对应一个第二半导体芯片上，其中所述多个第三半导体芯片中的每一个包括第三粘合膜。堆叠所述多个第一半导体芯片、所述多个第二半导体芯片及所述多个第三半导体芯片而形成在所述封装衬底上相互间隔开的多个堆叠结构，所述多个堆叠结构中的每一个包括粘合结构，所述粘合结构包括所述第一粘合膜、所述第二粘合膜及所述第三粘合膜，且其中所述粘合结构包括设置在所述第一半导体芯片、所述第二半导体芯片及所述第三半导体芯片中的相应者的多个侧壁上的多个延伸部。在所述多个第三半导体芯片的多个上表面上以及在位于所述多个堆叠结构中毗邻的多个堆叠结构之间的多个空间中的所述多个延伸部上形成第一模制层。移除所述多个第三半导体芯片中毗邻的多个第三半导体芯片之间的所述第一模制层。在通过移除所述多个第三半导体芯片中毗邻的多个第三半导体芯片之间的所述第一模制层而形成的多个空间的每一个中形成第二模制层。通过切穿所述第一模制层及所述第二模制层并切穿所述多个堆叠结构中毗邻的多个堆叠结构之间的所述封装衬底，而将所述多个堆叠结构中的每一个相互分离。
根据本发明概念的一个或多个示例性实施例，一种半导体装置包括第一半导体芯片，所述第一半导体芯片堆叠在封装衬底上且包括第一通孔(through via)。在所述第一半导体芯片上堆叠有第二半导体芯片且所述第二半导体芯片包括第二通孔。在所述封装衬底与所述第一半导体芯片之间设置有第一互连构件(interconnect member)且所述第一互连构件电连接至所述第一通孔。在所述第一半导体芯片与所述第二半导体芯片之间设置有第二互连构件且所述第二互连构件电连接至所述第二通孔。第一粘合层实质上填充所述封装衬底与所述第一半导体芯片之间的第一空间且实质上覆盖所述第一互连构件。第二粘合层实质上填充所述第一半导体芯片与所述第二半导体芯片之间的第二空间且实质上覆盖所述第二互连构件。所述第一粘合层及所述第二粘合层中的至少一个包括朝所述第一互连构件及所述第二互连构件中的一个凹陷的凹陷侧壁。
附图说明
通过参照附图详细阐述本发明概念的示例性实施例，本发明概念的以上及其他特征将变得更显而易见，在附图中：
图1、图2、图4、及图6至图13是说明根据本发明概念某些示例性实施例的制作半导体装置的方法的剖视图。
图3是说明图2所绘示的第一半导体芯片的一部分的平面图。
图5A是图4的区段M的放大图。
图5B是说明图4所绘示的第一半导体芯片的一部分的平面图。
图14是说明根据比较例的制造半导体装置的方法的剖视图。
图15是说明图14所绘示的半导体封装的顶表面的平面图。
图16至图19是说明根据本发明概念某些示例性实施例的制造半导体装置的方法的剖视图。
图20、图23、及图24是说明根据本发明概念某些示例性实施例的制造半导体装置的方法的剖视图。
图21是说明根据本发明概念某些示例性实施例的湿蚀刻工艺的流程图。
图22A至图22D是图20的区段N的放大剖视图。
附图标记：
100：封装衬底
102：外侧互连构件
104：连接焊盘
106：头
108：头膜
112：第一互连构件
120：第一半导体芯片
120a：第一有源表面
120b：第一无源表面
120c：中心区
120w：第三侧壁
120x：第四侧壁
120y：第一侧壁
120z：第二侧壁
122：第一电路层
124：第一通孔
132：第一背面垫
140：第一非导电膜
212：第二互连构件
220：第二半导体芯片
220a：第二有源表面
220b：第二无源表面
222：第二电路层
224：第二通孔
232：第二背面垫
240：第二非导电膜
312：第三互连构件
320：第三半导体芯片
320a：第三有源表面
320b：第三无源表面
322：第三电路层
500：第一模制层
505：第一模制图案
550：第二模制层
555：第二模制图案
610：碱性溶液
620：氧化剂
630：还原剂
640：水洗
AS：粘合结构
as1：第一粘合层
as2：第二粘合层
as3：第三粘合层
as1e：第一子延伸部
as2e：第二子延伸部
as3e：第三子延伸部
as1w：第一凹陷侧壁
as2w：第二凹陷侧壁
as3w：第三凹陷侧壁
ASe：延伸部
ASw：凹陷侧壁
BL1：第一刀片
BL2：第二刀片
CR：载体衬底
D1：第一距离
M、N：区段
MO：粘合模具
RG1：第一区
RG2：第二区
RG3：第三区
RP：残留产物
RS1：第一凹陷区
RS2：第二凹陷区
RS3：第三凹陷区
S110、S120、S130、S140：步骤
SS：堆叠结构
SP1：第一空间
SP2：第二空间
SP3：第三空间
T1：第一厚度
W1：第一宽度
W2：第二宽度
WE：湿蚀刻工艺
具体实施方式
图1、图2、图4、及图6至图13是说明根据本发明概念某些示例性实施例的制作半导体装置的方法的剖视图。图3是说明图2所绘示的第一半导体芯片的一部分的平面图。图5A是图4的区段M的放大图。图5B是说明图4所绘示的第一半导体芯片的一部分的平面图。
参照图1，可将封装衬底100粘合至载体衬底CR。举例来说，可通过设置在载体衬底CR与封装衬底100之间的粘合模具(adhesive mold)MO而使载体衬底CR与封装衬底100相互粘合。封装衬底100可包括第一区RG1、第二区RG2、及第三区RG3；然而，本发明概念的示例性实施例并非仅限于此。在本发明概念的示例性实施例中，封装衬底100除第一区RG1、第二区RG2及第三区RG3之外还可包括其他区。封装衬底100可(例如，在封装衬底100的底表面上)包括外侧互连构件102。举例来说，外侧互连构件102可为焊料球，所述焊料球可包含锡、铅、或铜。封装衬底100可包括位于封装衬底100的顶表面上的连接焊盘(landing pad)104。
作为实例，载体衬底CR可为硅晶片或玻璃衬底，且封装衬底100可为印制电路板(printed circuit board，PCB)。封装衬底100可包括一个或多个通孔，外侧互连构件102与连接焊盘104经由所述一个或多个通孔而在垂直方向上相互连接。
参照图2，可将各第一半导体芯片120分别定位在封装衬底100的第一区RG1、第二区RG2及第三区RG3中。各第一半导体芯片120可在实质上彼此相同的水平高度上水平相互间隔开。可以其中第一有源表面(active surface)120a面对封装衬底100的面朝下状态(face-down state)将第一半导体芯片120中的每一个堆叠在封装衬底100上。作为实例，可使用底表面装载有第一半导体芯片120的头106将各第一半导体芯片120实质上同时地粘合至封装衬底100。可在头106与第一半导体芯片120之间设置头膜108。举例来说，头膜108可包括可便于将第一半导体芯片120从头106分开的释放膜(release film)。第一半导体芯片120可各自为实质上同一类型的芯片。作为实例，第一半导体芯片120可各自具有实质上相同的大小且可执行实质上相同的功能。
以下将参照图3更详细地阐述单个第一半导体芯片120。参照图2及图3，第一半导体芯片120可包括其上可设置有第一电路层122的第一有源表面120a及与第一有源表面120a相对的第一无源表面(inactive surface)120b。举例来说，第一半导体芯片120可为存储器芯片。第一半导体芯片120可包括电连接至第一电路层122的第一通孔124。举例来说，第一通孔124中的至少一个可为硅通孔(through silicon via，TSV)。第一通孔124可设置在第一半导体芯片120的中心区120c中。在本发明概念的示例性实施例中，中心区120c可具有十字形状。在第一电路层122中，中心区120c可为外围电路区且除中心区120c之外的其他区可为存储器单元区。
第一半导体芯片120可包括第一侧壁120y、第二侧壁120z、第三侧壁120w及第四侧壁120x。第一侧壁120y与第二侧壁120z可相互面对，且第三侧壁120w与第四侧壁120x可相互面对。第一侧壁120y与第二侧壁120z之间的距离可为第一半导体芯片120在第一方向上的宽度，且第三侧壁120w与第四侧壁120x之间的距离可为第一半导体芯片120在与所述第一方向交叉的第二方向上的宽度。第一方向上的宽度可实质上相同于在与第一方向交叉的第二方向上的宽度；然而，本发明概念的示例性实施例并非仅限于此，且所述宽度可互不相同。
可在第一半导体芯片120的第一有源表面120a上设置第一互连构件112(例如，焊料球(solder ball)或焊料凸块(solder bump))。第一半导体芯片120可经由第一互连构件112而电连接至封装衬底100。可在第一半导体芯片120的第一无源表面120b上设置第一背面垫132。第一背面垫132可电连接至第一通孔124。举例来说，第一互连构件112与第一背面垫132可经由第一通孔124在垂直方向上相互连接。
可将第一非导电膜140粘合至第一半导体芯片120的第一有源表面120a。第一非导电膜140可为不包含导电颗粒的环氧树脂系粘合膜。举例来说，第一非导电膜140可在约100℃或高于100℃的温度下固化。第一非导电膜140可具有第一厚度T1。第一厚度T1可实质上相同于或大于第一互连构件112的突出长度。作为实例，第一非导电膜140可覆盖第一互连构件112且实质上完全填充第一互连构件112之间的空间。第一非导电膜140可不导电。
参照图4、图5A及图5B，可挤压在封装衬底100上堆叠的第一半导体芯片120以分别在第一区RG1、第二区RG2、及第三区RG3上形成第一粘合层as1。可将第一半导体芯片120挤压至使得第一互连构件112可分别实质上接触封装衬底100的各连接焊盘104中的相应一个连接焊盘104的整个上表面。由此，封装衬底100与第一半导体芯片120可相互电连接。
当将第一半导体芯片120堆叠在封装衬底100上时，可实质上同时地挤压各第一半导体芯片120。对第一半导体芯片120进行挤压可包括执行其中对第一半导体芯片120及第一非导电膜140施加热量及压力的热挤压。作为实例，第一半导体芯片120可在比第一非导电膜140的固化温度高的温度下接收来自头106的压力。举例来说，热挤压可包括在从约80℃到约300℃的温度下对第一半导体芯片120施加从约10N到约100N的力。
可挤压第一非导电膜140以分别形成第一粘合层as1。第一粘合层as1中的每一个可填充第一半导体芯片120与封装衬底100之间的第一空间SP1。第一粘合层as1可包括覆盖第一半导体芯片120的第一侧壁120y、第二侧壁120z、第三侧壁120w及第四侧壁120x的第一子延伸部as1e。
作为实例，在热挤压之后，在第一半导体芯片120的第一有源表面120a与封装衬底100的顶表面之间可获得第一距离D1，且第一距离D1可小于第一非导电膜140的第一厚度T1。作为实例，热挤压可减小第一非导电膜140的厚度，使得圆角(fillet)可在第一半导体芯片120外侧从第一非导电膜140突出。可将所突出的圆角固化以形成第一子延伸部as1e。第一子延伸部as1e可沿第一侧壁120y、第二侧壁120z、第三侧壁120w及第四侧壁120x垂直延伸并接触头膜108。头膜108可防止第一子延伸部as1e覆盖第一半导体芯片120的第一无源表面120b。
参照图6，可在第一半导体芯片120上分别堆叠第二半导体芯片220。第二半导体芯片220中的每一个可包括其上形成有第二电路层222的第二有源表面220a及与第二有源表面220a相对的第二无源表面220b。第二半导体芯片220可包括穿透过第二半导体芯片220且电连接至第二电路层222、位于第二有源表面220a上的第二互连构件212、及位于第二无源表面220b上的第二背面垫232的第二通孔224。举例来说，第二半导体芯片220可为与以上更详细阐述的第一半导体芯片120实质上相同的芯片。因此，可不再对其进行重复说明。
可将第二非导电膜240粘合至第二半导体芯片220中的每一个第二半导体芯片220的第二有源表面220a上。第二非导电膜240可为不包含导电颗粒的环氧树脂系粘合膜，且可为与以上更详细地论述的第一非导电膜140实质上相同的膜。第二非导电膜240可不导电。
可以其中第二有源表面220a面对第一半导体芯片120的面朝下状态将第二半导体芯片220中的每一个堆叠在第一半导体芯片120上。作为实例，可使用其底部表面(floorsurface)装载有第二半导体芯片220的头106将各第二半导体芯片220实质上同时地堆叠在各第一半导体芯片120上。第二半导体芯片220可在实质上相同的水平高度上水平相互间隔开。
参照图7，可挤压位于第一半导体芯片120上的第二半导体芯片220以分别在第一区RG1、第二区RG2、及第三区RG3上形成第二粘合层as2。可将第二半导体芯片220挤压至使得第二互连构件212可分别实质上接触第一半导体芯片120的第一背面垫132中的相应一个第一背面垫132的整个上表面。由此，第一半导体芯片120与第二半导体芯片220可相互电连接。
当将第二半导体芯片220堆叠在第一半导体芯片120上时，可实质上同时地挤压第二半导体芯片220。对第二半导体芯片220进行挤压可包括执行热挤压。对第二半导体芯片220进行的挤压可实质上相同于对第一半导体芯片120进行的挤压。
第二粘合层as2中的每一个可填充第一半导体芯片120与第二半导体芯片220之间的第二空间SP2。第二粘合层as2可包括覆盖第二半导体芯片220的侧壁的第二子延伸部as2e。第二子延伸部as2e可为当挤压第二半导体芯片220时，在第二半导体芯片220外侧从第二非导电膜240突出的固化的圆角。第一粘合层as1与第二粘合层as2可成一体地相互连接。
参照图8，可在第二半导体芯片220上分别堆叠第三半导体芯片320。第三半导体芯片320中的每一个可包括其上形成有第三电路层322的第三有源表面320a及与第三有源表面320a相对的第三无源表面320b。第三半导体芯片320可包括位于第三有源表面320a上的第三互连构件312。第三互连构件312不需要垂直地对齐第二通孔224。在本发明概念的示例性实施例中，第三半导体芯片320可不包括通孔；然而，本发明概念的示例性实施例并非仅限于此。第三半导体芯片320中的每一个可为存储器芯片。举例来说，第三半导体芯片320可各自具有比第一半导体芯片120的厚度及第二半导体芯片220的厚度大的厚度。
可将第三非导电膜粘合至第三半导体芯片320中的每一个第三半导体芯片320的第三有源表面320a上。第三非导电膜可为不包含导电颗粒的环氧树脂系粘合膜，且可为与以上更详细地论述的第一非导电膜140实质上相同的膜。第三非导电膜可不导电。
可以其中第三有源表面320a面对第二半导体芯片220的面朝下状态将第三半导体芯片320中的每一个堆叠在第二半导体芯片220上。作为实例，可使用其底部表面装载有第三半导体芯片320的头106将第三半导体芯片320实质上同时地堆叠在第二半导体芯片220上。第三半导体芯片320可在实质上相同的水平高度上水平相互间隔开。
当堆叠有第三半导体芯片320时，可挤压第三半导体芯片320以分别在第一区RG1、第二区RG2、及第三区RG3上形成第三粘合层as3。可将第三半导体芯片320挤压至使得第三互连构件312实质上接触第二半导体芯片220的第二背面垫232中的相应一个第二背面垫232的整个上表面。作为实例，第二半导体芯片220与第三半导体芯片320可相互电连接。因此，依序堆叠的第一半导体芯片120、第二半导体芯片220及第三半导体芯片320可在垂直方向上相互连接且可形成单个堆叠结构SS。可分别在第一区RG1、第二区RG2及第三区RG3中形成多个堆叠结构SS。
对第三半导体芯片320进行挤压可包括执行热挤压。对第三半导体芯片320进行的挤压可实质上相同于对第一半导体芯片120进行的挤压。
第三粘合层as3中的每一个可填充第三半导体芯片320与第二半导体芯片220之间的第三空间SP3。第三粘合层as3可包括覆盖第三半导体芯片320的侧壁的第三子延伸部as3e。第三子延伸部as3e可为当挤压第三半导体芯片320时，在第三半导体芯片320外侧从第三非导电膜突出的固化的圆角。
依序堆叠的第一粘合层as1、第二粘合层as2、及第三粘合层as3可成一体地相互连接以形成单个粘合结构AS。粘合结构AS可包括覆盖堆叠结构SS的侧壁的延伸部ASe，且延伸部ASe可包括第一子延伸部as1e、第二子延伸部as2e、及第三子延伸部as3e。
在堆叠半导体芯片320之前可堆叠另外的半导体芯片。作为实例，根据本发明概念示例性实施例的堆叠结构SS可包括多于三个堆叠半导体芯片。作为另外一种选择，举例来说，可省略第二半导体芯片220。作为实例，根据本发明概念示例性实施例的堆叠结构SS可包括两个堆叠半导体芯片。
在根据本发明概念示例性实施例的制造半导体装置的方法中，可使用第一非导电膜140及第二非导电膜240将第一半导体芯片120、第二半导体芯片220及第三半导体芯片320堆叠并结合在封装衬底100上，且因此可在第一互连构件112、第二互连构件212及第三互连构件312之间获得相对精细的节距而不会在相互毗邻的第一互连构件112、第二互连构件212及第三互连构件312之间形成电短路。由第一非导电膜140及第二非导电膜240形成的粘合结构AS可用作实质上填充第一空间SP1、第二空间SP2及第三空间SP3的底部填充物，由此提高第一互连构件112、第二互连构件212及第三互连构件312的机械耐用性。
参照图9，可形成第一模制层500来覆盖堆叠结构SS。由于粘合结构AS可用作实质上填充第一空间SP1、第二空间SP2及第三空间SP3的底部填充物，因此可在不执行模塑底部填充物(molded under-fill)工艺的条件下形成第一模制层500。举例来说，可将第一模制层500形成为实质上完全覆盖第三半导体芯片320的第三无源表面320b。
第一模制层500可包含具有相对低的粘度及相对高的间隙填充性质的模制组合物，且可因此实质上填充堆叠结构SS之间的空间。因此，堆叠结构SS之间例如因粘合结构AS的延伸部ASe而形成的不规则的且相对窄的空间可得到填充。
参照图10，可切割第三半导体芯片320之间的第一模制层500以移除设置在第三半导体芯片320之间的空间中的延伸部ASe。作为实例，可移除延伸部ASe中的每一个延伸部ASe的一部分，且延伸部ASe的所移除的一部分可为第三子延伸部as3e。
作为实例，可使用第一刀片BL1在第三半导体芯片320之间进行切割。可将第三半导体芯片320之间的第一模制层500与各第三半导体芯片320之间的延伸部ASe一起移除。第一刀片BL1可具有第一宽度W1。举例来说，第一宽度W1可实质上相同于第三半导体芯片320之间的距离。通过移除第三半导体芯片320之间的第一模制层500及延伸部ASe，可界定第三半导体芯片320之间的第一凹陷区RS1。
在本发明概念的示例性实施例中，不需要移除第一半导体芯片120之间及第二半导体芯片220之间的延伸部ASe。在本发明概念的示例性实施例中，所述切割工艺可移除第一半导体芯片120之间及第二半导体芯片220之间的延伸部ASe的至少一部分。其余未被移除的第一模制层500可形成填充于各堆叠结构SS之间的第一模制图案505。
参照图11，可在其余的第一模制层500上形成第二模制层550。第二模制层550可填充第一凹陷区RS1。举例来说，第二模制层550可包含与第一模制层500的材料不同的材料。作为实例，第二模制层550可包含比第一模制层500中的含量多的无机物质且可包含比第一模制层500中的含量少的有机物质。因此，第二模制层550可具有比第一模制层500的热膨胀系数小的热膨胀系数。作为实例，第二模制层550的模制组合物可具有比第一模制层500高的无机含量，使得第二模制层550可具有相对高的粘度及相对差的间隙填充性质。然而，第一凹陷区RS1可具有实质上呈均匀形状的空间及相对宽的宽度，使得第二模制层550的模制组合物可填充第一凹陷区RS1。作为实例，第二模制层550可包含与第一模制层500相同的材料；然而，本发明概念的示例性实施例并非仅限于此。
参照图12，可将第二模制层550及第一模制层500平坦化，直至暴露出第三半导体芯片320的第三无源表面320b，且因此可形成第二模制图案555。第二模制图案555可实质上分别填充第一凹陷区RS1。第一模制层500可被实质上完全地从第三半导体芯片320上移除。
通过平坦化工艺，可使第三半导体芯片320的第三无源表面320b与第二模制图案555的顶表面实质上对齐。当第三无源表面320b暴露至第一半导体芯片120、第二半导体芯片220、及第三半导体芯片320的外部时，可将热量从第一半导体芯片120、第二半导体芯片220及第三半导体芯片320移除。
可通过从载体衬底CR与封装衬底100之间移除粘合模具MO来将载体衬底CR从封装衬底100分开。
参照图13，可对封装衬底100执行切割工艺以形成多个半导体封装。作为实例，可使用第二刀片BL2在封装衬底100的第一区RG1、第二区RG2及第三区RG3之间进行切割。第一区RG1、第二区RG2及第三区RG3可因此相互分离。所述切割工艺可切割各堆叠结构SS之间的第一模制图案505及第二模制图案555。通过切割工艺可将单个半导体封装形成为包括位于第一区RG1、第二区RG2及第三区RG3中的一个上的堆叠结构SS。第二刀片BL2可具有第二宽度W2。第二宽度W2可小于第一宽度W1。
图14是说明根据比较例的制造半导体装置的方法的剖视图。图15是说明图14所绘示的半导体封装的顶表面的平面图。
在制造半导体装置的方法中，可不从第三半导体芯片320之间移除延伸部ASe。堆叠结构SS可仅被第一模制图案505覆盖。粘合结构AS的延伸部ASe可设置在第三半导体芯片320与第一模制图案505之间。延伸部ASe可具有实质上与第三半导体芯片320的第三无源表面320b对齐的顶表面。作为实例，延伸部ASe的顶表面可在第三半导体芯片320与第一模制图案505之间暴露于外部。所暴露的延伸部ASe可在半导体封装的顶表面上显示出不规则的形状。
在根据本发明概念示例性实施例的制造半导体装置的方法中，粘合结构AS可不具有暴露于外部的延伸部ASe且可不在半导体封装的顶表面上显示出不规则的形状。半导体封装的上部部分及下部部分可分别包括第一模制图案505及第二模制图案555，第一模制图案505与第二模制图案555的材料可互不相同。作为实例，第二模制图案555可具有相对低的热膨胀系数，且因此可能会减少或消除半导体封装的由热量引起的翘曲。
以下将参照图13更详细地阐述根据本发明概念示例性实施例的半导体装置。
参照图13，在封装衬底100上可设置有堆叠结构SS。举例来说，封装衬底100可为印制电路板(PCB)。封装衬底100可具有包括外侧互连构件102(例如，焊料球)的底表面及包括连接焊盘104的顶表面。封装衬底100可包括至少一个通孔。
堆叠结构SS可包括可依序堆叠的第一半导体芯片120、第二半导体芯片220、及第三半导体芯片230。第一半导体芯片120可包括电连接至第一电路层122的第一通孔124，且第二半导体芯片220可包括电连接至第二电路层222的第二通孔224。第三半导体芯片320可不包括通孔；然而，本发明概念的示例性实施例并非仅限于此。在本发明概念的示例性实施例中，第一半导体芯片120、第二半导体芯片220及第三半导体芯片320可各自为存储器芯片。
作为实例，第一半导体芯片120、第二半导体芯片220及第三半导体芯片320可具有实质上相互相同的平坦形状及大小。第三半导体芯片320可具有比第一半导体芯片120及第二半导体芯片220大的厚度；然而，本发明概念的示例性实施例并非仅限于此。
如焊料球或焊料凸块等的第一互连构件112可设置在第一半导体芯片120的第一有源表面120a上。第一半导体芯片120可经由第一互连构件112电连接至封装衬底100。第一半导体芯片120可包括设置在第一半导体芯片120的第一无源表面120b上的第一背面垫132。第一背面垫132可电连接至第一通孔124。
如焊料球或焊料凸块等的第二互连构件212可设置在第二半导体芯片220的第二有源表面220a上。第二半导体芯片220可经由第二互连构件212电连接至第一半导体芯片120。第二半导体芯片220可包括设置在第二半导体芯片220的第二无源表面220b上的第二背面垫232。第二背面垫232可电连接至第二通孔224。
如焊料球或焊料凸块等的第三互连构件312可设置在第三半导体芯片320的第三有源表面320a上。第三半导体芯片320可经由第三互连构件312电连接至第二半导体芯片220。因此，封装衬底100与第一半导体芯片120、第二半导体芯片220及第三半导体芯片320可在垂直方向上相互电连接。
粘合结构AS可填充封装衬底100与第一半导体芯片120之间的第一空间SP1、第一半导体芯片120与第二半导体芯片220之间的第二空间SP2、以及第二半导体芯片220与第三半导体芯片320之间的第三空间SP3。粘合结构AS可将第一半导体芯片120、第二半导体芯片220及第三半导体芯片320结合至封装衬底100。粘合结构AS可填充于相互毗邻的第一互连构件112、第二互连构件212以及第三互连构件312之间，使得第一互连构件112、第二互连构件212及第三互连构件312可相互绝缘。
粘合结构AS可包括覆盖第一半导体芯片120的侧壁及第二半导体芯片220的侧壁的延伸部ASe。粘合结构AS的一部分可为从第一半导体芯片120的外侧及第二半导体芯片220的外侧向外突出的延伸部ASe。延伸部ASe可仅覆盖第一半导体芯片120的侧壁；然而，本发明概念的示例性实施例并非仅限于此。
封装衬底100可包括覆盖堆叠结构SS的第一模制图案505及第二模制图案555。第二模制图案555可设置在第一模制图案505上且可覆盖第三半导体芯片320的侧壁。第一模制图案505可覆盖延伸部ASe的侧壁。举例来说，第二模制图案555可具有比第一模制图案505的热膨胀系数小的热膨胀系数。因此，第二模制图案555可减少或消除半导体封装的由热量引起的翘曲。
第二模制图案555可具有与第三半导体芯片320的第三无源表面320b实质上对齐的顶表面。第三半导体芯片320的第三无源表面320b可因此被暴露至第一半导体芯片120、第二半导体芯片220及第三半导体芯片320的外部。因此，可移除由第一半导体芯片120、第二半导体芯片220及第三半导体芯片320产生的热量。
图16至图19是说明根据本发明概念某些示例性实施例的制造半导体装置的方法的剖视图。以下参照图16至图19阐述的技术特征可实质上相同于以上参照图1至图13所论述的技术特征，且因此可不再对其进行重复说明。
参照图16，可对所得结构(例如，参照图9所阐述的所得结构)执行切割工艺以移除设置在堆叠结构SS之间的空间中的延伸部ASe。作为实例，可使用第一刀片BL1在堆叠结构SS之间进行切割。所述切割工艺可被执行至局部地暴露出封装衬底100的顶表面为止。延伸部ASe可因此被从各堆叠结构SS之间实质上完全移除。作为另外一种选择，第一模制层500及延伸部ASe中的至少一个可局部地保留在堆叠结构SS之间；然而，本发明概念的示例性实施例并非仅限于此。
在所述切割工艺移除堆叠结构SS之间的第一模制层500及延伸部ASe时，可界定出第二凹陷区RS2。当切割工艺结束时，粘合结构AS的第一粘合层as1、第二粘合层as2、及第三粘合层as3可相互分离并在垂直方向上相互间隔开。
参照图17，第二模制层550可被形成为覆盖堆叠结构SS。第二模制层550可被形成为填充第二凹陷区RS2。第二凹陷区RS2可具有实质上均匀的形状及相对宽的宽度，使得第二模制层550的模制组合物可填充第二凹陷区RS2。
参照图18，可将第二模制层550及第一模制层500平坦化直至暴露出第三半导体芯片320的第三无源表面320b为止，且因此可形成第二模制图案555。可通过从载体衬底CR与封装衬底100之间移除粘合模具MO来将载体衬底CR从封装衬底100分开。
参照图19，可对封装衬底100执行切割工艺以形成多个半导体封装。可使用第二刀片BL2来执行切割工艺。
根据本发明概念的示例性实施例，可将粘合结构AS的延伸部ASe实质上完全移除。因此，粘合结构AS可不具有暴露于外部的延伸部ASe且可不在半导体封装的顶表面上显示出不规则的形状。第二模制图案555可具有相对低的热膨胀系数，且因此可减少或消除半导体封装的由热量引起的翘曲。
以下将参照图19更详细地阐述根据本发明概念示例性实施例的半导体装置。以下参照图19阐述的技术特征可实质上相同于以上参照图13论述的技术特征，且因此可不再对其进行重复说明。
参照图19，粘合结构AS可包括第一粘合层as1、第二粘合层as2、及第三粘合层as3。第一粘合层as1、第二粘合层as2、及第三粘合层as3可实质上分别填充第一空间SP1、第二空间SP2及第三空间SP3。第一粘合层as1、第二粘合层as2以及第三粘合层as3可相互分离并在垂直方向上相互间隔开。
封装衬底100可包括覆盖堆叠结构SS的第二模制图案555。举例来说，第二模制图案555可与第一半导体芯片120的侧壁、第二半导体芯片220的侧壁及第三半导体芯片320的侧壁直接接触。第二模制图案555可与第一粘合层as1的侧壁、第二粘合层as2的侧壁及第三粘合层as3的侧壁直接接触。
图20、图23、及图24是说明根据本发明概念某些示例性实施例的制造半导体装置的方法的剖视图。图21是说明根据本发明概念某些示例性实施例的湿蚀刻工艺的流程图。图22A至图22D是图20的区段N的放大剖视图。以下参照图20、图21、图22A、图22B、图22C、图22D、图23及图24阐述的技术特征可实质上相同于以上参照图1至图13所论述的技术特征，且因此可不再对其进行重复说明。
参照图20，可对所得结构(例如，参照图8所阐述的所得结构)执行湿蚀刻工艺(wetetch process，WE工艺)以移除设置在堆叠结构SS之间的空间中的延伸部ASe。作为实例，所述湿蚀刻工艺WE可包括向堆叠结构SS之间的空间中引入蚀刻溶液来对延伸部ASe进行选择性的湿蚀刻。延伸部ASe可因此被从堆叠结构SS之间实质上完全移除。作为另外一种选择，延伸部ASe可局部地保留在堆叠结构SS之间；然而，本发明概念的示例性实施例并非仅限于此。作为实例，不需要形成第一模制层500。
参照图20、图21及图22A，湿蚀刻工艺WE可包括施加碱性溶液以使粘合结构的延伸部膨胀(S110)。举例来说，湿蚀刻工艺WE可包括向堆叠结构SS之间的延伸部ASe上施加碱性溶液610。可经由堆叠结构SS之间的空间将碱性溶液610施加至延伸部ASe上。碱性溶液610可使延伸部ASe中包含的树脂膨胀。举例来说，碱性溶液610可包含氢氧化钠溶液。
参照图20、图21、及图22B，湿蚀刻工艺WE可包括施加氧化剂以分解延伸部中含有的树脂(S120)。举例来说，湿蚀刻工艺WE可包括向堆叠结构SS之间的延伸部ASe上施加氧化剂620。氧化剂620可有效地分解延伸部ASe中包含的膨胀的树脂。举例来说，氧化剂620可包含高锰酸钾。作为实例，可基于以下由反应式1给出的蚀刻原理来分解延伸部ASe。
[反应式1]
CH4+12MnO4 -+14OH-→CO3 2-+12MnO4 2-+9H2O+O2
2MnO4 2-+2H2O→MnO2+OH-+O2
参照图20、图21及图22C，湿蚀刻工艺WE可包括施加还原剂以将残留产物还原成水溶性(S130)。湿蚀刻工艺可包括向存留在堆叠结构SS之间的残留产物RP上施加还原剂630。在氧化剂620分解延伸部ASe中包含的树脂之后，可能存留有包含未反应的氧化剂620的残留产物RP。因此，可施加还原剂630来将残留产物RP还原成水溶性。举例来说，还原剂630可包含过氧化氢及/或羟胺，且残留产物RP可包含氧化锰。作为实例，可基于以下反应式2所表达的还原原理来将残留产物RP还原成水溶性的。
[反应式2]
MnO2+4H++2e-→Mn2++2H2O
H2O2→2H++2e-+O2
2NH2OH→4H++2H2O+2e-+N2
参照图20、图21、及图22D，湿蚀刻工艺WE可包括进行水洗以移除残留物(S140)。湿蚀刻工艺可包括执行水洗640以移除堆叠结构SS之间的残留物。由于在先前工艺中已将残留产物RP还原成水溶性，因此水洗640可实质上完全移除残留物。因此，可实质上完全移除延伸部ASe且粘合结构AS的第一粘合层as1、第二粘合层as2及第三粘合层as3可相互分离并在垂直方向上相互间隔开。由于可通过湿蚀刻工艺WE或各向同性蚀刻工艺来将延伸部ASe移除，因此可在第一粘合层as1、第二粘合层as2、及第三粘合层as3中的至少一个上形成凹陷侧壁。举例来说，在第三粘合层as3上可形成第三凹陷侧壁as3w。由于可执行湿蚀刻工艺WE来移除堆叠结构SS之间的延伸部ASe，因此可界定出第三凹陷区RS3。
参照图23，可形成第二模制层550来覆盖堆叠结构SS。第二模制层550可被形成为填充第三凹陷区RS3。第三凹陷区RS3可具有实质上均匀的形状及相对宽的宽度，使得第二模制层550的模制组成物可填充第三凹陷区RS3。
参照图24，可将第二模制层550平坦化直至暴露出第三半导体芯片320的第三无源表面320b，且因此可形成第二模制图案555。可通过从载体衬底CR与封装衬底100之间移除粘合模具MO来将载体衬底CR从封装衬底100分开。可对封装衬底100执行切割工艺以形成多个半导体封装。可使用第二刀片BL2来执行切割工艺。
根据本发明概念的示例性实施例，可实质上完全移除粘合结构AS的可暴露至外部的延伸部ASe。因此，粘合结构AS可不具有暴露于外部的延伸部ASe且可不在半导体封装的顶表面上显示出不规则的形状。还可简化粘合结构AS的延伸部ASe的移除，这是因为不需要形成第一模制层500。第二模制图案555可具有相对低的热膨胀系数，且因此可减少或消除半导体封装的由热量引起的翘曲。
以下将参照图24更详细地阐述根据本发明概念示例性实施例的半导体装置。参照图24阐述的技术特征可实质上相同于参照图13阐述的技术特征，且因此可不再对其进行重复说明。
再次参照图24，粘合结构AS可包括第一粘合层as1、第二粘合层as2及第三粘合层as3。第一粘合层as1、第二粘合层as2及第三粘合层as3可分别实质上填充第一空间SP1、第二空间SP2及第三空间SP3。第一粘合层as1、第二粘合层as2及第三粘合层as3可相互分离并在垂直方向上相互间隔开。
第一粘合层as1、第二粘合层as2及第三粘合层as3可分别包括第一凹陷侧壁as1w、第二凹陷侧壁as2w及第三凹陷侧壁as3w。第一凹陷侧壁as1w、第二凹陷侧壁as2w及第三凹陷侧壁as3w可形成粘合结构AS的凹陷侧壁ASw。第一凹陷侧壁as1w、第二凹陷侧壁as2w及第三凹陷侧壁as3w可分别朝第一互连构件112、第二互连构件212及第三互连构件312凹陷。
封装衬底100可包括覆盖堆叠结构SS的第二模制图案555。举例来说，第二模制图案555可直接接触第一半导体芯片120的侧壁、第二半导体芯片220的侧壁及第三半导体芯片320的侧壁。第二模制图案555可直接接触第一凹陷侧壁as1w、第二凹陷侧壁as2w及第三凹陷侧壁as3w。第二模制图案555与粘合结构AS可包含互不相同的材料。举例来说，第二模制图案555可具有与粘合结构AS的热膨胀系数不同的热膨胀系数。
在制造根据本发明概念的示例性实施例的半导体装置的方法中，可有效地移除覆盖半导体芯片的粘合结构的延伸部，此不需要毁坏半导体封装的外观。模制层可具有相对低的热膨胀系数，且因此可减少或消除半导体封装的翘曲。
尽管已参照本发明概念的示例性实施例特别示出并阐述了本发明概念，然而所属领域的普通技术人员将理解，在不背离本发明概念的精神及范围的条件下，可在本文中作出形式及细节上的各种改变。

Claims (25)

1.一种制造半导体装置的方法，其特征在于，包括：
在封装衬底上堆叠水平相互间隔开的多个第一半导体芯片，其中所述多个第一半导体芯片中的每一个包括面对所述封装衬底的第一粘合膜；
在所述多个第一半导体芯片上分别堆叠水平相互间隔开的多个第二半导体芯片，其中所述多个第二半导体芯片中的每一个包括面对所述第一半导体芯片的第二粘合膜；
挤压所述第一粘合膜及所述第二粘合膜以形成粘合结构，其中所述粘合结构包括设置在所述第一半导体芯片的多个侧壁上及所述第二半导体芯片的多个侧壁上的延伸部；
从所述多个第二半导体芯片的所述多个侧壁移除所述延伸部；
形成覆盖所述多个第一半导体芯片及所述多个第二半导体芯片的第一模制层；以及
对所述多个第一半导体芯片之间与所述多个第二半导体芯片之间的所述封装衬底执行切割工艺，以形成多个半导体封装，所述多个半导体封装各自包括所述多个第一半导体芯片中的至少一个及所述多个第二半导体芯片中的至少一个。
2.根据权利要求1所述的制造半导体装置的方法，其特征在于，形成所述粘合结构包括：
在堆叠所述第一半导体芯片的同时，挤压所述第一粘合膜，以形成第一粘合层；以及
在堆叠所述第二半导体芯片的同时，挤压所述第二粘合膜，以形成第二粘合层。
3.根据权利要求1所述的制造半导体装置的方法，其特征在于，所述多个第一半导体芯片中的每一个包括至少一个通孔。
4.根据权利要求3所述的制造半导体装置的方法，其特征在于，所述多个第二半导体芯片中的每一个还包括至少一个互连构件，且
其中当堆叠所述第二半导体芯片时，所述至少一个互连构件电连接至所述至少一个通孔。
5.根据权利要求1所述的制造半导体装置的方法，其特征在于，在堆叠所述第一半导体芯片的时间之前，所述第一粘合膜具有第一厚度，且
其中在堆叠所述第一半导体芯片的时间之后，在所述封装衬底与所述第一半导体芯片的面对所述封装衬底的表面之间获得第一距离，所述第一厚度大于所述第一距离。
6.根据权利要求1所述的制造半导体装置的方法，其特征在于，还包括将所述第一模制层平坦化，直至暴露出所述多个第二半导体芯片的多个顶表面，以形成填充所述多个第二半导体芯片之间的多个空间的多个第一模制图案。
7.根据权利要求1所述的制造半导体装置的方法，其特征在于，在移除所述延伸部之前，还包括形成覆盖所述多个第一半导体芯片及所述多个第二半导体芯片的第二模制层，
其中所述第二模制层填充相互毗邻的所述多个第二半导体芯片之间的空间。
8.根据权利要求7所述的制造半导体装置的方法，其特征在于，移除所述延伸部包括切割相互毗邻的所述多个第二半导体芯片之间的所述第二模制层。
9.根据权利要求8所述的制造半导体装置的方法，其特征在于，在所述封装衬底的所述切割工艺中使用的刀片的宽度小于在所述第二模制层的所述切割工艺中使用的刀片的宽度。
10.根据权利要求7所述的制造半导体装置的方法，其特征在于，所述第一模制层具有比所述第二模制层的热膨胀系数小的热膨胀系数。
11.根据权利要求7所述的制造半导体装置的方法，其特征在于，所述延伸部包括：
第一子延伸部，设置在所述第一半导体芯片的所述多个侧壁上；以及
第二子延伸部，设置在所述第二半导体芯片的所述多个侧壁上，且
其中移除所述延伸部包括切割相互毗邻的所述多个第二半导体芯片之间的所述第二模制层，以移除所述第二子延伸部，且
其中在移除所述第二模制层的同时，形成第二模制图案来填充相互毗邻的所述多个第一半导体芯片之间的空间。
12.根据权利要求7所述的制造半导体装置的方法，其特征在于，所述延伸部包括：
第一子延伸部，设置在所述第一半导体芯片的所述多个侧壁上；以及
第二子延伸部，设置在所述第二半导体芯片的所述多个侧壁上，且
其中移除所述延伸部包括通过切割相互毗邻的所述多个第二半导体芯片之间及相互毗邻的所述多个第一半导体芯片之间的所述第二模制层来移除所述第一子延伸部及所述第二子延伸部。
13.根据权利要求1所述的制造半导体装置的方法，其特征在于，移除所述延伸部包括通过向相互毗邻的所述多个第二半导体芯片之间的空间中引入蚀刻溶液来对所述延伸部进行湿蚀刻。
14.根据权利要求13所述的制造半导体装置的方法，其特征在于，所述延伸部被移除使得在所述粘合结构上形成至少一个凹陷侧壁。
15.根据权利要求13所述的制造半导体装置的方法，其特征在于，对所述延伸部进行湿蚀刻包括：
对所述延伸部施加碱性溶液；以及
对所述延伸部施加氧化剂，以分解所述延伸部中包含的树脂。
16.一种制造半导体装置的方法，其特征在于，包括：
在封装衬底上形成水平相互间隔开的多个堆叠结构，所述多个堆叠结构中的每一个包括垂直堆叠的多个半导体芯片；
形成分别填充所述多个堆叠结构中毗邻的多个堆叠结构之间的多个空间的多个粘合结构；以及
移除所述毗邻的多个堆叠结构之间的所述粘合结构的至少一部分，
其中形成所述多个堆叠结构及所述多个粘合结构包括对所述多个半导体芯片依序进行堆叠及挤压，所述多个半导体芯片各自包括设置在所述半导体芯片的面对所述封装衬底的表面上的粘合膜。
17.根据权利要求16所述的制造半导体装置的方法，其特征在于，当堆叠所述多个半导体芯片时挤压所述粘合膜，使得在所述多个半导体芯片中的每一个半导体芯片的多个侧壁上形成圆角。
18.根据权利要求16所述的制造半导体装置的方法，其特征在于，所述多个半导体芯片中的至少一个半导体芯片包括：
至少一个通孔，穿透所述至少一个半导体芯片；以及
至少一个互连构件，设置在所述至少一个半导体芯片的表面上且电连接至所述至少一个通孔，
其中所述粘合膜设置在所述互连构件上。
19.根据权利要求16所述的制造半导体装置的方法，其特征在于，还包括：
形成覆盖所述多个粘合结构的模制层；以及
切割所述多个粘合结构之间的所述模制层。
20.根据权利要求16所述的制造半导体装置的方法，其特征在于，移除所述粘合结构的所述至少一部分包括通过在所述多个堆叠结构之间引入蚀刻溶液来对所述粘合结构进行湿蚀刻。
21.一种制造半导体装置的方法，其特征在于，包括：
在封装衬底上堆叠多个第一半导体芯片，其中所述多个第一半导体芯片在所述封装衬底上相互间隔开，且其中所述多个第一半导体芯片中的每一个包括第一粘合膜；
将多个第二半导体芯片中的第二半导体芯片分别堆叠在所述多个第一半导体芯片中的对应一个第一半导体芯片上，其中所述多个第二半导体芯片中的每一个包括第二粘合膜；
将多个第三半导体芯片中的第三半导体芯片分别堆叠在所述多个第二半导体芯片中的对应一个第二半导体芯片上，其中所述多个第三半导体芯片中的每一个包括第三粘合膜，
其中堆叠所述多个第一半导体芯片、所述多个第二半导体芯片及所述多个第三半导体芯片而形成在所述封装衬底上相互间隔开的多个堆叠结构，所述多个堆叠结构中的每一个包括粘合结构，所述粘合结构包括所述第一粘合膜、所述第二粘合膜及所述第三粘合膜，且其中所述粘合结构包括设置在所述第一半导体芯片、所述第二半导体芯片及所述第三半导体芯片中的相应者的多个侧壁上的多个延伸部；
在所述多个第三半导体芯片的多个上表面上以及在位于所述多个堆叠结构中毗邻的多个堆叠结构之间的多个空间中的所述多个延伸部上形成第一模制层；
移除所述多个第三半导体芯片中毗邻的多个第三半导体芯片之间的所述第一模制层；
在通过移除所述多个第三半导体芯片中毗邻的多个第三半导体芯片之间的所述第一模制层而形成的多个空间的每一个中形成第二模制层；以及
通过切穿所述第一模制层及所述第二模制层并切穿所述多个堆叠结构中毗邻的多个堆叠结构之间的所述封装衬底，而将所述多个堆叠结构中的每一个相互分离。
22.根据权利要求21所述的制造半导体装置的方法，其特征在于，所述粘合结构中的所述多个延伸部是通过挤压所述第一半导体芯片、所述第二半导体芯片、及所述第三半导体芯片中的每一个来形成。
23.根据权利要求21所述的制造半导体装置的方法，其特征在于，所述多个堆叠结构中的每一个堆叠结构的所述第一半导体芯片、所述第二半导体芯片、及所述第三半导体芯片相互电连接。
24.根据权利要求23所述的制造半导体装置的方法，其特征在于，所述多个堆叠结构中的每一个堆叠结构的所述第一半导体芯片、所述第二半导体芯片、及所述第三半导体芯片电连接至设置在所述封装衬底上的多个连接焊盘。
25.根据权利要求21所述的制造半导体装置的方法，其特征在于，所述第一模制层具有比所述第二模制层的热膨胀系数小的热膨胀系数。
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