CN110034075A - 使用具有导电性的模制材料的电路封装 - Google Patents
使用具有导电性的模制材料的电路封装 Download PDFInfo
- Publication number
- CN110034075A CN110034075A CN201811483008.2A CN201811483008A CN110034075A CN 110034075 A CN110034075 A CN 110034075A CN 201811483008 A CN201811483008 A CN 201811483008A CN 110034075 A CN110034075 A CN 110034075A
- Authority
- CN
- China
- Prior art keywords
- circuit package
- substrate
- power supply
- filler
- supply pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012778 molding material Substances 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 117
- 238000000465 moulding Methods 0.000 claims abstract description 106
- 239000000945 filler Substances 0.000 claims description 88
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 239000002184 metal Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 45
- 239000011248 coating agent Substances 0.000 claims description 33
- 238000000576 coating method Methods 0.000 claims description 33
- 239000000696 magnetic material Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 description 57
- 239000010408 film Substances 0.000 description 38
- 238000000034 method Methods 0.000 description 34
- 239000000956 alloy Substances 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 239000002131 composite material Substances 0.000 description 14
- 238000003466 welding Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910045601 alloy Inorganic materials 0.000 description 13
- 239000003795 chemical substances by application Substances 0.000 description 13
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 10
- 229910000859 α-Fe Inorganic materials 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000001723 curing Methods 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910001374 Invar Inorganic materials 0.000 description 6
- 239000011230 binding agent Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000011777 magnesium Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000002156 mixing Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- -1 phenolic aldehyde Chemical class 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 5
- 229910052749 magnesium Inorganic materials 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000003252 repetitive effect Effects 0.000 description 5
- 229910052725 zinc Inorganic materials 0.000 description 5
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 4
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 4
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 4
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 4
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 4
- TZCXTZWJZNENPQ-UHFFFAOYSA-L barium sulfate Chemical compound [Ba+2].[O-]S([O-])(=O)=O TZCXTZWJZNENPQ-UHFFFAOYSA-L 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 238000001548 drop coating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 238000013007 heat curing Methods 0.000 description 4
- 229920006015 heat resistant resin Polymers 0.000 description 4
- 238000001746 injection moulding Methods 0.000 description 4
- 239000012762 magnetic filler Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- 239000011701 zinc Substances 0.000 description 4
- 229910017061 Fe Co Inorganic materials 0.000 description 3
- 229910017082 Fe-Si Inorganic materials 0.000 description 3
- 229910017133 Fe—Si Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 235000010290 biphenyl Nutrition 0.000 description 3
- 239000004305 biphenyl Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910017518 Cu Zn Inorganic materials 0.000 description 2
- 229910017752 Cu-Zn Inorganic materials 0.000 description 2
- 229910017943 Cu—Zn Inorganic materials 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- 229910018605 Ni—Zn Inorganic materials 0.000 description 2
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 2
- 229910021502 aluminium hydroxide Inorganic materials 0.000 description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229910000019 calcium carbonate Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004927 clay Substances 0.000 description 2
- 229910052570 clay Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000009689 gas atomisation Methods 0.000 description 2
- 150000002460 imidazoles Chemical class 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- VTHJTEIRLNZDEV-UHFFFAOYSA-L magnesium dihydroxide Chemical compound [OH-].[OH-].[Mg+2] VTHJTEIRLNZDEV-UHFFFAOYSA-L 0.000 description 2
- 239000000347 magnesium hydroxide Substances 0.000 description 2
- 229910001862 magnesium hydroxide Inorganic materials 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010525 oxidative degradation reaction Methods 0.000 description 2
- 229910000889 permalloy Inorganic materials 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000003756 stirring Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000454 talc Substances 0.000 description 2
- 229910052623 talc Inorganic materials 0.000 description 2
- 235000012222 talc Nutrition 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- HUWSZNZAROKDRZ-RRLWZMAJSA-N (3r,4r)-3-azaniumyl-5-[[(2s,3r)-1-[(2s)-2,3-dicarboxypyrrolidin-1-yl]-3-methyl-1-oxopentan-2-yl]amino]-5-oxo-4-sulfanylpentane-1-sulfonate Chemical compound OS(=O)(=O)CC[C@@H](N)[C@@H](S)C(=O)N[C@@H]([C@H](C)CC)C(=O)N1CCC(C(O)=O)[C@H]1C(O)=O HUWSZNZAROKDRZ-RRLWZMAJSA-N 0.000 description 1
- HECLRDQVFMWTQS-RGOKHQFPSA-N 1755-01-7 Chemical compound C1[C@H]2[C@@H]3CC=C[C@@H]3[C@@H]1C=C2 HECLRDQVFMWTQS-RGOKHQFPSA-N 0.000 description 1
- OAYXUHPQHDHDDZ-UHFFFAOYSA-N 2-(2-butoxyethoxy)ethanol Chemical compound CCCCOCCOCCO OAYXUHPQHDHDDZ-UHFFFAOYSA-N 0.000 description 1
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229930185605 Bisphenol Natural products 0.000 description 1
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910019819 Cr—Si Inorganic materials 0.000 description 1
- 239000004641 Diallyl-phthalate Substances 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910017060 Fe Cr Inorganic materials 0.000 description 1
- 229910002544 Fe-Cr Inorganic materials 0.000 description 1
- UQSXHKLRYXJYBZ-UHFFFAOYSA-N Iron oxide Chemical compound [Fe]=O UQSXHKLRYXJYBZ-UHFFFAOYSA-N 0.000 description 1
- 239000002841 Lewis acid Substances 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003296 Ni-Mo Inorganic materials 0.000 description 1
- 229910003962 NiZn Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 125000002252 acyl group Chemical group 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 150000004703 alkoxides Chemical class 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229920003180 amino resin Polymers 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910000410 antimony oxide Inorganic materials 0.000 description 1
- 150000004984 aromatic diamines Chemical class 0.000 description 1
- 238000000889 atomisation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 125000002619 bicyclic group Chemical group 0.000 description 1
- QUDWYFHPNIMBFC-UHFFFAOYSA-N bis(prop-2-enyl) benzene-1,2-dicarboxylate Chemical compound C=CCOC(=O)C1=CC=CC=C1C(=O)OCC=C QUDWYFHPNIMBFC-UHFFFAOYSA-N 0.000 description 1
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- UPHIPHFJVNKLMR-UHFFFAOYSA-N chromium iron Chemical compound [Cr].[Fe] UPHIPHFJVNKLMR-UHFFFAOYSA-N 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 125000000853 cresyl group Chemical class C1(=CC=C(C=C1)C)* 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000975 dye Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- MTRJKZUDDJZTLA-UHFFFAOYSA-N iron yttrium Chemical class [Fe].[Y] MTRJKZUDDJZTLA-UHFFFAOYSA-N 0.000 description 1
- 150000007517 lewis acids Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 description 1
- 125000000951 phenoxy group Chemical group [H]C1=C([H])C([H])=C(O*)C([H])=C1[H] 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920005749 polyurethane resin Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 229910000815 supermalloy Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 150000003512 tertiary amines Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009692 water atomization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1205—Capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供一种使用具有导电性的模制材料的电路封装。本说明书中公开的电路封装具备具有电源图案的基板、和在上述基板的表面搭载的电子部件、和以将上述电子部件嵌入的方式覆盖上述基板的上述表面、具有导电性的模制部件。上述电源图案包括在上述基板的上述表面露出的第一电源图案,上述模制部件与上述第一电源图案相接。
Description
技术领域
本发明涉及电路封装,特别涉及使用具有导电性的模制材料的电路封装。
背景技术
近年来,智能手机等电子机器具有采用高性能的无线通信电路和数字芯片、使用的半导体IC的工作频率也上升的倾向。进而,预测具有将多个半导体IC用最短配线连接的2.5D结构或3D结构的系统级封装(SIP)化加快,电源系统电路的模块化今后也会逐渐增加。进而,预测将多个电子部件(电感器、电容器、电阻、滤波器等被动部件、晶体管、二极管等主动部件、半导体IC等集成电路部件、以及其他电路结构所需的部件的总称)模块化而成的电路模块今后也会越发增加,这些的总称即电路封装因智能手机等电子机器的高性能化和小型化、薄型化而具有高密度安装的倾向。这些倾向另一方面表示噪声引起的误动作和电磁干扰变得显著,用现有的噪声对策难以防止误动作和电磁干扰。因此,近年来,电路封装的自屏蔽化有所进展,提出了用导电膏或镀覆或溅射法进行的电磁屏蔽并实用化,但今后要求更高的屏蔽特性。
为了实现这一点,日本特开昭59-132196号公报中公开了用磁性模制树脂对电路进行模制,并且用金属壳体覆盖整体,由此提高了屏蔽性的电路封装。
但是,日本特开昭59-132196号公报中记载的电路封装中,因为用金属壳体覆盖整体,所以难以实现高度降低。另外,因为在金属壳体上设置了多个孔,并且金属壳体并未与基板的接地图案等连接,所以不能够得到充分的屏蔽效果。
发明内容
从而,本发明的目的在于提供一种能够实现高度降低、同时得到较高的屏蔽特性的电路封装。
本发明的电路封装具备:基板,其具有电源图案;电子部件,其搭载在上述基板的表面;和模制部件,其以将上述电子部件嵌入的方式覆盖上述基板的上述表面,并具有导电性;上述电源图案包括在上述基板的上述表面露出的第一电源图案;上述模制部件与上述第一电源图案相接。
根据本发明,因为模制部件具有导电性,所以能够通过模制部件自身得到电磁屏蔽功能。
本发明中,上述第一电源图案在上述基板的上述表面中所占的比例可以是2%以上,也可以是8%以上。通过增大第一电源图案在基板的表面中所占的比例,能够提高屏蔽。
本发明中,上述第一电源图案可以在上述基板的上述表面的至少一个角部配置,也可以在至少两个角部配置。该情况下,上述两个角部也可以是位于对角位置的。这样,如果将第一电源图案配置在基板的角部,能够容易地避免第一电源图案与其他配线图案的干涉。
本发明中,上述第一电源图案可以沿上述基板的上述表面的至少一条边配置,也可以沿至少两条边配置。该情况下,上述两条边可以相互相对。这样,如果使第一电源图案沿基板的边配置,能够容易地避免第一电源图案与其他配线图案的干涉。
本发明中,也可以是上述电源图案包括在上述基板的侧面露出的第二电源图案,上述模制部件进而与上述第二电源图案相接。由此,能够使模制部件的电位更加稳定。
本发明中,上述基板的上述侧面包括侧面上部、和与上述侧面上部相比更突出的侧面下部,上述第二电源图案在上述基板的上述侧面上部露出,上述模制部件也可以不覆盖上述基板的上述侧面下部,而覆盖上述基板的上述侧面上部。由此,能够在使基板单片化之前,将模制部件与在基板的侧面露出的第二电源图案连接。
本发明的电路封装可以进而具备覆盖上述模制部件、导电性比上述模制部件更高的金属膜。由此,能够进一步提高电磁屏蔽特性。
本发明中,上述模制部件包含树脂材料、和与上述树脂材料混合的第一填料,上述第一填料的表面可以被导电性比上述第一填料更高的金属涂层覆盖。由此,因为模制部件具有导电性和磁性,所以能够通过模制部件自身得到电磁屏蔽功能。特别是,如果使用磁性材料作为第一填料,则能够得到同时具有电磁屏蔽功能和磁屏蔽功能的复合屏蔽结构。
本发明的电路封装可以进而具备覆盖上述模制部件、磁导率比上述模制部件更高的磁性膜。由此,能够进一步提高磁屏蔽特性。
本发明中,上述模制部件可以进而包含比上述第一填料更小的第二填料。该情况下,上述第二填料的表面可以被金属涂层覆盖。由此,能够使模制部件的体积电阻进一步降低。
本发明中,上述第二填料可以由磁性材料构成,也可以由导电性材料构成,也可以由绝缘材料构成。
本发明中,上述第一填料可以由Fe中含有32~39重量%的以Ni为主成分的金属材料的材料构成。由此,能够使模制部件的热膨胀系数大幅减小,例如成为15ppm/℃以下。因此,能够防止基板的弯曲、模制材料的界面剥离、模制材料的裂纹等。
本发明的电路封装可以进而具备使上述电子部件及其端子电极与上述模制部件相互绝缘的绝缘涂层。由此,能够防止电子部件与模制部件的短路不良。
附图说明
本发明的上述特征及效果根据以下的附图以及附图所涉及的优选实施方式的说明会变得更加清楚。
图1是表示本发明的第一实施方式的电路封装的结构的截面图;
图2是表示图1所示的基板的表面的示意性的平面图;
图3~图7是用于说明图1所示的电路封装的制造方法的工序图;
图8是表示基板的表面上的电源图案的布局的第一例的示意性的平面图;
图9是表示基板的表面上的电源图案的布局的第二例的示意性的平面图;
图10是表示基板的表面上的电源图案的布局的第三例的示意性的平面图;
图11是表示基板的表面上的电源图案的布局的第四例的示意性的平面图;
图12是表示基板的表面上的电源图案的布局的第五例的示意性的平面图;
图13是表示基板的表面上的电源图案的布局的第六例的示意性的平面图;
图14是用于说明第一填料的结构的截面图;
图15A~图15C是用于说明第二填料的结构的截面图;
图16是表示本发明的第二实施方式的电路封装的结构的截面图;
图17是表示本发明的第三实施方式的电路封装的结构的截面图;
图18是表示本发明的第四实施方式的电路封装的结构的截面图;
图19是表示本发明的第五实施方式的电路封装的结构的截面图;
图20是表示本发明的第五实施方式的变形例的电路封装的结构的截面图;
图21是表示本发明的第六实施方式的电路封装的结构的截面图。
图22是表示实施例的测定结果的曲线图。
具体实施方式
本发明的优选实施方式将根据附图在下文详细说明。
<第一实施方式>
图1是表示本发明的第一实施方式的电路封装11的结构的截面图。
如图1所示,本实施方式的电路封装11具备基板20、和在基板20上搭载的多个电子部件31、32、和以将电子部件31、32嵌入的方式覆盖基板20的表面21的、具有导电性的复合模制部件40。
对于本实施方式的电路封装11的种类不特别限定,例如可以列举对高频信号进行处理的高频模块、进行电源控制的电源模块、具有2.5D结构或3D结构的系统级封装(SIP)、无线通信用或数字电路用半导体封装等。图1中仅图示了2个电子部件31、32,但实际上内置了更多的电子部件。
基板20具有在内部嵌入了多条配线的双面和多层配线结构,可以是FR-4、FR-5、BT、氰酸酯、酚醛、酰亚胺等热固化性树脂基材的有机基板、液晶聚合物等热塑性树脂基材的有机基板、LTCC基板、HTCC基板、柔性基板等任意的种类。本实施方式中基板20是4层结构,具有在基板20的表面21和背面22形成的配线层、和在内部嵌入的2层配线层。在基板20的表面21形成了多个焊盘图案23。焊盘图案23是用于与电子部件31、32连接的内部电极,两者经由焊料24(或导电膏)电连接并且机械连接。作为一例,电子部件31是控制器等半导体芯片,电子部件32是电容器或线圈等被动部件。电子部件的一部分(例如薄型化的半导体芯片等)也可以嵌入基板20中。
焊盘图案23经由在基板20的内部形成的内部配线25与在基板20的背面22形成的外部端子26连接。实际使用时,电路封装11安装在未图示的母板等上,将母板上的焊盘图案与电路封装11的外部端子26电连接。作为构成焊盘图案23、内部配线25和外部端子26的导体的材料,可以是铜、银、金、镍、铬、铝、钯、铟等金属或其金属合金也可以是用树脂或玻璃作为粘结剂的导电材料,基板20是有机基板或柔性基板的情况下,从成本和电导率等观点来看优选使用铜、银。作为这些导电材料的形成方法,能够使用印刷、镀覆、贴箔、溅射、蒸镀、喷墨等方法。另外,也可以在形成的焊盘图案23上通过镀覆或溅射、蒸镀等方法形成Au、Pd、Ag、Sn等低电阻金属,或者形成Cu-OSP等防氧化膜。
电子部件31、32及其端子电极和焊料24被绝缘涂层51、52覆盖,由此与复合模制部件40绝缘。图1所示的例子中,在电子部件31与基板20之间设置有绝缘涂层51,但也可以以覆盖电子部件31的整体的方式设置绝缘涂层51。电子部件32整体被绝缘涂层52覆盖。
如图1和图2所示,从焊盘图案23引出的电源图案23G不被绝缘涂层51、52覆盖而是露出,与复合模制部件40接触。电源图案23G典型而言是被赋予接地电位的接地图案,但只要是被赋予固定电位的图案即可,不限定于接地图案。
复合模制部件40以将电子部件31、32嵌入的方式覆盖基板20的表面21地设置。复合模制部件40与一般的模制部件不同,具有导电性。由此,在作为模制部件的通常的功能之外,也起到电磁屏蔽的作用。本实施方式中,复合模制部件40的侧面42与基板20的侧面27构成同一平面。对于复合模制部件40的详情在后文中叙述,优选其由与现有的磁性模制部件相比热膨胀系数非常小(例如15ppm/℃以下)的复合材料构成。
电源图案23G在基板20的表面21中所占的比例越大,屏蔽特性越是提高。这是因为电源图案23G在基板20的表面21中所占的比例越大,复合模制部件40的电位越稳定。考虑这一点时,优选电源图案23G在基板20的表面21中所占的比例为2%以上。另一方面,电源图案23G的占有率增加时,基板20的表面21上能够形成其他配线图案的面积减少。考虑这一点时,优选电源图案23G在基板20的表面21中所占的比率为30%以下。
接着,对本实施方式的电路封装11的制造方法进行说明。
图3~图7是用于说明电路封装11的制造方法的工序图。
首先,如图3所示,准备具有多层配线结构的集合基板20A。在集合基板20A的表面21形成了多个焊盘图案23和电源图案23G,在集合基板20A的背面22形成了多个外部端子26。另外,在集合基板20A的内层形成了多条内部配线25。另外,图3~图6所示的虚线a指的是在之后的划片工序中要切断的部分。
接着,如图3所示,以与焊盘图案23连接的方式在集合基板20A的表面21搭载多个电子部件31、32。具体而言,对焊盘图案23上供给焊料24之后,搭载电子部件31、32,通过进行回流焊而将电子部件31、32与焊盘图案23连接即可。
接着,如图4所示,用绝缘涂层51、52覆盖电子部件31、32、电子部件31、32的端子电极和焊料24。此时,需要电源图案23G的至少一部分成为不被绝缘涂层51、52覆盖而是露出的状态。
接着,如图5所示,以将电子部件31、32嵌入的方式用模制部件40覆盖集合基板20A的表面21。作为模制部件40的形成方法,能够使用基于传递成型、压缩成型、注塑成型、浇注、真空浇注、滴涂(dispense)、缝隙喷嘴的方法等。之后,如图6所示,通过对模制部件40的顶面进行研磨,而调整模制部件40的厚度。对于复合模制部件40的厚度不特别限定,优选包括电子部件31、32的所有电子部件中、最高的电子部件的上部的复合模制部件40的厚度为50μm以上,进而优选为100μm以上。由此,能够使复合模制部件40的体积电阻率充分小。但是,本发明中,并非必须对复合模制部件40的顶面进行研磨。
然后,如图7所示,通过沿虚线a将集合基板20A切断而使基板20单片化时,本实施方式的电路封装11完成。
这样,本实施方式的电路封装11中,因为复合模制部件40具有导电性,所以复合模制部件40自身起到电磁屏蔽的作用。由此,电子部件31、32发出的电磁波或从外部传播来的电磁波在复合模制部件40的内部被变换为电流,能够经由电源图案23G流向外部。而且,本实施方式中,因为电源图案23G在基板20的表面21露出,所以仅以覆盖基板20的表面21的方式形成复合模制部件40,就能够对复合模制部件40赋予固定电位。
另外,图2所示的例子中,从焊盘图案23引出的电源图案23G与复合模制部件40相接,但基板20的表面21上电源图案23G与焊盘图案23并非必须是一体的。从而,也可以设置与焊盘图案23独立的电源图案23G。另外,对于电源图案23G在基板20的表面21上的位置并不特别限定。例如也可以如图8所示,将电源图案23G配置在基板20的表面21的角部附近。图8所示的例子中,在基板20的表面21的中央部搭载电子部件33,在基板20的表面21的位于对角位置的2个角部附近配置了电源图案23G。另外,也可以如图9所示,在基板20的表面21的所有角部附近都配置电源图案23G。基板20的表面21的角部附近与中央区域相比、配线图案的形成密度更低的情况较多,所以通过在该部分配置电源图案23G,能够将面积的开销(overhead)抑制为最低限度。
另外,也可以如图10所示,沿基板20的表面21的一条边配置电源图案23G。基板20的表面21的外周附近与中央区域相比、配线图案的形成密度更低的情况较多,所以通过在该部分配置电源图案23G,能够将面积的开销抑制为最低限度。而且,与将电源图案23G配置在角部附近的情况相比,能够充分确保电源图案23G的面积。电源图案23G的面积不足的情况下,也可以如图11所示地,沿相对的2条边配置电源图案23G,也可以如图12所示,沿邻接的2条边配置电源图案23G,也可以如图13所示,沿所有的边配置电源图案23G。
接着,对构成复合模制部件40的模制材料详细地进行说明。
构成模制部件40的模制材料与一般的模制材料不同,具有导电性。而且,复合模制部件40因为与电源图案23G连接,所以被赋予接地电位等固定电位。由此,能够使复合模制部件40自身具有电磁屏蔽功能。为了充分发挥电磁屏蔽效果,优选导电性模制部件40的体积电阻率为1×10-4Ω·cm以下。
复合模制部件40包含粘结剂、和第一填料。粘结剂并不特别限定,优选其以热固化性树脂材料为主成分。具体而言,优选以环氧树脂、酚醛树脂、聚氨酯树脂、硅酮树脂或酰亚胺树脂为主成分,进而优选使用环氧树脂或酚醛树脂类的半导体密封材料中使用的主剂和固化剂。
最优选的是末端具有反应性的环氧基的环氧树脂,能够与各种固化剂和固化促进剂组合。作为环氧树脂的例子,可以列举双酚A型、双酚F型、苯氧基、萘、多官能型(双环戊二烯型等)、联苯型(二官能型)和特殊结构型,能够低热膨胀化的联苯、萘、双环戊二烯型等是有用的。作为固化剂或固化促进剂的例子,可以列举胺类化合物脂环族二胺、芳香族二胺、其他胺类(咪唑、叔胺)、酸酐类化合物(主要是高温固化剂)、酚醛树脂(酚醛清漆型、甲酚酚醛清漆型等)、氨基树脂、双氰胺、路易斯酸配位化合物。材料的搅拌方法适当使用捏合机或三辊研磨机、搅拌机等公知的方法即可。
图14是表示第一填料F1的一例的截面图。第一填料F1的中位粒径(D50)为d1,优选对其表面施加导电性比第一填料F1更高的金属涂层M。如果对第一填料F1的表面施加金属涂层M,则能够使复合模制部件40的体积电阻进一步低电阻化。作为金属涂层M的材料,可以列举以Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu为主成分的材料,在这些之中优选使用难以氧化劣化、电阻率低的Ag、Au。另外,为了使复合模制部件40的体积电阻进一步低电阻化,金属涂层M的电阻率优选为5×10-6Ω·cm以下。在第一填料F1上形成的金属涂层M的厚度优选为1~3000nm的范围。进而,施加了金属涂层M的第一填料F1的在粉体状态下的体积电阻率优选在施加了25MPa的压强的状态下为1×10-3Ω·cm以下。
对于第一填料F1的材料不特别限定,优选由坡莫合金等磁性材料、金属等导电性材料或者熔融石英等绝缘材料构成,特别优选由磁性材料构成。特别是进而优选使用由Fe-Ni类材料构成、含有32重量%、39重量%以下的以Ni为主成分的软磁性金属材料的材料。占其余61~68重量%的元素是Fe。这样的Fe-Ni类材料被称为“因瓦合金材料”。通过使用因瓦合金材料作为第一填料F1的材料,能够使复合模制部件40的热膨胀系数成为例如15ppm/℃以下,同时能够得到较高的磁特性。以Ni为主成分的软磁性金属材料也可以含有少量的Co。即,也可以将Ni的一部分用Co置换。由此,能够使复合磁性密封材料的热膨胀系数进一步降低。Co的添加量优选相对于第一填料F1整体在0.1重量%以上、8重量%以下。
使用导电性材料作为第一填料F1的材料的情况下,使用Ag、Cu、Sn等已知的金属粉即可。从成本的观点来看,优选使用磁性材料或绝缘材料作为第一填料F1的材料。使用绝缘材料作为第一填料F1的材料的情况下,能够使用碳酸钙、滑石、二氧化硅、粘土、氧化铝、AlN、BN、BeO、硫酸钡、氢氧化铝、氢氧化镁、氧化锑、玻璃、氧化钛、钛酸钡、耐热性树脂等已知的材料。优选包含选自SiO2、ZrW2O8、(ZrO)2P2O7、KZr2(PO4)3和Zr2(WO4)(PO4)2中的至少一种材料。这些材料热膨胀系数非常低、或者具有负值,所以能够使复合模制材料的热膨胀系数降低。
对于第一填料F1的形状不特别限定,可以为了高填充化而采用球状,为了成为最密填充而混合多种粒度分布的填料。另外,如果使第一填料F1成为大致球形,则也能够减少模制时对电子部件的损伤。特别是为了最密填充化或高填充化,第一填料F1的形状优选为球形。优选第一填料F1振实密度高、粉末比表面积小。作为第一填料F1是磁性材料的情况下的形成方法,有水雾化法、气体雾化法、离心盘雾化法等方法,其中,最优选能够得到较高的振实密度、同时能够减小比表面积的气体雾化法。
复合模制部件40在第一填料F1之外,也可以包含图15A所示的由磁性材料构成的第二填料F2a、图15B所示的由导电性材料构成的第二填料F2b、或图15C所示的由绝缘材料构成的第二填料F2c。第二填料F2a、F2b、F2c的中位粒径d2比第一填料F1的中位粒径d1更小。由此,能够提高复合模制部件40中包含的填料的填充率。关于第二填料F2a、F2b、F2c,也优选其表面被金属涂层M覆盖。由此,能够使复合模制部件40的体积电阻进一步低电阻化。金属涂层M的材料和厚度可以与对第一填料F1施加的金属涂层M的材料和厚度相同。另外,施加了金属涂层M的第二填料F2的粉体状态下的体积电阻率优选在施加了25MPa的压强的状态下为1×10-4Ω·cm以下。包括第一填料F1和第二填料F2a、F2b、F2c的总填料相对于粘结剂的混合比优选为50~85体积%。另外,第一填料F1相对于总填料的混合比优选为50~99体积%。进而,优选以施加了金属涂层M的第一填料F1与施加了金属涂层M的第二填料F2的混合物的粉体状态下的体积电阻率在施加了25MPa的压强的状态下为1×10-4Ω·cm以下的方式,混合第一填料F1和第二填料F2。
图15A所示的第二填料F2a由磁性材料构成。构成第二填料F2a的磁性材料能够使用选自Fe、Fe-Co类合金、Fe-Ni类合金、Fe-Al类合金、Fe-Si类合金、Ni-Zn类尖晶石铁氧体、Mn-Zn类尖晶石铁氧体、Ni-Cu-Zn类尖晶石铁氧体、Mg类尖晶石铁氧体、钇铁类石榴石铁氧体中的至少一种材料。特别是作为构成第二填料F2a的磁性材料,优选使用因瓦合金材料。通过使用因瓦合金材料作为第二填料F2a的材料,能够使复合模制部件40的热膨胀系数成为例如15ppm/℃以下,同时能够得到较高的磁特性。以Ni为主成分的软磁性金属材料也可以含有少量的Co。即,也可以将Ni的一部分用Co置换。由此,能够使复合磁性密封材料的热膨胀系数进一步降低。Co的添加量优选相对于第二填料F2a整体在0.1重量%以上、8重量%以下。另外,第二填料F2a的材料也可以与第一填料F1相同。在第二填料F2a上形成的金属涂层M的厚度优选在1~2000nm的范围内。
图15B所示的第二填料F2b由导电性材料构成。构成第二填料F2b的导电性材料能够使用以Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu为主成分的材料。即使使用导电性材料作为第二填料F2b的材料的情况下,也可以将其表面进一步用金属涂层M覆盖。
图15C所示的第二填料F2c由绝缘材料构成。构成第二填料F2c的绝缘材料能够使用碳酸钙、滑石、二氧化硅、粘土、氧化铝、AlN、BN、BeO、硫酸钡、氢氧化铝、氢氧化镁、氧化锑、玻璃、氧化钛、钛酸钡、耐热性树脂等已知的绝缘材料。耐热性树脂可以是热固化性树脂,也可以是热塑性树脂。特别优选使用SiO2、ZrW2O8、(ZrO)2P2O7、KZr2(PO4)3或Zr2(WO4)(PO4)2等热膨胀系数比第一填料F1更小的材料、或者热膨胀系数具有负值的材料。如果在复合模制部件40中添加这样的第二填料F2c,则能够使热膨胀系数进一步减小。另外,也可以添加氧化铝、氧化镁这样的阻燃剂、用于着色的炭黑或颜料或染料、用于提高滑动性、流动性、分散/搅拌性的100nm以下粒径的表面处理后的纳米二氧化硅、用于提高脱模性的蜡成分等。在第二填料F2c上形成的金属涂层M的厚度优选在1~2000nm的范围内。另外,本发明中,构成复合模制部件40的复合材料并非必须包括第二填料F2a、F2b或F2c。
构成复合模制部件40的复合材料的形态可以是液状和固体形状中的任意一方,形态因与成型方法对应的主剂和固化剂的选择而不同。固体形状的复合材料如果是传递成型用则为平板形状即可,如果是注塑成型用或压缩成型用则为颗粒状即可。另外,关于使用复合材料的模制成型方法,有基于传递成型、压缩成型、注塑成型、浇注、真空浇注、真空印刷、印刷、滴涂、缝隙喷嘴的方法等,能够适当选择。成型条件根据使用的主剂、固化剂、固化促进剂的组合适当选择即可,成型后也可以根据需要实施后固化。
这样,如果使用因瓦合金材料作为第一填料F1的材料,能够具有磁屏蔽特性,同时防止伴随温度变化的基板的弯曲、模制材料的界面剥离、模制材料的裂纹等。
<第二实施方式>
图16是表示本发明的第二实施方式的电路封装12的结构的截面图。
如图16所示,本实施方式的电路封装12中,复合模制部件40的平面尺寸比基板20的平面尺寸略大,由此,基板20的侧面27被复合模制部件40覆盖。在基板20的侧面27上,作为内部配线25的一部分的电源图案25G露出,露出的电源图案25G与复合模制部件40接触。由此,经由电源图案25G对复合模制部件40赋予固定电位(典型而言是接地电位)。其他结构与第一实施方式的电路封装11相同,所以对同一要素附加同一符号,省略重复的说明。
本实施方式的电路封装12中,复合模制部件40在基板20的顶面21和侧面27双方与电源图案23G、25G连接,所以与第一实施方式的电路封装11相比,能够使复合模制部件40的电位(典型而言是接地电位)进一步稳定化。
本实施方式的电路封装12能够通过在将集合基板20A切断从而使基板20单片化之后,在基板20的顶面21和侧面27形成复合模制部件40而制作。
<第三实施方式>
图17是表示本发明的第三实施方式的电路封装13的结构的截面图。
如图17所示,本实施方式的电路封装13中,基板20的侧面27成阶梯状。具体而言,具有侧面下部27b与侧面上部27a相比更突出的形状。在侧面上部27a,电源图案25G露出,露出的电源图案25G与复合模制部件40接触。在侧面下部27b,电源图案25G并不露出,侧面下部27b与复合模制部件40的侧面42构成同一平面。其他结构与第二实施方式的电路封装12相同,所以对同一要素附加同一符号,省略重复的说明。
本实施方式的电路封装13能够通过在集合基板20A上形成构成侧面上部27a的槽,以将该槽填充的方式在基板20的顶面21形成复合模制部件40后单片化而制作。
<第四实施方式>
图18是表示本发明的第四实施方式的电路封装14的结构的截面图。
如图18所示,本实施方式的电路封装14在追加了覆盖复合模制部件40的顶面41和侧面42、和基板20的侧面27的金属膜60这一点上与第一实施方式的电路封装11不同。电源图案25G在基板20的侧面27上露出,其与金属膜60接触。其他结构与第一实施方式的电路封装11相同,所以对同一要素附加同一符号,省略重复的说明。
金属膜60与复合模制部件40一同起到电磁屏蔽的作用,优选以选自Au、Ag、Cu和Al中的至少1种金属为主成分。金属膜60优选电阻尽可能低,考虑成本等最优选使用Cu。金属膜60的电阻值需要至少比复合模制部件40的电阻值更低。另外,金属膜60的外侧表面优选被由SUS、Ni、Cr、Ti、黄铜等防蚀性的金属、或者环氧、酚醛、酰亚胺、聚氨酯、硅酮等树脂构成的防氧化包层覆盖。这是因为金属膜60会因热、湿度等外部环境而氧化劣化,所以为了抑制和防止这一点而优选实施上述处理。金属膜60的形成方法从溅射法、蒸镀法、无电解镀法、电解镀法等公知的方法中适当选择即可,也可以在形成金属膜60前实施作为提高密合性前处理的等离子体处理、偶联处理、喷砂处理、蚀刻处理等。进而,也可以事先较薄地形成钛或铬、SUS等高密合性金属膜作为金属膜60的衬底。
这样,本实施方式的电路封装14具备与电源图案25G连接的金属膜60,所以与第一实施方式的电路封装11相比,能够使复合模制部件40的电位(典型而言是接地电位)进一步稳定化。
<第五实施方式>
图19是表示本发明的第五实施方式的电路封装15的结构的截面图。
如图19所示,本实施方式的电路封装15在追加了覆盖复合模制部件40的顶面41的磁性膜70这一点上与第一实施方式的电路封装11不同。其他结构与第一实施方式的电路封装11相同,所以对同一要素附加同一符号,省略重复的说明。
磁性膜70由由磁性填料分散在热固化性树脂材料中得到的复合磁性材料构成的膜、由软磁性材料或铁氧体构成的薄膜、或者箔或散片(bulk sheet)构成,起到第二磁屏蔽的作用。磁性膜70的有效磁导率需要至少比复合模制部件40的有效磁导率更大,优选为2倍以上。
选择由复合磁性材料构成的膜作为磁性膜70的情况下,作为热固化性树脂材料能够使用环氧树脂、酚醛树脂、硅酮树脂、邻苯二甲酸二烯丙酯树脂、聚酰亚胺树脂、聚氨酯树脂等,能够使用印刷法、成型法、缝隙喷嘴涂布法、喷涂法、滴涂法、注塑法、传递法、压缩成型法、使用未硬化的片状树脂的层叠法等厚膜工艺形成。通过使用热固化性材料,可以提高耐热性、绝缘性、抗冲击性、落下强度等对电路封装要求的可靠性。
另外,作为磁性填料,优选使用铁氧体或软磁性金属,特别优选使用块体中的磁导率高的软磁性金属。作为铁氧体或软磁性金属,可以列举选自Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1种或2种以上金属、或者其氧化物。作为具体例,能够列举Ni-Zn类、Mn-Zn、Ni-Cu-Zn类等铁氧体、坡莫合金(Fe-Ni合金)、超坡莫合金(Fe-Ni-Mo合金)、铁硅铝软磁合金(Fe-Si-Al合金)、Fe-Si合金、Fe-Co合金、Fe-Cr合金、Fe-Cr-Si合金、Fe-Ni-Co合金、Fe等。对于磁性填料的形状不特别限定,可以为了高填充化而采用球状,为了成为最密填充而混合多种粒度分布的填料。为了最大限度地发挥磁导率实数成分的屏蔽效果和磁导率虚数成分的损耗的热变换效果,进而优选混合长径比5以上的扁平粉地形成。
对于磁性填料的表面,也可以为了提高流动性、密合性,而用Si、Al、Ti、Mg等金属的氧化物、或者有机材料进行绝缘涂覆。绝缘涂覆可以在磁性填料的表面对热固化性材料进行涂覆处理,或者通过金属醇盐的脱水反应形成氧化膜,最优选形成氧化硅的涂覆膜。进而优选进一步在其上实施有机官能偶联处理。
复合磁性材料能够使用印刷法、成型法、缝隙喷嘴涂布法、喷涂法、滴涂法、使用未硬化的片状树脂的层叠法等公知的方法在复合模制部件40的顶面41形成。
另外,选择由软磁性材料或铁氧体构成的薄膜作为磁性膜70的情况下,作为其材料,能够使用选自Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1种或2种以上金属、或者其氧化物。在溅射法、蒸镀法等薄膜工艺之外,能够使用镀覆法、喷涂法、AD法、喷镀法等在复合模制部件40的顶面41形成。该情况下,磁性膜70的材料根据需要的磁导率和频率适当选择即可,为了提高低频(kHz~100MHz)侧的屏蔽效果,最优选Fe-Co、Fe-Ni、Fe-Al、Fe-Si类的合金。另一方面,为了提高高频(50~数百MHz)的屏蔽效果,最优选NiZn、MnZn、NiCuZn等铁氧体膜或Fe。
进而,使用箔或散片作为磁性膜70的情况下,如果在形成复合模制部件40时的模具中预先设置箔或散片,则能够在复合模制部件40的顶面41直接形成由箔或散片构成的磁性膜70。
这样,本实施方式的电路封装15在复合模制部件40的顶面41设置了磁导率比复合模制部件40更高的磁性膜70,所以能够进一步提高磁屏蔽特性。另外,也可以是图20所示的变形例的电路封装15A这样,不仅将复合模制部件40的顶面41、进而也将复合模制部件40的侧面42和基板20的侧面27用磁性膜70覆盖。由此,能够进一步提高侧面方向上的磁屏蔽特性。
<第六实施方式>
图21是表示本发明的第六实施方式的电路封装16的结构的截面图。
如图21所示,本实施方式的电路封装16在追加了隔着金属膜60覆盖复合模制部件40的顶面41的磁性膜70这一点上与第四实施方式的电路封装14不同。其他结构与第四实施方式的电路封装14相同,所以对同一要素附加同一符号,省略重复的说明。
本实施方式的电路封装16中,作为电磁屏蔽和磁屏蔽的复合模制部件40的表面被作为电磁屏蔽的金属膜60和作为磁屏蔽的磁性膜70覆盖,能够进一步提高电磁屏蔽和磁屏蔽特性。
以上对本发明优选的实施方式进行了说明,但本发明不限定于上述实施方式,能够在不脱离本发明的主旨的范围内进行各种变更,这些当然也包含在本发明的范围内。
示例
准备中位粒径(D50)为10μm的第一填料F1和中位粒径(D50)为0.7μm的第二填料F2c。第一填料F1由Fe为64重量%、Ni为36重量%的因瓦合金材料构成,对其表面施加厚度50nm的Ag镀层。第二填料F2由耐热性树脂构成,对其表面施加厚度80nm的Ag镀层。
接着,使联苯型环氧树脂、酚醛清漆型固化剂和催化剂(咪唑)在丁基卡必醇中溶解而调整粘结剂,将上述第一填料F1和第二填料F2c投入粘结剂中,用搅拌装置进行搅拌、混合从而得到膏状的复合密封材料。复合密封材料中的第一填料F1的混合比是50体积%,第二填料F2c的混合比是25体积%,粘结剂的混合比是25体积%。
接着,使用图8所示的基板20实际制作了具有与电路封装11相同的结构的实施例试样1和2。作为基板20,使用平面尺寸为7.72mm×7.72mm、厚度为0.3mm的多层树脂基板。而且,试样1中,使图8所示的电源图案23G的宽度W1为1.18mm,试样2中,使图8所示的电源图案23G的宽度W1为2.26mm。因此,电源图案23G的面积在试样1中为1.4mm2,在试样2中为5.1mm2。试样1中,电源图案23G在基板20的表面21中所占的比例为约2.3%。试样2中,电源图案23G在基板20的表面21中所占的比例为约8.6%。
另外,使用图11所示的基板20实际制作了具有与电路封装11相同的结构的实施例试样3。基板20的平面尺寸和厚度与试样1和2相同。而且,使图11所示的电源图案23G的宽度W2为0.52mm。因此,电源图案23G的面积为8.0mm2,电源图案23G在基板20的表面21中所占的比例为约13.5%。
进而,使用图13所示的基板20实际制作了具有与电路封装11相同的结构的实施例试样4。基板20的平面尺寸和厚度与试样1和2相同。而且,使图13所示的电源图案23G的宽度W3为0.44mm。因此,电源图案23G的面积为12.8mm2,电源图案23G在基板20的表面21中所占的比例为约21.5%。
关于复合模制部件40,试样1~4都使用上述复合密封材料,用真空印刷法在基板20的顶面21形成复合模制部件40后,在100℃下加热4小时从而除去溶剂,进而在180℃下进行了3小时的后固化。
另外,作为比较例,制作了代替上述复合密封材料地使用不具有磁性和导电性的一般的模制材料进行模制、并在其表面通过溅射形成了厚度6μm的Cu膜的比较例试样。Cu膜与接地图案连接。
接着,将各试样回流焊安装在屏蔽特性评价用基板上,通过用近磁场测定装置测定噪声衰减量而对屏蔽特性进行了评价。结果如图22所示。
如图22所示,确认了实施例试样1在20MHz~150MHz的频段和1.5GHz~2.4GHz的频段中,与比较例试样相比噪声衰减量更大。另外,确认了实施例试样2~4在测定的全频段(20MHz~2.4GHz)中,与比较例试样相比噪声衰减量更大。确认了特别是在超过80MHz的频段中,电源图案23G的占有率越大,得到越大的噪声衰减量。另外,实施例1~4都在20MHz附近得到了接近检测极限的噪声衰减量。进而,实施例试样3中在1GHz附近得到了接近检测极限的噪声衰减量,实施例试样4中在测定的全频段中得到了接近检测极限的噪声衰减量。
Claims (21)
1.一种电路封装,其特征在于,
具备:
基板,具有电源图案;
电子部件,搭载在所述基板的表面上;和
模制部件,以将所述电子部件嵌入的方式覆盖所述基板的所述表面,并具有导电性,
所述电源图案包括在所述基板的所述表面露出的第一电源图案,
所述模制部件与所述第一电源图案相接。
2.如权利要求1所述的电路封装,其特征在于:
所述第一电源图案在所述基板的所述表面中所占的比例为2%以上。
3.如权利要求2所述的电路封装,其特征在于:
所述第一电源图案在所述基板的所述表面中所占的比例为8%以上。
4.如权利要求1所述的电路封装,其特征在于:
所述第一电源图案在所述基板的所述表面的至少一个角部配置。
5.如权利要求4所述的电路封装,其特征在于:
所述第一电源图案在所述基板的所述表面的至少两个角部配置。
6.如权利要求5所述的电路封装,其特征在于:
所述两个角部位于对角位置。
7.如权利要求1所述的电路封装,其特征在于:
所述第一电源图案沿所述基板的所述表面的至少一条边配置。
8.如权利要求7所述的电路封装,其特征在于:
所述第一电源图案沿所述基板的所述表面的至少两条边配置。
9.如权利要求8所述的电路封装,其特征在于:
所述两条边相互相对。
10.如权利要求1所述的电路封装,其特征在于:
所述电源图案包括在所述基板的侧面露出的第二电源图案,
所述模制部件进一步与所述第二电源图案相接。
11.如权利要求10所述的电路封装,其特征在于:
所述基板的所述侧面包括侧面上部、和与所述侧面上部相比更突出的侧面下部,
所述第二电源图案在所述基板的所述侧面上部露出,
所述模制部件不覆盖所述基板的所述侧面下部,而覆盖所述基板的所述侧面上部。
12.如权利要求1所述的电路封装,其特征在于:
进一步具备覆盖所述模制部件、且导电性比所述模制部件更高的金属膜。
13.如权利要求1所述的电路封装,其特征在于:
所述模制部件包含树脂材料、和与所述树脂材料混合的第一填料,
所述第一填料的表面被导电性比所述第一填料更高的金属涂层覆盖。
14.如权利要求13所述的电路封装,其特征在于:
所述第一填料由磁性材料构成。
15.如权利要求14所述的电路封装,其特征在于:
进一步具备覆盖所述模制部件、并且磁导率比所述模制部件更高的磁性膜。
16.如权利要求13所述的电路封装,其特征在于:
所述模制部件进一步包含比所述第一填料更小的第二填料;
所述第二填料的表面被金属涂层覆盖。
17.如权利要求16所述的电路封装,其特征在于:
所述第二填料由磁性材料构成。
18.如权利要求16所述的电路封装,其特征在于:
所述第二填料由导电性材料构成。
19.如权利要求16所述的电路封装,其特征在于:
所述第二填料由绝缘材料构成。
20.如权利要求14所述的电路封装,其特征在于:
所述第一填料由Fe中含有32~39重量%的以Ni为主成分的金属材料的材料构成。
21.如权利要求1所述的电路封装,其特征在于:
进一步具备使所述电子部件及其端子电极与所述模制部件相互绝缘的绝缘涂层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/832,769 | 2017-12-05 | ||
US15/832,769 US10373917B2 (en) | 2017-12-05 | 2017-12-05 | Electronic circuit package using conductive sealing material |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110034075A true CN110034075A (zh) | 2019-07-19 |
CN110034075B CN110034075B (zh) | 2023-04-28 |
Family
ID=66659465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811483008.2A Active CN110034075B (zh) | 2017-12-05 | 2018-12-05 | 使用具有导电性的模制材料的电路封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10373917B2 (zh) |
CN (1) | CN110034075B (zh) |
TW (1) | TWI692845B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200001102A (ko) * | 2018-06-26 | 2020-01-06 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
KR102514042B1 (ko) * | 2018-08-01 | 2023-03-24 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
US10825782B2 (en) * | 2018-12-27 | 2020-11-03 | Micron Technology, Inc. | Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact |
US11024616B2 (en) * | 2019-05-16 | 2021-06-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
KR102562315B1 (ko) * | 2019-10-14 | 2023-08-01 | 삼성전자주식회사 | 반도체 패키지 |
US10849235B1 (en) * | 2020-05-20 | 2020-11-24 | Tactotek Oy | Method of manufacture of a structure and structure |
US11502015B2 (en) * | 2020-05-28 | 2022-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
US12055633B2 (en) * | 2020-08-25 | 2024-08-06 | Lumentum Operations Llc | Package for a time of flight device |
JP2023130249A (ja) * | 2022-03-07 | 2023-09-20 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
CN114615798B (zh) * | 2022-04-01 | 2022-11-29 | 广州三则电子材料有限公司 | 一种零收缩填孔导电浆料及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110006408A1 (en) * | 2009-07-13 | 2011-01-13 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US20170025363A1 (en) * | 2015-07-22 | 2017-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same |
CN107230664A (zh) * | 2016-03-23 | 2017-10-03 | Tdk株式会社 | 电子电路封装 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003273571A (ja) | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 素子間干渉電波シールド型高周波モジュール |
JP2003298004A (ja) | 2002-04-04 | 2003-10-17 | Fujitsu Ltd | 素子間干渉電波シールド型高周波モジュール及び電子装置 |
JP3826898B2 (ja) | 2003-04-22 | 2006-09-27 | 松下電工株式会社 | 電子部品の製造方法及び半導体装置 |
KR100732787B1 (ko) * | 2005-10-14 | 2007-06-27 | 한화석유화학 주식회사 | 분산성 및 밀착성이 우수한 도전성 무전해 도금분체의제조방법 |
JP4816647B2 (ja) * | 2005-11-28 | 2011-11-16 | 株式会社村田製作所 | 回路モジュールの製造方法および回路モジュール |
JP2009016715A (ja) * | 2007-07-09 | 2009-01-22 | Tatsuta System Electronics Kk | シールド及び放熱性を有する高周波モジュール及びその製造方法 |
US7759163B2 (en) * | 2008-04-18 | 2010-07-20 | Infineon Technologies Ag | Semiconductor module |
WO2010047007A1 (ja) * | 2008-10-23 | 2010-04-29 | 株式会社村田製作所 | 電子部品モジュールの製造方法 |
CN103354228A (zh) * | 2013-07-10 | 2013-10-16 | 三星半导体(中国)研究开发有限公司 | 半导体封装件及其制造方法 |
US9786623B2 (en) * | 2015-03-17 | 2017-10-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming PoP semiconductor device with RDL over top package |
JP6237732B2 (ja) | 2015-08-28 | 2017-11-29 | 東洋インキScホールディングス株式会社 | 電子部品モジュールの製造方法 |
JP6536535B2 (ja) * | 2016-03-31 | 2019-07-03 | Tdk株式会社 | 複合磁性封止材料 |
US9907179B2 (en) * | 2016-04-25 | 2018-02-27 | Tdk Corporation | Electronic circuit package |
-
2017
- 2017-12-05 US US15/832,769 patent/US10373917B2/en active Active
-
2018
- 2018-12-03 TW TW107143246A patent/TWI692845B/zh active
- 2018-12-05 CN CN201811483008.2A patent/CN110034075B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110006408A1 (en) * | 2009-07-13 | 2011-01-13 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
CN101958254A (zh) * | 2009-07-13 | 2011-01-26 | 日月光半导体制造股份有限公司 | 芯片封装体及其制作方法 |
US20170025363A1 (en) * | 2015-07-22 | 2017-01-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same |
CN107230664A (zh) * | 2016-03-23 | 2017-10-03 | Tdk株式会社 | 电子电路封装 |
Also Published As
Publication number | Publication date |
---|---|
TW201926590A (zh) | 2019-07-01 |
US20190172791A1 (en) | 2019-06-06 |
TWI692845B (zh) | 2020-05-01 |
CN110034075B (zh) | 2023-04-28 |
US10373917B2 (en) | 2019-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110034075A (zh) | 使用具有导电性的模制材料的电路封装 | |
CN108074878B (zh) | 复合磁性密封材料及使用其的电子电路封装体 | |
JP5988004B1 (ja) | 電子回路パッケージ | |
JP6376230B2 (ja) | 電子回路パッケージ | |
JP6328698B2 (ja) | 電子回路パッケージ | |
JP6407186B2 (ja) | 電子回路パッケージ | |
CN109119380A (zh) | 使用复合磁性密封材料的电子电路封装 | |
TWI634639B (zh) | 電子電路封裝 | |
JP6394719B2 (ja) | 電子回路パッケージ | |
CN107424961B (zh) | 使用复合磁性密封材料的电子电路封装 | |
US20190035744A1 (en) | Electronic circuit package using composite magnetic sealing material | |
JP2018019057A (ja) | 電子回路パッケージ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |