TWI692845B - 使用具有導電性的模製材料之電子電路封裝 - Google Patents
使用具有導電性的模製材料之電子電路封裝 Download PDFInfo
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- TWI692845B TWI692845B TW107143246A TW107143246A TWI692845B TW I692845 B TWI692845 B TW I692845B TW 107143246 A TW107143246 A TW 107143246A TW 107143246 A TW107143246 A TW 107143246A TW I692845 B TWI692845 B TW I692845B
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Abstract
本發明提供一種使用具有導電性的模製材料之電路封裝。本說明書中所揭示的電路封裝具備具有電源圖案的基板、搭載於上述基板表面的電子零件,以及以將上述電子零件嵌入的方式覆蓋上述基板的上述表面且具有導電性的模製構件。上述電源圖案包括在上述基板的上述表面露出的第一電源圖案,上述模製構件與上述第一電源圖案相接。
Description
本發明係關於電路封裝,特別係關於使用具有導電性的模製材料的電路封裝。
近年來,智慧手機等電子機器採用高性能的無線通訊電路和數位晶片,且具有所使用之半導體IC的工作頻率也上升的傾向。進而,預測具有將多個半導體IC用最短配線連接的2.5D結構或3D結構的系統級封裝(System In Package,SIP)化將加速,電源系統電路的模組化今後也會逐漸增加。進而,預測將多個電子零件(電感器、電容器、電阻、濾波器等被動零件、電晶體、二極體等主動零件、半導體IC等積體電路零件、以及其他電路結構所需的零件的總稱)模組化而成的電路模組今後也會越發增加,該等之總稱即電路封裝因智慧手機等電子機器的高性能化和小型化、薄型化而具有高密度安裝的傾向。這些傾向另一方面表示雜訊引起的誤動作和電磁干擾變得顯著,用現有的雜訊對策難以防止誤動作和電磁干擾。因此,近年來,電路封裝的自遮罩化有所進展,提出了用導電膏或鍍覆或濺射法進行的電磁遮罩並實用化,但今後要求更高的遮罩特性。
為了實現這一點,日本專利特開昭59-132196號公報中公開了用磁性模製樹脂對電路進行模製,並且用金屬殼體覆蓋整體,由此提高了遮罩性的電路封裝。
但是,日本專利特開昭59-132196號公報中記載的電路封裝中,因為用金屬殼體覆蓋整體,所以難以實現其高度降低。另外,因為在金屬殼體上設置了多個孔,並且金屬殼體並未與基板的接地圖案等連接,所以不能夠得到充分的遮罩效果。
從而,本發明的目的在於提供一種能夠實現高度降低、同時得到較高的遮罩特性的電路封裝。
本發明的電路封裝具備:基板,其具有電源圖案;電子零件,其搭載在上述基板的表面;和模製構件,其以將上述電子零件嵌入的方式覆蓋上述基板的上述表面,並具有導電性;上述電源圖案包括在上述基板的上述表面露出的第一電源圖案;上述模製構件與上述第一電源圖案相接。
根據本發明,因為模製構件具有導電性,所以能夠藉由模製構件自身得到電磁遮罩功能。
本發明中,上述第一電源圖案在上述基板的上述表面中所占的比例可為2%以上,亦可為8%以上。藉由增大第一電源圖案在基板的表面中所占的比例,能夠提高遮罩。
本發明中,上述第一電源圖案可以在上述基板的上述表面的至少一個角部配置,也可以在至少兩個角部配置。該情況下,上述兩個角部也可以是位於對角位置的。這樣,如果將第一電源圖案配置在基板的角部,能夠輕易地避免第一電源圖案與其他配
線圖案的干涉。
本發明中,上述第一電源圖案可以沿上述基板的上述表面之至少一邊配置,也可以沿至少兩邊配置。該情況下,上述兩邊可以彼此相對。這樣,如果使第一電源圖案沿基板的邊配置,能夠輕易地避免第一電源圖案與其他配線圖案的干涉。
本發明中,亦可為上述電源圖案包括在上述基板的側面露出的第二電源圖案,上述模製構件進而與上述第二電源圖案相接。由此,能夠使模製構件的電位更加穩定。
本發明中,上述基板的上述側面包括側面上部以及與上述側面上部相比更突出的側面下部,上述第二電源圖案在上述基板的上述側面上部露出,上述模製構件也可以不覆蓋上述基板的上述側面下部,而覆蓋上述基板的上述側面上部。藉此,能夠在使基板單片化之前,將模製構件與在基板的側面露出的第二電源圖案連接。
本發明的電路封裝可以進而具備覆蓋上述模製構件、導電性比上述模製構件更高的金屬膜。由此,能夠進一步提高電磁遮罩特性。
本發明中,上述模製構件包含樹脂材料以及與上述樹脂材料混合的第一填料,上述第一填料的表面可以被導電性比上述第一填料更高的金屬塗層覆蓋。由此,因為模製構件具有導電性和磁性,所以能夠藉由模製構件自身得到電磁遮罩功能。特別是,如果使用磁性材料作為第一填料,則能夠得到同時具有電磁遮罩功能和磁遮罩功能的複合遮罩結構。
本發明的電路封裝可以進而具備覆蓋上述模製構
件、磁導率比上述模製構件更高的磁性膜。由此,能夠進一步提高磁遮罩特性。
本發明中,上述模製構件可以進而包含中位粒徑比上述第一填料更小的第二填料。該情況下,上述第二填料的表面可以被金屬塗層覆蓋。由此,能夠使模製構件的體積電阻進一步降低。
本發明中,上述第二填料可以包含磁性材料,也可以包含導電性材料,也可以包含絕緣材料。
本發明中,上述第一填料可以包含以Fe中含有32~39重量%的以Ni為主成分的金屬材料的材料。由此,能夠使模製構件的熱膨脹係數大幅減少,例如成為15ppm/℃以下。因此,能夠防止基板的彎曲、模製材料的介面剝離、模製材料的裂紋等。
本發明的電路封裝可以進而具備使上述電子零件及其端子電極與上述模製構件彼此絕緣的絕緣塗層。由此,能夠防止電子零件與模製構件的短路不良。
11~16、15A‧‧‧電路封裝
20‧‧‧基板
20A‧‧‧集合基板
21‧‧‧表面
22‧‧‧背面
23‧‧‧焊盤圖案
23G、25G‧‧‧電源圖案
24‧‧‧焊料
25‧‧‧內部配線
26‧‧‧外部端子
27‧‧‧側面
27a‧‧‧側面上部
27b‧‧‧側面下部
31、32、33‧‧‧電子零件
40‧‧‧複合模製構件
41‧‧‧(複合模製構件之)上表面
42‧‧‧(複合模製構件之)側面
51、52‧‧‧絕緣塗層
60‧‧‧金屬膜
70‧‧‧磁性膜
a‧‧‧虛線
W1、W2、W3‧‧‧寬度
d1、d2‧‧‧中位粒徑
M‧‧‧金屬塗層
F1‧‧‧第一填料
F2a、F2b、F2c‧‧‧第二填料
本發明的上述特徵及效果根據以下的附圖以及附圖所相關之較佳實施例的說明將更為清楚。
圖1為表示本發明的第一實施形態的電路封裝結構之截面圖;圖2為表示圖1所示之基板表面的示意性平面圖;圖3至圖7為用於說明圖1所示之電路封裝的製造方法的步驟圖;圖8為表示基板表面上的電源圖案配置之第一例的示意性平面圖;圖9為表示基板表面上的電源圖案配置之第二例的示意性平面
圖;圖10為表示基板表面上的電源圖案配置之第三例的示意性平面圖;圖11為表示基板表面上的電源圖案配置之第四例的示意性平面圖;圖12為表示基板表面上的電源圖案配置之第五例的示意性平面圖;圖13為表示基板表面上的電源圖案配置之第六例的示意性平面圖;圖14為用於說明第一填料之結構的截面圖;圖15A至圖15C為用於說明第二填料之結構的截面圖;圖16為表示本發明之第二實施形態的電路封裝結構之截面圖;圖17為表示本發明之第三實施形態的電路封裝結構之截面圖;圖18為表示本發明之第四實施形態的電路封裝結構之截面圖;圖19為表示本發明之第五實施形態的電路封裝結構之截面圖;圖20為表示本發明之第五實施形態的變形例的電路封裝結構之截面圖;圖21為表示本發明之第六實施形態的電路封裝結構之截面圖。
圖22為表示實施例之測定結果的曲線圖。
以下,參照附圖詳細地說明本發明較佳之實施形態。
圖1為表示本發明的第一實施形態的電路封裝11之結構之截面圖。
如圖1所示,本實施形態的電路封裝11具備基板20;搭載於基板20上的多個電子零件31、32;以及以將電子零件31、32嵌入的方式覆蓋基板20的表面21且具有導電性的複合模製構件40。
對於本實施形態的電路封裝11的種類並無特別限定,例如可以列舉對高頻信號進行處理的高頻模組、進行電源控制的電源模組、具有2.5D結構或3D結構的系統級封裝(SIP)、無線通訊用或數位電路用半導體封裝等。圖1中僅圖示了2個電子零件31、32,但實際上內部包含有更多的電子零件。
基板20具有在內部嵌入了多條配線的雙面和多層配線結構,可以是FR-4、FR-5、BT、氰酸酯、酚醛、醯亞胺等熱固性樹脂基材的有機基板、液晶聚合物等熱塑性樹脂基材的有機基板、LTCC基板、HTCC基板、柔性基板等任意的種類。本實施形態中基板20是4層結構,具有在基板20的表面21和背面22形成的配線層以及嵌入在內部的2層配線層。在基板20的表面21形成了多個焊盤圖案23。焊盤圖案23是用於與電子零件31、32連接的內部電極,兩者經由焊料24(或導電膏)電連接並且機械連接。作為一例,電子零件31是控制器等半導體晶片,電子零件32是電容器或線圈等被動零件。電子零件的一部分(例如薄型化的半導體晶片等)也可以嵌入基板20中。
焊盤圖案23經由在基板20的內部形成的內部配線25,與在基板20的背面22形成的外部端子26連接。實際使用時,電路封裝11安裝在未圖示的主機板等之上,將主機板上的焊盤圖案與電路封裝11的外部端子26電連接。作為焊盤圖案23、內部配
線25和外部端子26的導體所包含之材料,可以是銅、銀、金、鎳、鉻、鋁、鈀、銦等金屬或其金屬合金,也可以是用樹脂或玻璃作為黏結劑的導電材料,於基板20是有機基板或柔性基板的情況下,從成本和電導率等觀點來看較佳為使用銅、銀。作為這些導電材料的形成方法,可使用印刷、鍍覆、箔積層、濺射、蒸鍍、噴墨等方法。另外,也可以在已形成的焊盤圖案23上藉由鍍覆或濺射、蒸鍍等方法形成Au、Pd、Ag、Sn等低電阻金屬,或者形成Cu-OSP等抗氧化膜。
電子零件31、32及其端子電極和焊料24被絕緣塗層51、52覆蓋,由此與複合模製構件40絕緣。圖1所示的例子中,在電子零件31與基板20之間設置有絕緣塗層51,但也可以依覆蓋電子零件31的整體的方式設置絕緣塗層51。電子零件32整體則被絕緣塗層52所覆蓋。
如圖1和圖2所示,從焊盤圖案23引出的電源圖案23G不被絕緣塗層51、52覆蓋而是露出,與複合模製構件40接觸。電源圖案23G典型而言是被賦予接地電位的接地圖案,但只要是被賦予固定電位的圖案即可,不限定於接地圖案。
複合模製構件40以將電子零件31、32嵌入的方式覆蓋基板20的表面21地設置。複合模製構件40與一般的模製構件不同,具有導電性。由此,在作為模製構件的通常的功能之外,也起到電磁遮罩的作用。本實施形態中,複合模製構件40的側面42與基板20的側面27構成同一平面。複合模製構件40的細節將在後文中詳述,較佳為包含與現有的磁性模製構件相比熱膨脹係數非常小(例如15ppm/℃以下)的複合材料。
電源圖案23G在基板20的表面21中所占的比例越大,遮罩特性越是提高。這是因為電源圖案23G在基板20的表面21中所占的比例越大,則複合模製構件40的電位越穩定。若考慮此點,較佳為電源圖案23G在基板20的表面21中所占的比例為2%以上。另一方面,電源圖案23G的佔有率增加時,基板20的表面21上能夠形成其他配線圖案的面積便減少。若考慮此點,較佳為電源圖案23G在基板20的表面21中所占的比率為30%以下。
接著,對本實施形態的電路封裝11的製造方法進行說明。
圖3至圖7為用於說明電路封裝11的製造方法的步驟圖。
首先,如圖3所示,準備具有多層配線結構的集合基板20A。在集合基板20A的表面21形成了多個焊盤圖案23和電源圖案23G,在集合基板20A的背面22形成了多個外部端子26。另外,在集合基板20A的內層形成了多條內部配線25。另外,圖3~圖6所示的虛線a指的是在之後的劃片步驟中要切斷的部分。
接著,如圖3所示,以與焊盤圖案23連接的方式在集合基板20A的表面21搭載多個電子零件31、32。具體而言,對焊盤圖案23上供給焊料24之後,搭載電子零件31、32,藉由進行迴焊而將電子零件31、32與焊盤圖案23連接即可。
接著,如圖4所示,用絕緣塗層51、52覆蓋電子零件31、32、電子零件31、32的端子電極和焊料24。此時,需要電源圖案23G的至少一部分成為不被絕緣塗層51、52覆蓋而是露出的狀態。
接著,如圖5所示,以將電子零件31、32嵌入的方式用模製構件40覆蓋集合基板20A的表面21。作為模製構件40的形成方法,可使用基於傳遞成型、壓縮成型、注塑成型、澆注、真空澆注、滴塗(dispense)、縫隙噴嘴的方法等。之後,如圖6所示,藉由對模製構件40的上表面進行研磨,而調整模製構件40的厚度。對於複合模製構件40的厚度並無特別限定,較佳為包括電子零件31、32的所有電子零件中,最高的電子零件的上部中之複合模製構件40的厚度為50μm以上,進而較佳為100μm以上。由此,能夠使複合模製構件40的體積電阻率足夠小。但是,本發明中,並不一定要對複合模製構件40的上表面進行研磨。
進而,如圖7所示,藉由沿虛線a將集合基板20A切斷而使基板20單片化時,便完成本實施形態的電路封裝11。
如此,本實施形態的電路封裝11中,因為複合模製構件40具有導電性,所以複合模製構件40自身作為電磁遮罩而發揮作用。藉此,電子零件31、32發出的電磁波或從外部傳播來的電磁波在複合模製構件40的內部被變換為電流,能夠經由電源圖案23G流向外部。而且,本實施形態中,因為電源圖案23G在基板20的表面21露出,所以僅以覆蓋基板20的表面21的方式形成複合模製構件40,就能夠對複合模製構件40賦予固定電位。
另外,圖2所示的例子中,從焊盤圖案23引出的電源圖案23G與複合模製構件40相接,但基板20的表面21上電源圖案23G與焊盤圖案23並不一定是一體的。因此,也可以設置自焊盤圖案23獨立的電源圖案23G。另外,對於電源圖案23G在基板20的表面21上的位置並無特別限定。例如也可以如圖8所示般,
將電源圖案23G配置在基板20的表面21的角部附近。圖8所示的例子中,在基板20的表面21的中央部搭載電子零件33,在基板20的表面21的位於對角位置的2個角部附近配置了電源圖案23G。另外,也可以如圖9所示,在基板20的表面21的所有角部附近都配置電源圖案23G。基板20的表面21的角部附近與中央區域相比、配線圖案的形成密度更低的情況較多,所以藉由在該部分配置電源圖案23G,能夠將面積的額外處理(overhead)抑制為最低限度。
另外,也可以如圖10所示,沿基板20的表面21的一邊配置電源圖案23G。基板20的表面21的外周附近與中央區域相比、配線圖案的形成密度更低的情況較多,所以藉由在該部分配置電源圖案23G,能夠將面積的額外處理抑制為最低限度。而且,與將電源圖案23G配置在角部附近的情況相比,能夠充分確保電源圖案23G的面積。於電源圖案23G的面積不足的情況下,也可以如圖11所示地,沿相對的兩邊配置電源圖案23G,也可以如圖12所示,沿鄰接的兩邊配置電源圖案23G,也可以如圖13所示,沿所有的邊配置電源圖案23G。
接著,對複合模製構件40所包含的模製材料詳細地進行說明。
模製構件40所包含的模製材料與一般的模製材料不同,其具有導電性。而且,複合模製構件40因為與電源圖案23G連接,所以被賦予接地電位等固定電位。由此,能夠使複合模製構件40自身具有電磁遮罩功能。為了充分發揮電磁遮罩效果,較佳為導電性模製構件40的體積電阻率為1×10-4Ω‧cm以下。
複合模製構件40包含黏結劑和第一填料。黏結劑並無特別限定,較佳為以熱固性樹脂材料為主成分。具體而言,較佳為以環氧樹脂、酚醛樹脂、聚氨酯樹脂、矽酮樹脂或醯亞胺樹脂為主成分,進而較佳為使用環氧樹脂或酚醛樹脂類的半導體密封材料中使用的主劑和固化劑。
最佳為末端具有反應性的環氧基的環氧樹脂,能夠與各種固化劑和固化促進劑組合。作為環氧樹脂的例子,可以列舉雙酚A型、雙酚F型、苯氧基、萘、多官能型(雙環戊二烯型等)、聯苯型(二官能型)和特殊結構型,能夠低熱膨脹化的聯苯、萘、雙環戊二烯型等是有用的。作為固化劑或固化促進劑的例子,可以列舉胺類化合物脂環族二胺、芳香族二胺、其他胺類(咪唑、叔胺)、酸酐類化合物(主要是高溫固化劑)、酚醛樹脂(酚醛清漆型、甲酚酚醛清漆型等)、氨基樹脂、雙氰胺、路易士酸配位化合物。材料的攪拌方法適當使用捏合機或三輥研磨機、攪拌機等公知的方法即可。
圖14是表示第一填料F1的一例的截面圖。第一填料F1的中位粒徑(D50)為d1,較佳為對其表面施加導電性比第一填料F1更高的金屬塗層M。如果對第一填料F1的表面施加金屬塗層M,則能夠使複合模製構件40的體積電阻進一步低電阻化。作為金屬塗層M的材料,可以列舉以Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu為主成分的材料,在這些之中較佳為使用難以氧化劣化、電阻率低的Ag、Au。另外,為了使複合模製構件40的體積電阻進一步低電阻化,金屬塗層M的電阻率較佳為5×10-6Ω‧cm以下。在第一填料F1上形成的金屬塗層M的厚度較
佳為1~3000nm的範圍。進而,施加了金屬塗層M的第一填料F1的在粉體狀態下的體積電阻率較佳為在外加了25MPa的壓力的狀態下為1×10-3Ω‧cm以下。
對於第一填料F1的材料並無特別限定,較佳為包含坡莫合金等磁性材料、金屬等導電性材料或者熔融石英等絕緣材料,特佳為包含磁性材料。特別是進而較佳為使用包含Fe-Ni類材料、含有32重量%、39重量%以下的以Ni為主成分的軟磁性金屬材料的材料。占其餘61~68重量%的元素為Fe。這樣的Fe-Ni類材料被稱為「不變鋼材料」。藉由使用不變鋼材料作為第一填料F1的材料,能夠使複合模製構件40的熱膨脹係數成為例如15ppm/℃以下,同時能夠得到較高的磁特性。以Ni為主成分的軟磁性金屬材料也可以含有少量的Co。即,也可以將Ni的一部分用Co置換。由此,能夠使複合磁性密封材料的熱膨脹係數進一步降低。Co的添加量較佳為相對於第一填料F1整體在0.1重量%以上、8重量%以下。
使用導電性材料作為第一填料F1的材料的情況下,使用Ag、Cu、Sn等已知的金屬粉即可。從成本的觀點來看,較佳為使用磁性材料或絕緣材料作為第一填料F1的材料。使用絕緣材料作為第一填料F1的材料的情況下,可使用碳酸鈣、滑石、二氧化矽、黏土、氧化鋁、AlN、BN、BeO、硫酸鋇、氫氧化鋁、氫氧化鎂、氧化銻、玻璃、氧化鈦、鈦酸鋇、耐熱性樹脂等已知的材料。較佳為包含選自SiO2、ZrW2O8、(ZrO)2P2O7、KZr2(PO4)3和Zr2(WO4)(PO4)2所組成之群中的至少一種材料。該等材料之熱膨脹係數非常低、或者具有負值,所以能夠使複合模製材料的熱膨脹係
數降低。
對於第一填料F1的形狀並無特別限定,然而,可為了高填充化而採用球狀,並為了成為最密填充而混合多種粒度分佈的填料。另外,如果使第一填料F1成為近似球形,亦能減少模製時對電子零件的損傷。特別是為了最密填充化或高填充化,第一填料F1的形狀較佳為球形。較佳為第一填料F1敲緊密度高、粉末比表面積小。作為第一填料F1為磁性材料之情況下的形成方法,有水霧化法、氣體霧化法、離心盤霧化法等方法,其中,最佳為能夠得到較高的敲緊密度、同時能夠減少比表面積的氣體霧化法。
複合模製構件40在第一填料F1之外,也可以包含圖15A所示的包含磁性材料的第二填料F2a、圖15B所示的包含導電性材料的第二填料F2b、或圖15C所示的包含絕緣材料的第二填料F2c。第二填料F2a、F2b、F2c的中位粒徑d2比第一填料F1的中位粒徑d1更小。由此,能夠提高複合模製構件40中所包含的填料之填充率。關於第二填料F2a、F2b、F2c,較佳為其表面被金屬塗層M覆蓋。由此,能夠使複合模製構件40的體積電阻進一步低電阻化。金屬塗層M的材料和厚度可以與對第一填料F1施加的金屬塗層M的材料和厚度相同。另外,施加了金屬塗層M的第二填料F2的粉體狀態下的體積電阻率較佳為在外加了25MPa的壓力的狀態下為1×10-4Ω‧cm以下。包括第一填料F1和第二填料F2a、F2b、F2c的總填料相對於黏結劑的混合比較佳為50~85體積%。另外,第一填料F1相對於總填料的混合比較佳為50~99體積%。進而,較佳為以施加了金屬塗層M的第一填料F1與施加了金屬塗層M的第二填料F2的混合物的粉體狀態下的體積電阻率,在外加了25MPa
的壓力的狀態下為1×10-4Ω‧cm以下的方式,混合第一填料F1和第二填料F2。
圖15A所示的第二填料F2a包含磁性材料。第二填料F2a所包含的磁性材料可使用選自Fe、Fe-Co類合金、Fe-Ni類合金、Fe-Al類合金、Fe-Si類合金、Ni-Zn類尖晶石鐵氧體、Mn-Zn類尖晶石鐵氧體、Ni-Cu-Zn類尖晶石鐵氧體、Mg類尖晶石鐵氧體、釔鐵類石榴石鐵氧體所組成之群中的至少一種材料。特別是作為第二填料F2a所包含的磁性材料,較佳為使用不變鋼材料。藉由使用不變鋼材料作為第二填料F2a的材料,能夠使複合模製構件40的熱膨脹係數成為例如15ppm/℃以下,同時能夠得到較高的磁特性。以Ni為主成分的軟磁性金屬材料也可以含有少量的Co。即,也可以將Ni的一部分用Co置換。由此,能夠使複合磁性密封材料的熱膨脹係數進一步降低。Co的添加量較佳為相對於第二填料F2a整體在0.1重量%以上、8重量%以下。另外,第二填料F2a的材料也可以與第一填料F1相同。在第二填料F2a上形成的金屬塗層M的厚度較佳為在1~2000nm的範圍內。
圖15B所示的第二填料F2b包含導電性材料。第二填料F2b所包含的導電性材料可使用以Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu為主成分的材料。即使使用導電性材料作為第二填料F2b之材料的情況下,也可以將其表面進一步用金屬塗層M覆蓋。
圖15C所示的第二填料F2c包含絕緣材料。第二填料F2c所包含的絕緣材料可使用碳酸鈣、滑石、二氧化矽、黏土、氧化鋁、AlN、BN、BeO、硫酸鋇、氫氧化鋁、氫氧化鎂、氧化銻、
玻璃、氧化鈦、鈦酸鋇、耐熱性樹脂等已知的絕緣材料。耐熱性樹脂可以是熱固性樹脂,也可以是熱塑性樹脂。特佳為使用SiO2、ZrW2O8、(ZrO)2P2O7、KZr2(PO4)3或Zr2(WO4)(PO4)2等熱膨脹係數比第一填料F1更小的材料、或者熱膨脹係數具有負值的材料。如果在複合模製構件40中添加這樣的第二填料F2c,則能夠使熱膨脹係數進一步降低。另外,也可以添加氧化鋁、氧化鎂這樣的阻燃劑、用於著色的炭黑或顏料或染料、用於提高滑動性、流動性、分散/攪拌性的100nm以下粒徑的表面處理後的奈米二氧化矽、用於提高脫模性的蠟成分等。在第二填料F2c上形成的金屬塗層M的厚度較佳為在1~2000nm的範圍內。另外,本發明中,複合模製構件40所包含的複合材料並不一定包括第二填料F2a、F2b或F2c。
複合模製構件40所包含的複合材料的形態可以是液狀和固體形狀中的任意一種,形態因與成型方法對應的主劑和固化劑的選擇而不同。固體形狀的複合材料如果是傳遞成型用則為平板形狀即可,如果是注塑成型用或壓縮成型用則為顆粒狀即可。另外,關於使用複合材料的模製成型方法,有基於傳遞成型、壓縮成型、注塑成型、澆注、真空澆注、真空印刷、印刷、滴塗、縫隙噴嘴的方法等,能夠適當選擇。成型條件根據使用的主劑、固化劑、固化促進劑的組合適當選擇即可,成型後也可以根據需要實施後固化。
如此,如果使用不變鋼材料作為第一填料F1的材料,能夠具有磁遮罩特性,同時防止伴隨溫度變化之基板彎曲、模製材料的介面剝離、模製材料的裂紋等。
圖16為本發明之第二實施形態的電路封裝12之結構之截面圖。
如圖16所示,本實施形態的電路封裝12中,複合模製構件40的平面尺寸比基板20的平面尺寸略大,藉此,基板20的側面27被複合模製構件40覆蓋。在基板20的側面27上,作為內部配線25的一部分的電源圖案25G露出,露出的電源圖案25G與複合模製構件40接觸。藉此,經由電源圖案25G對複合模製構件40賦予固定電位(典型而言是接地電位)。其他結構與第一實施形態的電路封裝11相同,因此對同一要素附加同一符號,省略重複的說明。
本實施形態的電路封裝12中,複合模製構件40在基板20的上表面21和側面27雙方與電源圖案23G、25G連接,所以與第一實施形態的電路封裝11相比,能夠使複合模製構件40的電位(典型而言是接地電位)進一步穩定化。
本實施形態的電路封裝12能夠藉由在將集合基板20A切斷從而使基板20單片化之後,在基板20的上表面21和側面27形成複合模製構件40而製作。
圖17為表示本發明之第三實施形態的電路封裝13之結構之截面圖。
如圖17所示,本實施形態的電路封裝13中,基板20的側面27成為階梯狀。具體而言,具有與側面上部27a相比側
面下部27b更為突出的形狀。在側面上部27a,電源圖案25G露出,露出的電源圖案25G與複合模製構件40接觸。在側面下部27b,電源圖案25G並未露出,側面下部27b與複合模製構件40的側面42構成同一平面。其他結構與第二實施形態的電路封裝12相同,因此對同一要素附加同一符號,省略重複的說明。
本實施形態的電路封裝13能夠藉由在集合基板20A上形成構成側面上部27a的溝,以將該溝填充的方式在基板20的上表面21形成複合模製構件40後單片化而製作。
圖18為表示本發明之第四實施形態的電路封裝14之結構之截面圖。
如圖18所示,本實施形態的電路封裝14在追加了覆蓋複合模製構件40的上表面41和側面42、和基板20的側面27的金屬膜60這一點上與第一實施形態的電路封裝11不同。電源圖案25G在基板20的側面27上露出,其與金屬膜60接觸。其他結構與第一實施形態的電路封裝11相同,因此對同一要素附加同一符號,省略重複的說明。
金屬膜60與複合模製構件40一同起到電磁遮罩的作用,較佳為以選自Au、Ag、Cu和Al中的至少1種金屬為主成分。金屬膜60較佳為具有盡可能低之電阻,而考慮成本等最佳為使用Cu。金屬膜60的電阻值需要至少比複合模製構件40的電阻值更低。另外,金屬膜60的外側表面較佳為被包含SUS、Ni、Cr、Ti、黃銅等防蝕性的金屬、或者環氧、酚醛、醯亞胺、聚氨酯、矽酮等
樹脂的防氧化包層覆蓋。由於金屬膜60會因熱、濕度等外部環境而氧化劣化,所以為了抑制和防止這一點,較佳為實施上述處理。金屬膜60的形成方法可從濺射法、蒸鍍法、無電解鍍法、電解鍍法等公知的方法中適當選擇,也可以在形成金屬膜60前實施作為提高密合性前處理的電漿處理、偶合處理、噴砂處理、蝕刻處理等。進而,也可以事先較薄地形成鈦或鉻、SUS等高密合性金屬膜作為金屬膜60的基底。
如此,本實施形態的電路封裝14具備與電源圖案25G連接的金屬膜60,所以與第一實施形態的電路封裝11相比,能夠使複合模製構件40的電位(典型而言是接地電位)進一步穩定化。
圖19為表示本發明的第五實施形態的電路封裝15之結構之截面圖。
如圖19所示,本實施形態的電路封裝15在追加了覆蓋複合模製構件40的頂面41的磁性膜70這一點上與第一實施形態的電路封裝11不同。其他結構與第一實施形態的電路封裝11相同,因此對同一要素附加同一符號,省略重複的說明。
磁性膜70為包含磁性填料分散在熱固性樹脂材料中得到的複合磁性材料的膜、包含軟磁性材料或鐵氧體的薄膜、或者包含箔或散片(bulk sheet),進而起到第二磁遮罩的作用。磁性膜70的有效磁導率需要至少比複合模製構件40的有效磁導率更大,較佳為2倍以上。
選擇包含複合磁性材料之膜作為磁性膜70的情況
下,作為熱固性樹脂材料能夠使用環氧樹脂、酚醛樹脂、矽酮樹脂、鄰苯二甲酸二烯丙酯樹脂、聚醯亞胺樹脂、聚氨酯樹脂等,能夠使用印刷法、成型法、縫隙噴嘴塗佈法、噴塗法、滴塗法、注塑法、傳遞法、壓縮成型法、使用未硬化的片狀樹脂的層疊法等厚膜工藝形成。藉由使用熱固性材料,可以提高耐熱性、絕緣性、抗衝擊性、落下強度等對電路封裝要求的可靠性。
另外,作為磁性填料,較佳為使用鐵氧體或軟磁性金屬,特佳為使用塊體中磁導率高的軟磁性金屬。作為鐵氧體或軟磁性金屬,可以列舉選自Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1種或2種以上金屬、或者其氧化物。作為具體例,能夠列舉Ni-Zn類、Mn-Zn、Ni-Cu-Zn類等鐵氧體、坡莫合金(Fe-Ni合金)、超級坡莫合金(Fe-Ni-Mo合金)、三達斯特合金(Fe-Si-Al合金)、Fe-Si合金、Fe-Co合金、Fe-Cr合金、Fe-Cr-Si合金、Fe-Ni-Co合金、Fe等。對於磁性填料的形狀並無特別限定,可以為了高填充化而採用球狀,為了成為最密填充而混合多種粒度分佈的填料。為了最大限度地發揮磁導率實數成分的遮罩效果和磁導率虛數成分的損耗的熱變換效果,進而較佳為混合長徑比5以上的扁平粉而形成。
對於磁性填料的表面,也可以為了提高流動性、密合性,而用Si、Al、Ti、Mg等金屬的氧化物、或者有機材料進行絕緣塗覆。絕緣塗覆可以在磁性填料的表面對熱固性材料進行塗覆處理,或者藉由金屬醇鹽的脫水反應形成氧化膜,最佳為形成氧化矽的塗覆膜。進而較佳為進一步在其上實施有機官能偶聯處理。
複合磁性材料能夠使用印刷法、成型法、縫隙噴嘴塗佈法、噴塗法、滴塗法、使用未硬化的片狀樹脂的層疊法等公知的
方法在複合模製構件40的上表面41形成。
另外,選擇包含軟磁性材料或鐵氧體的薄膜作為磁性膜70的情況下,作為其材料,能夠使用選自Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1種或2種以上金屬、或者其氧化物。在濺射法、蒸鍍法等薄膜工藝之外,能夠使用鍍覆法、噴塗法、AD法、噴鍍法等在複合模製構件40的上表面41形成。於該情況下,磁性膜70的材料根據所需的磁導率和頻率適當選擇即可,為了提高低頻(kHz~100MHz)側的遮罩效果,最佳為Fe-Co、Fe-Ni、Fe-Al、Fe-Si類的合金。另一方面,為了提高高頻(50~數百MHz)的遮罩效果,最佳為NiZn、MnZn、NiCuZn等鐵氧體膜或Fe。
進而,使用箔或散片作為磁性膜70的情況下,如果在形成複合模製構件40時的模具中預先設置箔或散片,則能夠在複合模製構件40的上表面41直接形成包含箔或散片的磁性膜70。
如此,本實施形態的電路封裝15在複合模製構件40的頂面41設置了磁導率比複合模製構件40更高的磁性膜70,所以能夠進一步提高磁遮罩特性。另外,也可以如圖20所示之變形例中電路封裝15A般,不僅將複合模製構件40的上表面41、進而也將複合模製構件40的側面42和基板20的側面27用磁性膜70覆蓋。由此,能夠進一步提高側面方向上的磁遮罩特性。
圖21為表示本發明之第六實施形態的電路封裝16之結構之截面圖。
如圖21所示,本實施形態的電路封裝16在追加了隔著金屬膜60覆蓋複合模製構件40的上表面41的磁性膜70這一點
上與第四實施形態的電路封裝14不同。其他結構與第四實施形態的電路封裝14相同,因此對同一要素附加同一符號,省略重複的說明。
本實施形態的電路封裝16中,作為電磁遮罩和磁遮罩的複合模製構件40的表面被作為電磁遮罩的金屬膜60和作為磁遮罩的磁性膜70覆蓋,能夠進一步提高電磁遮罩和磁遮罩特性。
以上對本發明較佳的實施形態進行了說明,但本發明不限定於上述實施形態,能夠在不脫離本發明的主旨的範圍內進行各種變更,此等當然也包含在本發明的範圍內。
準備中位粒徑(D50)為10μm的第一填料F1和中位粒徑(D50)為0.7μm的第二填料F2c。第一填料F1包含Fe為64重量%、Ni為36重量%的不變鋼材料,對其表面施加厚度50nm的Ag鍍層。第二填料F2包含耐熱性樹脂,對其表面施加厚度80nm的Ag鍍層。
接著,使聯苯型環氧樹脂、酚醛清漆型固化劑和催化劑(咪唑)在丁基卡必醇中溶解而調整黏結劑,將上述第一填料F1和第二填料F2c投入黏結劑中,用攪拌裝置進行攪拌、混合從而得到膏狀的複合密封材料。複合密封材料中的第一填料F1的混合比是50體積%,第二填料F2c的混合比是25體積%,黏結劑的混合比是25體積%。
接著,使用圖8所示的基板20實際製作了具有與電路封裝11相同的結構的實施例試樣1和2。作為基板20,使用平面尺寸為7.72mm×7.72mm、厚度為0.3mm的多層樹脂基板。而且,
於試樣1中,使圖8所示的電源圖案23G的寬度W1成為1.18mm;於試樣2中,使圖8所示的電源圖案23G的寬度W1成為2.26mm。因此,電源圖案23G的面積在試樣1中為1.4mm2,在試樣2中為5.1mm2。於試樣1中,電源圖案23G在基板20的表面21中所占的比例為約2.3%。於試樣2中,電源圖案23G在基板20的表面21中所占的比例為約8.6%。
另外,使用圖11所示的基板20實際製作了具有與電路封裝11相同結構的實施例試樣3。基板20的平面尺寸和厚度與試樣1和2相同。而且,使圖11所示的電源圖案23G的寬度W2成為0.52mm。因此,電源圖案23G的面積為8.0mm2,電源圖案23G在基板20的表面21中所占的比例為約13.5%。
進而,使用圖13所示的基板20實際製作了具有與電路封裝11相同結構的實施例試樣4。基板20的平面尺寸和厚度與試樣1和2相同。而且,使圖13所示的電源圖案23G的寬度W3成為0.44mm。因此,電源圖案23G的面積為12.8mm2,電源圖案23G在基板20的表面21中所占的比例為約21.5%。
關於複合模製構件40,試樣1~4都使用上述複合密封材料,用真空印刷法在基板20的頂面21形成複合模製構件40後,在100℃下加熱4小時從而除去溶劑,進而在180℃下進行了3小時的後固化。
另外,作為比較例,製作了代替上述複合密封材料地使用不具有磁性和導電性的一般的模製材料進行模製、並在其表面藉由濺射形成了厚度6μm的Cu膜的比較例試樣。Cu膜與接地圖案連接。
接著,將各試樣回流焊安裝在遮罩特性評價用基板上,藉由用近磁場測定裝置測定雜訊衰減量而對遮罩特性進行了評價。結果如圖22所示。
如圖22所示,確認了實施例試樣1在20MHz~150MHz的頻段和1.5GHz~2.4GHz的頻段中,與比較例試樣相比雜訊衰減量更大。另外,確認了實施例試樣2~4在測定的全頻段(20MHz~2.4GHz)中,與比較例試樣相比雜訊衰減量更大。確認了特別是在超過80MHz的頻段中,電源圖案23G的佔有率越大,則得到越大的雜訊衰減量。另外,實施例1~4都在20MHz附近得到了接近檢測極限的雜訊衰減量。進而,實施例試樣3中在1GHz附近得到了接近檢測極限的雜訊衰減量,實施例試樣4中在已測定的全頻段中得到了接近檢測極限的雜訊衰減量。
11‧‧‧電路封裝
20‧‧‧基板
21‧‧‧表面
22‧‧‧背面
23‧‧‧焊盤圖案
23G‧‧‧電源圖案
24‧‧‧焊料
25‧‧‧內部配線
26‧‧‧外部端子
27‧‧‧側面
31、32‧‧‧電子零件
40‧‧‧複合模製構件
42‧‧‧(複合模製構件之)側面
51、52‧‧‧絕緣塗層
Claims (18)
- 一種電路封裝,其特徵在於具備:基板,其具有電源圖案;電子零件,其搭載於上述基板的表面上;模製構件,其以將上述電子零件嵌入的方式覆蓋上述基板的上述表面,並具有導電性;和絕緣塗層,其係使上述電子零件及其端子電極與上述模製構件彼此絕緣;上述電源圖案包含在上述基板的上述表面露出的第一電源圖案;上述模製構件與上述第一電源圖案相接;上述模製構件包含樹脂材料、以及與上述樹脂材料混合的含軟磁性金屬材料之第一填料;上述第一填料的表面係由導電性比上述第一填料更高的金屬塗層覆蓋。
- 如請求項1之電路封裝,其中,上述第一電源圖案在上述基板的上述表面中所占的比例為2%以上。
- 如請求項2之電路封裝,其中,上述第一電源圖案在上述基板的上述表面中所占的比例為8%以上。
- 如請求項1之電路封裝,其中,上述第一電源圖案係配置在上述基板的上述表面的至少一個角部。
- 如請求項4之電路封裝,其中,上述第一電源圖案係配置在上述基板的上述表面的至少兩個角部。
- 如請求項5之電路封裝,其中,上述兩個角部位於對角之位置。
- 如請求項1之電路封裝,其中,上述第一電源圖案係沿上述基 板的上述表面之至少一邊配置。
- 如請求項7之電路封裝,其中,上述第一電源圖案係沿上述基板的上述表面之至少兩邊配置。
- 如請求項8之電路封裝,其中,上述兩邊彼此相對。
- 如請求項1之電路封裝,其中,上述電源圖案包括在上述基板的側面露出的第二電源圖案;上述模製構件進一步與上述第二電源圖案相接。
- 如請求項10之電路封裝,其中,上述基板的上述側面包括側面上部、和與上述側面上部相比更突出的側面下部;上述第二電源圖案係在上述基板的上述側面上部露出;上述模製構件不覆蓋上述基板的上述側面下部,而覆蓋上述基板的上述側面上部。
- 如請求項1之電路封裝,其中,進一步具備覆蓋上述模製構件且導電性比上述模製構件更高的金屬膜。
- 如請求項1之電路封裝,其中,進一步具備覆蓋上述模製構件,且磁導率比上述模製構件更高的磁性膜。
- 如請求項1之電路封裝,其中,上述模製構件進一步包含中位粒徑比上述第一填料更小的第二填料;上述第二填料的表面係由金屬塗層覆蓋。
- 如請求項14之電路封裝,其中,上述第二填料包含磁性材料。
- 如請求項14之電路封裝,其中,上述第二填料包含導電性材料。
- 如請求項14之電路封裝,其中,上述第二填料包含絕緣材料。
- 如請求項1之電路封裝,其中,上述第一填料包含含有32~39重量%之於Fe中以Ni為主成分的金屬材料之材料。
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