CN109119380A - 使用复合磁性密封材料的电子电路封装 - Google Patents
使用复合磁性密封材料的电子电路封装 Download PDFInfo
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- CN109119380A CN109119380A CN201810660826.9A CN201810660826A CN109119380A CN 109119380 A CN109119380 A CN 109119380A CN 201810660826 A CN201810660826 A CN 201810660826A CN 109119380 A CN109119380 A CN 109119380A
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- electronic circuit
- circuit package
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- composite molding
- component
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Classifications
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- C—CHEMISTRY; METALLURGY
- C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
- C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
- C08K3/00—Use of inorganic substances as compounding ingredients
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
- H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
- H01F1/03—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity
- H01F1/12—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials
- H01F1/14—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys
- H01F1/147—Alloys characterised by their composition
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- H01F1/14733—Fe-Ni based alloys in the form of particles
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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Abstract
本说明书所公开的电子电路封装具备:基板,具有电源图案;电子部件,被搭载于所述基板的表面;以及复合成型构件,其以埋入所述电子部件的方式覆盖所述基板的所述表面,连接于所述电源图案并具有导电性。所述复合成型构件包含树脂材料和第1填料,该第1填料配合于所述树脂材料,并在Fe中含有32~39重量%的以Ni作为主成分的金属材料。
Description
技术领域
本发明涉及一种电子电路封装,特别是涉及使用了复合磁性材料作为成型材料的电子电路封装。
背景技术
近年来,智能手机等电子设备倾向于采用高性能的无线通信电路以及数字芯片并且所使用的半导体IC的工作频率也上升。再有,具有以最短配线来连接多个半导体IC的2.5D结构或3D结构的系统级封装(SIP:system in package)化在不断加速,并且预测电源系统电路的模块化今后也会有所增长。进一步,多个电子部件(电感器、电容器、电阻、滤波器等被动部件;晶体管、二极管等主动部件;半导体IC等集成电路部件;其它电子电路构成所必要的部件的总称)被模块化的电子电路模块也被预测为在今后会越发增加,总称这些的电子电路封装正处于由智能手机等电子设备的高功能化以及小型化、薄型化而被高密度安装的倾向。然而这些倾向显示出由噪音引起的误动作以及电波干扰变得显著,并且就现有的噪音对策而言要防止误动作或电波干扰是很困难的。因此,近年来,电子电路封装的自屏蔽(Self Shield)化在发展,并且有方案提出通过导电性膏体或者电镀或溅射法的电磁屏蔽并且使之实用化,但是今后会进一步要求更高的屏蔽特性。
为了实现上述目的,在近些年有方案提出使成型材料自身具有磁屏蔽特性的电子电路封装。例如,在日本特开平10-64714号公报中,作为电子电路封装用的成型材料,公开有添加了具有氧化膜的软磁体粉末的复合磁性密封材料。
然而,现有的复合磁性密封材料会有所谓热膨胀系数大的问题。因此,在复合磁性密封材料与封装基板或者电子部件之间会产生热膨胀系数的不匹配,其结果就会有时会在模具成型后具有条状(stripshape)的集合基板的状态下产生大的翘曲,有时在个片化之后的电子电路封装在安装回流焊的时候发生在连接性上产生问题的程度大的翘曲。以下针对该现象进行说明。
近年来,对于半导体封装或电子部件模块来说,有各种的结构体的提案以及实用化,目前的主流一般是将半导体IC等电子部件安装于有机多层基板上并且以树脂密封材料对其上部以及周围实行模具成型后得到的结构。具有如此结构的半导体封装或者电子部件模块是在以集合基板的状态进行模具成型后通过由切割等进行的个片化处理来制作的。
该结构因为物性不同的有机多层基板和树脂密封材料构成所谓双金属材料,所以会由于热膨胀系数之差、玻璃化转变、成型材料的固化收缩等的原因而会发生翘曲。为了抑制该现象,有必要尽可能使热膨胀系数等物性一致。近年来,用于半导体封装或电子电路模块的有机多层基板根据低背化要求而越来越倾向于发展薄层化以及多层化。为了既要达到该要求又要实现为了确保薄基板处理性的高刚性以及低热膨胀化,一般有时使用玻璃化转变温度高的基板材料有时将热膨胀率低的填料添加于基板材料并且使用更低热膨胀系数的玻璃布。
另外,因为被搭载于基板的半导体IC以及电子部件与成型材料之间的物性差也会导致应力产生,所以会引起成型材料的界面剥离、电子部件或成型材料的龟裂等各种各样的问题。将硅使用于半导体IC,硅的热膨胀系数为3.5ppm/℃,陶瓷电容器以及电感器等的烧成型贴片部件的热膨胀系数为10ppm/℃的程度。
因此,对于成型材料说也要求低热膨胀化,市售有突破10ppm/℃的那样的材料。作为使成型材料低热膨胀化的手法当然是采用低热膨胀的环氧树脂,使用以高填充率将0.5ppm/℃的热膨胀系数非常低的熔融二氧化硅配合于密封树脂中的手法。
另一方面,一般的磁性材料其热膨胀系数高。因此,如日本特开平10-64714号公报中所记载的那样,将一般的软磁体粉末添加到成型树脂的复合磁性密封材料存在不能达到目标的低热膨胀系数的问题。
另外,在日本特开昭59-132196号公报中,公开有通过由磁性成型树脂来对电子电路进行成型并用金属盒覆盖整体从而提高屏蔽性的电子电路封装。
然而,日本特开昭59-132196号公报所记载的电子电路封装中,因为是用金属盒覆盖整体,所以难以实现低背化。另外,因为在金属盒上设置多个孔并且金属盒没有连接于基板的接地图案等,所以不能够获得充分的屏蔽效果。
现有技术文献
专利文献
专利文献1:日本专利申请公开平10-64714号公报
专利文献2:日本专利申请公开昭59-132196号公报
发明内容
因此,本发明的一个目的在于提供一种将热膨胀系数低的复合磁性密封材料作为成型材料来使用的电子电路封装。
另外,本发明的其它目的在于提供一种既实现低背化又能够获得高屏蔽特性的电子电路封装。
本发明的电子电路封装具备:基板,其具有电源图案;电子部件,其被搭载于上述基板的表面;以及成型构件,其以埋入上述电子部件的形式覆盖上述基板的上述表面,连接于上述电源图案并具有导电性,上述复合成型构件包含树脂材料和第1填料,该第1填料配合于上述树脂材料并在Fe中含有32~39重量%的将Ni作为主成分的金属材料。
根据本发明,因为使用了热膨胀系数低的第1填料,所以大幅度地减小了由复合磁性密封材料构成的成型构件的热膨胀系数,例如能够控制在15ppm/℃以下。因此,能够防止基板的翘曲、成型材料的界面剥离、成型材料的龟裂等。而且,成型构件因为具有导电性和磁性,所以能够由成型构件本身来获得兼有电磁屏蔽功能和磁屏蔽功能的复合屏蔽结构。
在本发明中,上述第1填料的表面也是可以被导电性高于上述第1填料的金属涂层(metal coat)包覆。由此,能够进一步降低复合成型构件的体积电阻。
在本发明中,上述复合成型构件可以进一步包含小于上述第1填料的第2填料。在此情况下,上述第2填料的表面可以被金属涂层包覆。由此,能够更进一步降低复合成型构件的体积电阻。
在本发明中,上述第2填料可以是由磁性材料构成的填料,并且既可以是由导电性材料构成的也可以是由绝缘材料构成的。
在本发明中,上述第1以及第2填料在上述复合成型构件中的配合比例可以是50体积%以上且85体积%以下。另外,相对于上述第1填料和上述第2填料的合计,上述第1填料的量可以是50体积%以上且99体积%以下。
本发明所涉及的电子电路封装可以进一步具备上述电子部件以及使其端子电极与上述复合成型构件互相绝缘的绝缘涂层。由此,就能够防止电子部件与复合成型构件的短路缺陷。
在本发明中,上述复合成型构件既可以与露出于上述基板的上述表面的上述电源图案相接触,也可以与露出于上述基板的上述侧面的上述电源图案相接触。
在本发明中,上述基板的侧面包含侧面上部和比上述侧面上部突出的侧面下部,上述电源图案露出于上述基板的上述侧面上部,上述复合成型构件可以不覆盖上述基板的上述侧面下部而覆盖上述基板的上述侧面上部。由此,能够在对基板实施个片化之前,将复合成型构件连接于露出于基板的侧面的电源图案。
本发明所涉及的电子电路封装可以进一步具备覆盖上述复合成型构件并且导电性高于上述复合成型构件的金属膜。由此,可以进一步提高电磁屏蔽特性。
本发明所涉及的电子电路封装可以进一步具备覆盖上述复合成型构件并且导磁率高于上述复合成型构件的磁性膜。由此,可以进一步提高磁屏蔽特性。
在本发明中,上述金属材料可以相对于上述第1填料的整体进一步包含0.1~8重量%的Co。由此,可以进一步降低由复合磁性密封材料构成的磁性成型树脂的热膨胀系数。
在本发明中,在上述电子部件的上部的上述复合成型构件的厚度可以为50μm以上,可以是100μm以上且300μm以下。由此,能够实现低背化并且与以金属膜屏蔽一般的成型构件表面的结构相比能够获得更高的屏蔽特性。
附图说明
接下来,结合附图通过特定的优选实施方式来进一步说明上述本发明的技术特征和优点。
图1是表示本发明的第1实施方式所涉及的电子电路封装结构的截面图。
图2~图6是用于说明图1所示的电子电路封装的制造方法的工序图。
图7是用于说明第1填料结构的截面图。
图8A~图8C是用于说明第2填料结构的截面图。
图9是表示本发明的第2实施方式所涉及的电子电路封装的结构的截面图。
图10是表示本发明的第3实施方式所涉及的电子电路封装的结构的截面图。
图11是表示本发明的第4实施方式所涉及的电子电路封装的结构的截面图。
图12是表示本发明的第5实施方式所涉及的电子电路封装的结构的截面图。
图13是表示本发明的第6实施方式所涉及的电子电路封装的结构的截面图。
图14是表示本发明的第7实施方式所涉及的电子电路封装的结构的截面图。
图15是表示本发明的第8实施方式所涉及的电子电路封装的结构的截面图。
图16是表示本发明的第8实施方式的变形例所涉及的电子电路封装的结构的截面图。
图17是表示本发明的第9实施方式所涉及的电子电路封装的结构的截面图。
图18是表示实施例的测定结果的图表。
具体实施方式
以下参照附图并就本发明的优选实施方式进行详细说明。
<第1实施方式>
图1是表示本发明的第1实施方式所涉及的电子电路封装11的结构的截面图。
如图1所示,本实施方式所涉及的电子电路封装11具备基板20;搭载于基板20的多个电子部件31、32;以及以埋入电子部件31、32的方式覆盖基板20的表面21的具有导电性的复合成型构件40。
关于本实施方式所涉及的电子电路封装11的种类并没有特别的限定,例如可以列举具有处理高频信号的高频模块、进行电源控制的电源模块、具有2.5D结构或3D结构的系统级封装(SIP:system in package)、或无线通信用或者数字电路用半导体封装等。在图1中,只表示了2个电子部件31、32,但是实际上内藏有更多的电子部件。
基板20具有多根配线埋入到内部的双面以及多层配线结构,不论FR-4、FR-5、BT、氰酸酯树脂(cyanate ester)、酚醛树脂(phenol)、聚酰亚胺(imide)等热固性树脂基底的有机基板、液晶聚合物等热可塑性树脂基底的有机基板、LTCC基板、HTCC基板、挠性基板等种类。在本实施方式中,基板20为4层结构,并具有形成于基板20的表面21以及背面22的配线层、埋入到内部的2层配线层。在基板20的表面21上形成有多个焊盘图案23。焊盘图案23是为了与电子部件31、32相连接的内部电极,两者经由焊锡24(或者导电性膏体)而被电连接以及机械连接。作为一个例子,电子部件31为控制器等的半导体芯片,电子部件32是电容器或线圈等被动部件。电子部件的一部分(例如被薄型化了的半导体芯片等)可以被埋入到基板20。
焊盘图案23经由形成于基板20内部的内部配线25而被连接于形成于基板20的背面22的外部端子26。在实际使用时,电子电路封装11被安装于未图示的母板等,母板上的焊盘图案和电子电路封装11的外部端子26被电连接。作为构成焊盘图案23、内部配线25以及外部端子26的导体材料,可以是铜、银、金、镍、铬、铝、钯、铟等金属或者它们的金属合金,也可以是将树脂或玻璃作为粘结剂的导电材料,不过在基板20为有机基板或者挠性基板的情况下,从成本和导电率等观点出发优选使用铜、银。作为这些导电材料的形成方法可以使用印刷、电镀、箔层压、溅射、蒸镀、喷墨等方法。另外,在形成好的焊盘图案23上可以用电镀或溅射、蒸镀等方法来形成Au、Pd、Ag、Sn等低电阻金属,或者也可以形成Cu-OSP等抗氧化膜。
电子部件31、32及其端子电极以及图案24被绝缘涂层51、52覆盖,由此,从复合成型构件40起被绝缘。在图1所示的例子中,绝缘涂层51被设置于电子部件31与基板20之间,但是也可以以覆盖电子部件31整体的形式设置绝缘涂层51。针对电子部件32,整体被绝缘涂层52覆盖。
如图1所示,从焊盘图案23引出的电源图案23G不被绝缘涂层51、52覆盖而露出,并与复合成型构件40相接触。电源图案23G典型的例子是能提供接地电位的接地图案,但只要是提供固定电位的图案的话并不限定于接地图案。
复合成型构件40是通过以埋入电子部件31、32的方式覆盖基板20的表面21而进行设置。复合成型构件40具有导电性并具有高导磁率。由此,除了作为成型构件的通常的功能之外,即使作为电磁屏蔽以及磁屏蔽也能够行使其功能。在本实施方式中,复合成型构件40的侧面42和基板20的侧面27构成同一个平面。关于复合成型构件40的细节将在后面进行叙述,但与现有的磁性成型构件相比是由热膨胀系数非常小(例如15ppm/℃以下)的复合材料构成。
接下来,就本实施方式所涉及的电子电路封装11的制造方法进行说明。
图2~图6是用于说明电子电路封装11的制造方法的工序图。
首先,如图2所示准备具有多层配线结构的集合基板20A。在集合基板20A的表面21上形成多个焊盘图案23以及电源图案23G,在集合基板20A的背面22上形成多个外部端子26。另外,在集合基板20A的内层形成多根内部配线25。另外,图2~图5所表示的虚线a是指在之后的切割工序中应该被切断的部分。
接下来,如图2所示,以被连接于焊盘图案23的形式将多个电子部件31、32搭载于集合基板20A的表面21。具体而言,可以通过在将焊锡24提供给焊盘图案23上之后搭载电子部件31、32,并进行回流焊从而将电子部件31、32连接于焊盘图案23。
接下来,如图3所示,用绝缘涂层51、52来覆盖电子部件31、32、电子部件31、32的端子电极以及焊锡24。此时,有必要做成电源图案23G的至少一部分不被绝缘涂层51、52覆盖而露出的状态。
接下来,如图4所示,以埋入电子部件31、32的形式通过复合成型构件40来覆盖集合基板20A的表面21。作为复合成型构件40的形成方法可以使用传递模塑法(transfermolding)、压缩模塑法(compression molding)、注塑成型法(injection molding)、铸造法、真空铸造法、分配法(dispense)、狭缝喷嘴法(slit nozzle)等。之后,如图5所示,通过研磨复合成型构件40的上表面从而调整复合成型构件40的厚度。关于复合成型构件40的厚度并没有特别的限定,但是包含电子部件31、32的所有电子部件中最高的电子部件的上部的复合成型构件40的厚度优选为50μm以上,更加优选为100μm以上。由此,能够充分减小复合成型构件40的体积电阻率。但是,在本发明中,研磨复合成型构件40的上表面并不是必须的。
于是,如图6所示,如果通过沿着虚线a切断集合基板20A从而将基板20进行个片化的话,则完成了本实施方式所涉及的电子电路封装11。
接下来,针对构成复合成型构件40的成型材料进行详细地说明。
构成复合成型构件40的成型材料与一般的成型材料不同,具有磁性以及导电性。这样,复合成型构件40因为连接于电源图案23G,所以能够提供接地电位等固定电位。由此,能够提供兼有磁屏蔽功能和电磁屏蔽功能的复合屏蔽结构。
复合成型构件40包含粘结剂、具有磁性以及导电性的第1填料。虽然没有特别的限定,但是优选粘结剂将热固性树脂材料作为主成分。具体而言优选将环氧树脂、酚醛树脂、聚氨酯树脂、硅酮树脂或者聚酰亚胺树脂作为主成分,进一步优选使用被用于环氧树脂或者酚醛树脂类半导体密封材料的主剂以及固化剂。
最优选的是在末端持有环氧基的环氧树脂,并能够与各种固化剂以及固化促进剂相组合。作为环氧树脂的例子可以列举双酚(bisphenol)A型、双酚F型、苯氧基、萘、多官能型(双环戊二烯dicyclopentadiene)、联苯型(2个官能团)以及特殊结构型,能够低热膨胀化的联苯型、萘型、双环戊二烯型等是有用的。作为固化剂或者固化促进剂的例子,可以列举胺类化合物脂环族二胺、芳香族二胺、其它胺类(咪唑、叔胺)、酸酐类化合物(主要是高温固化剂)、酚醛树脂(酚醛(novolak)型、甲酚醛(cresol novolac)型等)、氨基树脂、双氰胺(dicyandiamide)、路易斯酸络合物。材料的混炼方法可以适用使用捏合机或三辊轧机、混合搅拌机等公知的方法。
图7是表示第1填料F1的一个例子的截面图。第1填料F1的中值粒径(median-diameter)(D50)为d1,在其表面上优选施以导电性比第1填料F1更高的金属涂层M。如果在第1填料F1的表面上施以金属涂层M则能够将复合成型构件40的体积电阻进一步低电阻化。作为金属涂层M的材料可以列举将Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu作为主成分的材料。形成于第1填料F1的金属涂层M的厚度优选为1~3000nm的范围。
第1填料F1由Fe-Ni系材料构成,包含32重量%以上且39重量%以下的以Ni作为主成分的软磁性金属材料。占有剩下的61~68重量%的元素为Fe。这样的Fe-Ni系材料被称作为“因瓦(invar)合金材料”。通过使用因瓦合金材料作为第1填料F1的材料,从而可以将复合成型构件40的热膨胀系数控制为例如15ppm/℃以下,并且能够获得高的磁特性。以Ni作为主成分的软磁性金属材料可以含有少量的Co。即,Ni的一部分可以由Co置换。由此,可以进一步降低复合磁性密封材料的热膨胀系数。Co的添加量相对于第1填料F1的整体优选为0.1重量%以上且8重量%以下。
关于第1填料F1的形状并没有特别的限定,但是为了高填充化可以做成球状,也可以以成为最密填充的形式混合调配多个粒度分布的填料。另外,如果将第1填料F1做成大致球形,能够减少相对于电子部件的成型时的损伤。特别是为了最密填充化或者高填充化,优选第1填料F1的形状为完全球状。第1填料F1优选振实密度(tap density)高且粉末比表面积小。作为第1填料F1的形成方法是水雾化(water atomization)法、气体雾化(gasatomization)法、离心盘雾化(centrifugal disk atomization)法等的方法,其中尤其优选能够获得高振实密度且能够减小比表面积的气体雾化法。
除了第1填料F1之外,复合成型构件40还可以包含由图8A所示的磁性材料构成的第2填料F2a、由图8B所示的导电性材料构成的第2填料F2b、或者由图8C所示的绝缘材料构成的第2填料F2c。第2填料F2a、F2b、F2c的中值粒径d2小于第1填料F1的中值粒径d1。由此,就能够提高包含于复合成型构件40中的填料的填充率。关于第2填料F2a、F2b、F2c,也优选其表面被金属涂层M包覆。由此,能够进一步使复合成型构件40的体积电阻低电阻化。金属涂层M的材料以及厚度可以与对第1填料F1实施了金属涂层M的材料以及厚度相同。包含第1填料F1以及第2填料F2a、F2b、F2c的总填料相对于粘结剂的配合比例优选为50~85体积%。另外,第1填料F相对于总填料的配合比例优选为50~99体积%。
图8A所示的第2填料F2a由磁性材料构成。构成第2填料F2a的磁性材料可以使用选自Fe、Fe-Co系合金、Fe-Ni系合金、Fe-Al系合金、Fe-Si系合金、Ni-Zn系尖晶石型铁氧体(spinel ferrite)、Mn-Zn系尖晶石型铁氧体、Ni-Cu-Zn系尖晶石型铁氧体、Mg系尖晶石型铁氧体、钇铁系石榴石型铁氧体(garnet ferrite)中至少一种材料。另外,第2填料F2a的材料可以与第1填料F1相同。形成于第2填料F2a的金属涂层M的厚度优选为1~2000nm的范围。
图8B所示的第2填料F2b由导电性材料构成。构成第2填料F2b的导电性材料可以使用以Au、Ag、Al、Mg、W、Mo、Zn、Ni、Fe、Pt、Pd、Sn、Cu作为主成分的材料。即使在使用导电性材料作为第2填料F2b的材料的情况下,可以进一步用金属涂层M包覆其表面。
图8C所示的第2填料F2c由绝缘材料构成。构成第2填料F2c的绝缘材料可以使用熔融二氧化硅、碳酸钙、氧化镁、氧化铝、氧化钛、耐热性树脂等。耐热性树脂可以是热固性树脂,也可以是热可塑性树脂。特别优选使用SiO2、ZrW2O8、(ZrO)2P2O7、KZr2(PO4)3或者Zr2(WO4)(PO4)2等热膨胀系数小于第1填料F1的材料或者热膨胀系数具有负值的材料。如果将这样的第2填料F2c添加到复合成型构件40,则能够进一步降低热膨胀系数。另外,也可以添加如氧化铝、氧化镁那样的阻燃剂、用于着色的炭黑或颜料或者染料、用于提高顺滑性、流动性以及分散/混炼性而进行100nm以下的粒径的表面处理后的纳米二氧化硅、用于提高脱模性的蜡成分等。形成于第2填料F2c的金属涂层M的厚度优选为1~2000nm的范围。另外,在本发明中,构成复合成型构件40的复合材料不是必须包含第2填料F2a、F2b或者F2c。
构成复合成型构件40的复合材料的形态既可以是液体状及固体状的任意种,根据对应于成型方法的主剂以及固化剂的选择而形态会有所不同。对于固体状的复合材料,如果是传递模塑用则可做成药片(tablet)形状,如果是注塑成型用或者压缩模塑用则可做成颗粒状。另外,关于使用了复合材料的成型方法有传递模塑法、压缩模塑法、注塑成型法、铸造法、真空铸造法、真空印刷法、印刷法、分配法、狭缝喷嘴法等,可以适当选择。成型条件可以通过所使用的主剂、固化剂以及固化促进剂的组合适当选择,成型后也可以根据需要实施后固化(after cure)。
如以上所说明的那样,本实施方式所涉及的电子电路封装11因为复合成型构件40具有导电性,因此复合成型构件40自身作为电磁屏蔽发挥功能。由此,电子部件31、32发出的电磁波或者从外部飞来的电磁波在复合成型构件40的内部被转换成电流,可经由电源图案23G流到外部。而且,因为包含于复合成型构件40中的第1填料F1是由因瓦合金材料构成的,所以既具有磁屏蔽特性又能够防止伴随于温度变化的基板的翘曲、成型材料的界面剥离、成型材料的龟裂等。
<第2实施方式>
图9是表示本发明的第2实施方式所涉及的电子电路封装12的结构的截面图。
如图9所示,本实施方式所涉及的电子电路封装12中,复合成型构件40的平面尺寸只比基板20的平面尺寸大一点点,由此,基板20的侧面27被复合成型构件40覆盖。内部配线25的一部分即电源图案25G露出于基板20的侧面27,所露出的电源图案25G与复合成型构件40接触。由此,通过电源图案25G对复合成型构件40提供固定电位(典型地为接地电位)。在本实施方式中,不管是在基板20的表面21不设置电源图案23G还是设置有电源图案23G的情况下,都是用绝缘涂层51、52覆盖,并且由此电源图案23G与复合成型构件40不相接触。其它结构中,因为与第1实施方式所涉及的电子电路封装11相同,所以对相同要素标注相同符号并省略重复的说明。
本实施方式所涉及的电子电路封装12因为露出于基板20的侧面27的电源图案25G与复合成型构件40接触,所以没有必要使电源图案23G露出于基板20的表面21。由此,例如因为能够将绝缘涂层51、52形成于基板20的表面21的整个面,所以能够简化制造工艺。
本实施方式所涉及的电子电路封装12可以通过在经切断集合基板20A而将基板20个片化之后,将复合成型构件40形成于基板20的上表面21以及侧面27来制作。
<第3实施方式>
图10是表示本发明的第3实施方式所涉及的电子电路封装13的结构的截面图。
如图10所示,在本实施方式所涉及的电子电路封装13中,基板20的侧面27成为阶梯状。具体而言,侧面下部27b具有比侧面上部27a突出的形状。电源图案25G露出于侧面上部27a,所露出的电源图案25G与复合成型构件40接触。电源图案25G不露出于侧面下部27b,侧面下部27b和复合成型构件40的侧面42构成同一平面。其它结构与第2实施方式所涉及的电子电路封装12相同,因此对相同要素标注相同符号并省略重复的说明。
本实施方式所涉及的电子电路封装13中,因为露出于基板20的侧面上部27a的电源图案25G与复合成型构件40接触,因此没有必要使电源图案23G露出于基板20的表面21。由此,与第2实施方式相同,因为能够将绝缘涂层51、52形成于基板20的表面21的整个面,因此能够简化制造工艺。
本实施方式所涉及的电子电路封装13可以通过在将构成侧面上部27a的沟槽形成于集合基板20A并以掩埋该沟槽的形式将复合成型构件40形成于基板20的上表面21之后,进行个片化来进行制作。
<第4实施方式>
图11是表示本发明的第4实施方式所涉及的电子电路封装14的结构的截面图。
如图11所示,本实施方式所涉及的电子电路封装14中,被设置于基板20的表面21的电源图案23G与复合成型构件40相接触,在这一点上与第2实施方式所涉及的电子电路封装12不同。其它结构与第2实施方式所涉及的电子电路封装12相同,所以对相同要素标注相同符号并省略重复的说明。
本实施方式所涉及的电子电路封装14中,因为复合成型构件40在基板20的上表面21以及侧面27的两面连接于电源图案23G、25G,因此与第2实施方式所涉及的电子电路封装12相比,能够进一步使复合成型构件40的电位(典型地为接地电位)稳定化。
<第5实施方式>
图12是表示本发明的第5实施方式所涉及的电子电路封装15的结构的截面图。
如图12所示,本实施方式所涉及的电子电路封装15中,被设置于基板20的表面21的电源图案23G与复合成型构件40相接触,在这一点上与第3实施方式所涉及的电子电路封装13不同。其它结构与第3实施方式所涉及的电子电路封装13相同,因此对相同要素标注相同符号并省略重复的说明。
本实施方式所涉及的电子电路封装15中,复合成型构件40在基板20的上表面21以及侧面27a的两面连接于电源图案23G、25G,因此与第3实施方式所涉及的电子电路封装13相比,能够进一步使复合成型构件40的电位(典型地为接地电位)稳定化。
<第6实施方式>
图13是表示本发明的第6实施方式所涉及的电子电路封装16的结构的截面图。
如图13所示,本实施方式所涉及的电子电路封装16中,在基板20的表面21追加有独立的电源图案29G,在这一点上与第1实施方式所涉及的电子电路封装11不同。其它结构与第1实施方式所涉及的电子电路封装11相同,因此对相同要素标注相同符号并省略重复的说明。
电源图案29G是用于对复合成型构件40提供固定电位的专用图案。电源图案29G在基板20的上表面21不连接于其它焊盘图案23或配线而被独立设置。与电源图案23G相同的固定电位经由形成于基板20的内部的内部配线25被提供给电源图案29G。如本实施方式所例示的那样,作为用于对复合成型构件40提供固定电位的电源图案,能够不仅使用从焊盘图案23引出的电源图案23G还使用独立的专用电源图案29G。由此,可以进一步使复合成型构件40的电位(典型地为接地电位)稳定化。
<第7实施方式>
图14是表示本发明的第7实施方式所涉及的电子电路封装17的结构的截面图。
如图14所示,本实施方式所涉及的电子电路封装17中,追加了覆盖复合构件40的上表面41以及侧面42和基板20的侧面27的金属膜60,在这一点上与第1实施方式所涉及的电子电路封装11不同。电源图案25G露出于基板20的侧面27,其与金属膜60相接触。其它结构与第1实施方式所涉及的电子电路封装11相同,所以对相同要素标注相同符号,并省略重复的说明。
金属膜60与复合成型构件40一起作为电磁屏蔽发挥功能,优选将选自Au、Ag、Cu以及Al中的至少一种金属作为主成分。金属膜60优选尽可能为低电阻,鉴于成本等原因最优选使用Cu。金属膜60的电阻值有必要至少低于复合成型构件40的电阻值。另外,金属膜60的外侧表面优选被由SUS、Ni、Cr、Ti、黄铜等防腐蚀性的金属、或者环氧树脂、酚醛树脂、聚酰亚胺树脂、聚氨酯树脂、硅酮树脂等树脂构成的氧化防止覆膜覆盖。这是因为金属膜60会在热、湿度等的环境条件下发生氧化劣化,所以为了抑制和防止该氧化劣化,优选实施上述处理。金属膜60的形成方法可以从溅射法、蒸镀法、无电解电镀法、电解电镀法等公知的方法中适当选择,也可以在形成金属膜60之前实施提高紧密附着性的前处理,即等离子处理、偶联处理、喷砂处理、蚀刻处理等。进一步,作为金属膜60的基底,可以事先薄薄地形成钛或铬、SUS等的高紧密附着性金属膜。
这样,本实施方式所涉及的电子电路封装17具备连接于电源图案25G的金属膜60,因此与第1实施方式所涉及的电子电路封装11相比,相对来说能够进一步使复合成型构件40的电位(典型地为接地电位)稳定化。
<第8实施方式>
图15是表示本发明的第8实施方式所涉及的电子电路封装18的结构的截面图。
如图15所示,本实施方式所涉及的电子电路封装18中,追加了覆盖复合成型构件40的上表面41的磁性膜70,在这一点上与第1实施方式所涉及的电子电路封装11不同。其它结构与第1实施方式所涉及的电子电路封装11相同,因此对相同要素标注相同符号并省略重复的说明。
磁性膜70是由下述材料构成,即,由磁性填料分散于热固性树脂材料中得到的复合磁性材料构成的膜、由软磁性材料或铁氧体构成的薄膜、或者箔或大薄片(bulk sheet),并作为第2磁屏蔽发挥功能。磁性膜70的有效导磁率至少需要大于复合成型构件40的有效导磁率,优选为2倍以上。
在作为磁性膜70选择由复合磁性材料构成的膜的情况下,作为热固性树脂材料可以使用环氧树脂、酚醛树脂、硅酮树脂、邻苯二甲酸二烯丙酯(diallyl phthalate)树脂、聚酰亚胺树脂、聚氨酯树脂等,并可以使用印刷法、成型法、狭缝喷嘴涂布法、喷涂法、分配法、转移法、压缩模塑法、使用未固化的薄片状树脂的层压法等厚膜制法而形成。通过使用热固性材料,从而就能够提高耐热性、绝缘性、耐冲击性、落下强度等电子电路封装所要求的可靠性。
另外,作为磁性填料优选使用铁氧体或者软磁性金属,特别优选使用块体下的导磁率高的软磁性金属。作为铁氧体或者软磁性金属,可以列举选自Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1种或者2种以上的金属、或者其氧化物。作为具体例子可以列举Ni-Zn系和Mn-Zn系以及Ni-Cu-Zn系等的铁氧体、坡莫合金(permalloy)(Fe-Ni合金)、超级坡莫合金(superpermalloy)(Fe-Ni-Mo合金)、铁硅铝(sendust)(Fe-Si-Al合金)、Fe-Si合金、Fe-Co合金、Fe-Cr合金、Fe-Cr-Si合金、Fe-Ni-Co合金、Fe等。关于磁性填料的形状并没有特别的限定,但是为了高填充化而制成球状,也可以以成为最密填充的形式混合调配多种粒度分布的填料。为了最大限度地取得导磁率实分量的屏蔽效果和导磁率虚分量的损耗的热变换效果,而优选进一步使长宽比为5以上的扁平粉末取向而形成。
为了提高流动性和紧密附着性,磁性填料的表面可以由Si、Al、Ti、Mg等金属的氧化物或者有机材料进行绝缘包覆。绝缘涂层可以通过在磁性填料的表面包覆处理热固性材料,或者也可以通过金属醇盐的脱水反应来形成氧化膜,最优选形成氧化硅的涂层包覆膜。更加优选进一步在其上实施有机官能性偶联处理。
复合磁性材料可以通过使用印刷法、成型法、狭缝喷嘴涂布法、喷涂法、分配法、使用未固化的薄片状树脂的层压法等公知的方法来形成于复合成型构件40的上表面41。
另外,在作为磁性膜70选择由软磁性材料或者铁氧体构成的薄膜的情况下,可以使用Fe、Ni、Zn、Mn、Co、Cr、Mg、Al、Si中的1种或者2种以上的金属、或者它们的氧化物,除了溅射法和蒸镀法等薄膜制法之外还可以使用电镀法、喷涂法、AD法、热喷涂法等来形成于复合成型构件40的上表面41。在此情况下,磁性膜70的材料可以从所必要的导磁率和频率适当选择,但是为了提高低频(kHz~100MHz)侧的屏蔽效果,最优选为Fe-Co、Fe-Ni、Fe-Al、Fe-Si系的合金。另外,为了提高高频(50~数百MHz)的屏蔽效果而最优选为NiZn、MnZn、NiCuZn等的铁氧体膜或者Fe。
进一步,在作为磁性膜70而使用箔或者大薄片(bulk sheet)的情况下,如果预先将箔或者大薄片设置于形成复合成型构件40的时候的模具,则能够将由箔或者大薄片构成的磁性膜70直接形成于复合成型构件40的上表面41。
这样,本实施方式所涉及的电子电路封装18将导磁率高于复合成型构件40的磁性膜70设置于复合成型构件40的上表面41,所以能够进一步提高磁屏蔽特性。另外,如图16所表示的变形例所涉及的电子电路封装18A那样,可以用磁性膜70不仅覆盖复合成型构件40的上表面41而且还进一步覆盖复合成型构件40的侧面42或基板20的侧面27。由此,能够进一步提高侧面方向上的磁屏蔽特性。
<第9实施方式>
图17是表示本发明的第9实施方式所涉及的电子电路封装19的结构的截面图。
如图17所示,本实施方式所涉及的电子电路封装19中,追加了经由金属膜60覆盖复合成型构件40的上表面41的磁性膜70,在这一点上与第7实施方式所涉及的电子电路封装17不同。其它结构与第7实施方式所涉及的电子电路封装17相同,因此对相同要素标注相同符号并省略重复的说明。
本实施方式所涉及的电子电路封装19中,成为电磁屏蔽以及磁屏蔽的复合成型构件40的表面被构成电磁屏蔽的金属膜60以及构成磁屏蔽的磁性膜70覆盖,因此能够进一步提高电磁屏蔽以及磁屏蔽特性。
以上针对本发明的优选的实施方式进行了说明,但是本发明并不限定于以上所述的实施方式,可以在不脱离本发明宗旨的范围内进行各种各样的变更,那些变更显然包含于本发明的范围内。
实施例
准备中值粒径(D50)为10μm的第1填料F1和中值粒径(D50)为0.7μm的第2填料F2c。第1填料F1是由Fe为64重量%且Ni为36重量%的因瓦(invar)合金材料构成,将厚度为50nm的Ag镀层形成于其表面。第2填料F2由耐热性树脂构成,在其表面施以厚度为80nm的Ag镀层。
接下来,通过使联苯型环氧树脂、酚醛型固化剂以及催化剂(咪唑)溶解于丁基卡必醇从而调节粘结剂,并将上述的第1填料F1和第2填料F2c投入到粘结剂中,并在混炼装置中进行搅拌·混炼,从而获得复合密封材料。复合密封材料中的第1填料F1的配合比例为50体积%,第2填料F2c的配合比例为25体积%,粘结剂的配合比例为25体积%。
接下来,实际制作具有与图1所表示的电子电路封装11相同结构的实施例试样1~3。作为基板20,使用了平面尺寸为8mm×8mm且厚度为0.3mm的多层树脂基板。关于复合成型构件40,使用上述的复合密封材料,并在通过真空印刷法将复合成型构件40形成于基板20的上表面21之后,通过在100℃下加热4小时从而除去溶剂,进一步在180℃温度条件下进行了3小时的后固化。
在进行了后固化之后,通过研磨机(grinder)来磨削复合成型构件40的上表面41,从而调整厚度。在此,作为高度最高的电子部件的上部上的复合成型构件40的厚度(t),实施例试样1中为100μm,实施例2中为200μm,实施例3中为300μm。
另外,作为比较例,制作出替代上述复合密封材料而使用不具有磁性以及导电性的一般性的成型材料来进行成型,并通过溅射法将厚度为6μm的Cu膜形成于其表面的比较例试样。Cu膜连接于接地图案。
接下来,将各试样回流焊安装于屏蔽特性评价用基板,并通过用近旁磁场测定装置来测定噪音衰减量从而评价屏蔽特性。将结果示于图18中。
如图18所示,实施例试样1~3在20MHz~2.4GHz的频带区域被确认为噪音衰减量大于比较例试样。特别是在20MHz~50MHz的频带区域,实施例试样1~3基本上没有差别,并且被确认为相对于比较例试样能够获得相对较大的噪音衰减量。另外,在超过50MHz的频带区域,复合成型构件40的厚度越大越能够获得大的噪音衰减量,在实施例试样3中,在1GHz附近能够获得接近于测定界限的噪音衰减量。
Claims (20)
1.一种电子电路封装,其特征在于:
具备:
基板,其具有电源图案;
电子部件,被搭载于所述基板的表面;以及
复合成型构件,其以埋入所述电子部件的形式覆盖所述基板的所述表面,连接于所述电源图案并具有导电性,
所述复合成型构件包含树脂材料、和第1填料,所述第1填料配合于所述树脂材料,并在Fe中含有32~39重量%的以Ni作为主成分的金属材料。
2.如权利要求1所述的电子电路封装,其特征在于:
所述第1填料的表面被导电性高于所述第1填料的金属涂层包覆。
3.如权利要求1所述的电子电路封装,其特征在于:
所述复合成型构件进一步包含小于所述第1填料的第2填料。
4.如权利要求3所述的电子电路封装,其特征在于:
所述第2填料的表面被金属涂层包覆。
5.如权利要求3所述的电子电路封装,其特征在于:
所述第2填料由磁性材料构成。
6.如权利要求3所述的电子电路封装,其特征在于:
所述第2填料由导电性材料构成。
7.如权利要求3所述的电子电路封装,其特征在于:
所述第2填料由绝缘材料构成。
8.如权利要求3所述的电子电路封装,其特征在于:
所述第1填料以及第2填料在所述复合成型构件中的配合比例为50体积%以上且85体积%以下。
9.如权利要求3所述的电子电路封装,其特征在于:
相对于所述第1填料和所述第2填料的总量,所述第1填料的量为50体积%以上且99体积%以下。
10.如权利要求1所述的电子电路封装,其特征在于:
进一步具备将所述电子部件及其端子电极与所述复合成型构件互相绝缘的绝缘涂层。
11.如权利要求1所述的电子电路封装,其特征在于:
所述复合成型构件与露出于所述基板的所述表面的所述电源图案相接触。
12.如权利要求11所述的电子电路封装,其特征在于:
所述复合成型构件进一步与露出于所述基板的侧面的所述电源图案相接触。
13.如权利要求1所述的电子电路封装,其特征在于:
所述复合成型构件与露出于所述基板的侧面的所述电源图案相接触。
14.如权利要求13所述的电子电路封装,其特征在于:
所述基板的侧面包含侧面上部、和比所述侧面上部突出的侧面下部,
所述电源图案露出于所述基板的所述侧面上部,
所述复合成型构件不覆盖所述基板的所述侧面下部而覆盖所述基板的所述侧面上部。
15.如权利要求1所述的电子电路封装,其特征在于:
进一步具备覆盖所述复合成型构件并且导电性高于所述复合成型构件的金属膜。
16.如权利要求1所述的电子电路封装,其特征在于:
进一步具备覆盖所述复合成型构件并且导磁率高于所述复合成型构件的磁性膜。
17.如权利要求1所述的电子电路封装,其特征在于:
所述金属材料相对于所述第1填料整体进一步包含0.1~8重量%的Co。
18.如权利要求1所述的电子电路封装,其特征在于:
所述复合成型构件的热膨胀系数为15ppm/℃以下。
19.如权利要求1所述的电子电路封装,其特征在于:
在所述电子部件的上部的所述复合成型构件的厚度为50μm以上。
20.如权利要求19所述的电子电路封装,其特征在于:
在所述电子部件的上部的所述复合成型构件的厚度为100μm以上且300μm以下。
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