CN104009006A - 封装基板及其制法暨半导体封装件及其制法 - Google Patents

封装基板及其制法暨半导体封装件及其制法 Download PDF

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CN104009006A
CN104009006A CN201310069049.8A CN201310069049A CN104009006A CN 104009006 A CN104009006 A CN 104009006A CN 201310069049 A CN201310069049 A CN 201310069049A CN 104009006 A CN104009006 A CN 104009006A
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electric connection
packing colloid
connection pad
semiconductor package
making
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CN104009006B (zh
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林邦群
蔡岳颖
陈泳良
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装基板及其制法暨半导体封装件及其制法，该封装基板包括：具有相对的第一与第二表面的封装胶体、嵌埋于该封装胶体中的导电组件、以及形成于该封装胶体的第二表面上的保护层，该导电组件具有外露于该封装胶体的第一表面的第一电性连接垫及外露于该封装胶体的第二表面的第二电性连接垫，且该保护层位于该第二电性连接垫上。由于该保护层形成于该封装胶体与该第二电性连接垫上，所以能防止该封装胶体的第二表面因运送或外力冲击而刮伤。

Description

封装基板及其制法暨半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种提高良率的半导体封装件及其制法。
背景技术
随着半导体封装技术的演进，半导体封装件已开发出不同的封装型态，于现有技术中，该半导体封装件主要在一核心层上先形成多层线路结构以制成封装基板，再装置芯片于该封装基板上，且将芯片电性连接在该多层线路结构上，最后以封装胶体进行封装。但经由此方式形成的封装基板，因其核心层占有一定厚度，所以限制对封装件的厚度薄化。因而业界发展出一种无核心层的封装基板，其省略使用核心层，以降低封装件的高度，而此种封装件能缩减整体半导体封装件的体积，遂成为电子产品轻、薄、短、小的封装趋势。
图1A至图1D为绘示现有无核心层（coreless）的封装基板1’的制法的剖视示意图。
如图1A所示，提供一如金属板的载板10。
如图1B所示，形成多个第一电性连接垫121于该载板10上，再形成多个第二电性连接垫122于该些第一电性连接垫121上，使该第一电性连接垫121与该第二电性连接垫122构成导电组件12。
所述的第一电性连接垫121用于电性连接半导体组件，如芯片，而该第二电性连接垫122则作为植球垫，且于两个第一电性连接垫121之间可设计有线路（图略）通过。
如图1C所示，形成具有第一表面11a与第二表面11b的第一封装胶体11于该些导电组件12与载板10上，令该第一封装胶体11的第一表面11a结合该载板10，且经研磨该第一封装胶体11的第二表面11b的工艺后，该第二电性连接垫122将外露于该第一封装胶体11的第二表面11b。
如图1D所示，贯穿该载板10以形成开口100，使该载板10的剩余材质作为框体10’，且令该第一封装胶体11的第一表面11a与第一电性连接垫121外露于该开口100，以完成多个封装基板1’。
该框体10’设于该第一封装胶体11的第一表面11a上且位于该些第一电性连接垫121的外围，且于后续的封装工艺后，可沿该框体10’的位置进行切割，以移除该框体10’，如图1E所示。
图1E为应用前述制法所制作的封装基板而制成的现有加强型四方形平面无引脚（enhanced Quad Flat No leads,eQFN）半导体封装件1。
如图1E所示，进行封装工艺，通过粘着层150将一半导体组件15设于该第一封装胶体11的第一表面11a的置晶区D上，再以多条焊线16电性连接该半导体组件15与该置晶区D外围的第一电性连接垫121。
接着，形成第二封装胶体17于该第一封装胶体11的第一表面11a上，以包覆该半导体组件15与焊线16，且形成多个焊球18于该些第二电性连接垫122上，再进行切割（可沿框体的位置），以形成该半导体封装件1。
然而，现有半导体封装件1中，于设置该半导体组件15前，该第一封装胶体11的第二表面11b为外露，所以该第一封装胶体11容易因运送（handling）或外力冲击而造成其第二表面11b刮伤，或造成该第一封装胶体11碎裂（crack），致使产品报废。
此外，该第二电性连接垫122于封装工艺前为外露，所以需以有机保焊剂工艺（Organic Solderability Preservative,OSP）进行保护，以防止该第二电性连接垫122氧化，但却因此增加制作成本。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺点，本发明的主要目的在于提供一种封装基板及其制法暨半导体封装件及其制法，能防止该封装胶体的第二表面因运送或外力冲击而刮伤。
本发明的封装基板，包括：封装胶体，其具有相对的第一表面与第二表面；多个导电组件，其嵌埋于该封装胶体中，该导电组件具有外露于该封装胶体的第一表面的第一电性连接垫及外露于该封装胶体的第二表面的第二电性连接垫；以及保护层，其形成于该封装胶体的第二表面与该第二电性连接垫上。
本发明还提供一种封装基板的制法，其包括：提供一载板；形成多个导电组件于该载板上，且该导电组件具有设于该载板上的第一电性连接垫及电性连接该第一电性连接垫的第二电性连接垫；形成具有相对的第一表面与第二表面的封装胶体于该载板与该些导电组件上，且该封装胶体的第一表面结合该载板，而该第二电性连接垫外露于该封装胶体的第二表面；形成保护层于该封装胶体的第二表面与该第二电性连接垫上；以及移除该载板，以外露该封装胶体的第一表面与该第一电性连接垫。
前述的制法中，该载板的相对两侧具有金属层。
前述的封装基板及其制法中，形成该第一电性连接垫的材质为铜，且形成该第二电性连接垫的材质为铜。
前述的封装基板及其制法中，形成该保护层的材质为金属，如铜。
前述的封装基板及其制法中，移除该载板的部分材质，以外露该封装胶体的第一表面与该些第一电性连接垫，因而产生框体于该封装胶体的第一表面上且位于该第一电性连接垫的外围。
本发明另提供一种半导体封装件，其包括：第一封装胶体，其具有相对的第一表面与第二表面；多个导电组件，其嵌埋于该第一封装胶体中，该导电组件具有外露于该第一封装胶体的第一表面的第一电性连接垫及外露于该第一封装胶体的第二表面的第二电性连接垫，且该第二电性连接垫凹入于该第一封装胶体的第二表面；以及半导体组件，其设于该第一封装胶体的第一表面上，且该第一电性连接垫电性连接该半导体组件。
前述的半导体封装件中，还包括框体，其设于该第一封装胶体的第一表面上，且位于该半导体组件的外围。
本发明并提供一种半导体封装件的制法，其包括：提供一前述的封装基板；设置半导体组件于该第一封装胶体的第一表面上，且该第一电性连接垫电性连接该半导体组件；以及移除该保护层，以外露该第一封装胶体的第二表面与该第二电性连接垫。
前述的制法中，形成该保护层的材质为金属，如铜，且移除该保护层时，一并使该第二电性连接垫凹入于该第一封装胶体的第二表面。
前述的半导体封装件及其制法中，形成该第一电性连接垫的材质为铜，且形成该第二电性连接垫的材质为铜。
前述的半导体封装件及其制法中，该半导体组件通过多条焊线电性连接该些第一电性连接垫。
前述的半导体封装件及其制法中，还包括形成第二封装胶体于该第一封装胶体的第一表面上，以包覆该半导体组件。
依上述，该封装基板还包括框体，其设于该第一封装胶体的第一表面上，且位于该第一电性连接垫的外围，令该第二封装胶体形成于该框体中。于形成该第二封装胶体之后，再移除该框体。
前述的半导体封装件及其制法中，该第一封装胶体的第一表面上定义有置晶区，以供设置该半导体组件，且部分该导电组件位于该置晶区外围。
另外，前述的半导体封装件及其制法中，于移除该保护层后，还包括形成焊球于该第二电性连接垫上。
由上可知，本发明的封装基板及其制法暨半导体封装件及其制法，通过将保护层设于该第一封装胶体（即该封装基板的封装胶体）与该第二电性连接垫上，即可防止该第一封装胶体的表面刮伤，甚至避免该第一封装胶体碎裂。
此外，该第二电性连接垫于工艺中被该保护层遮盖，以防止该第二电性连接垫氧化，所以相比于现有技术，本发明的制法不需进行有机保焊剂工艺，因而可降低制作成本。
附图说明
图1A至图1D为现有封装基板的制法的剖视示意图；
图1E为现有半导体封装件的剖视示意图；
图2A至图2I为本发明封装基板的制法的剖视示意图；以及
图3A至图3D为本发明半导体封装件的制法的剖视示意图。
符号说明
1,3,3’           半导体封装件
1’,2             封装基板
10,30             载板
10’,20           框体
100,300           开口
11,21             第一封装胶体
11a,21a           第一表面
11b,21b           第二表面
12,22             导电组件
121,221,221’     第一电性连接垫
122,222,222’     第二电性连接垫
15,25             半导体组件
150,250           粘着层
16,26             焊线
17,27             第二封装胶体
18,28             焊球
23                保护层
24                表面处理层
30a               第一侧
30b               第二侧
301               第一金属层
302               第二金属层
31                第一阻层
310               第一开孔
32                第二阻层
320               第二开孔
D                 置晶区
S                 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2I为绘示本发明的封装基板2的制法的剖视示意图。
如图2A所示，先提供一载板30，该载板30具有相对的第一侧30a与第二侧30b，且该载板30的第一侧30a与第二侧30b上分别形成有一第一金属层301与一第二金属层302。于其它实施例中，该载板30可为如金属板的导电板材，因而可不具有该第一金属层301与一第二金属层302。
如图2B所示，形成一第一阻层31于该第二金属层302上，且该第一阻层31具有多个外露该第二金属层302的第一开孔310。
如图2C所示，通过该第二金属层302作为电镀种子层（seed layer）而电镀工艺，以形成第一电性连接垫221于该些第一开孔310中的第二金属层302上。于本实施例中，形成该第一电性连接垫221的材质为铜。于其它实施例中，可直接利用如金属板的导电载板30作为电镀导电层，以进行电镀工艺。
此外，也可利用该第一阻层31的第一开孔310的变化，同时制作连接该第一电性连接垫221的导电线路（图略），以使该导电线路与该第一电性连接垫221构成图案化线路层。
如图2D所示，形成一第二阻层32于该第一阻层31与该第一电性连接垫221上，且该第二阻层32具有多个第二开孔320，以外露该些第一电性连接垫221的部分表面。
如图2E所示，电镀形成多个第二电性连接垫222于该些第二开孔320中且电性连接该第一电性连接垫221，使该第一电性连接垫221与该第二电性连接垫222构成导电组件22。于本实施例中，形成该第二电性连接垫222的材质为铜。
此外，也可利用该第二阻层32的第二开孔320的变化，同时制作连接该第二电性连接垫222的导电线路（图略），以使该导电线路与该第二电性连接垫222构成图案化线路层。
如图2F所示，移除该第一阻层31与第二阻层32，以外露该第二金属层302与导电组件22。
如图2G所示，进行预成型（pre-mold）工艺，形成具有第一表面21a（即顶面）与第二表面21b（即底面）的第一封装胶体21于该些导电组件22与该载板30上，令该第一封装胶体21的第一表面21a结合该载板30的第二金属层302，且该第二电性连接垫222外露于该第一封装胶体21的第二表面21b。
接着，形成一保护层23于该第一封装胶体21的第二表面21b与该第二电性连接垫222上。于本实施例中，形成该保护层23的材质为铜。该保护层23可由溅镀或化镀(Electroless Plating)方式形成。
如图2H所示，蚀刻贯穿该载板30（含该第一金属层301与第二金属层302）以形成一开口300，令该第一封装胶体21的第一表面21a与该第一电性连接垫221外露于该开口300。
于本实施例中，该第一封装胶体21的第一表面21a上定义有一置晶区D，且部分的导电组件22设于该置晶区D外围，使该置晶区D内的第一电性连接垫221’作为置晶垫。
此外，因仅移除该载板30的部分材质，所以该载板30的剩余材质作为框体20，其设于该第一封装胶体21的第一表面21a上且位于该些第一电性连接垫221,221’的外围。
如图2I所示，形成一表面处理层24于该置晶区D外围的第一电性连接垫221上。
于本实施例中，形成该表面处理层24的材质为镍、钯、金所组群组的合金或多层金属的其中一者。
本发明的封装基板2的制法中，于该第一封装胶体21的第二表面21b上形成该保护层23，得以防止该第一封装胶体21的第二表面21b因运送（handling）或外力冲击而刮伤，进而能避免该第一封装胶体21碎裂，所以能降低产品的报废率。
此外，于该第二电性连接垫222上形成该保护层23，使该第二电性连接垫222于封装工艺前能通过该保护层23的遮盖，而得以防止该第二电性连接垫222氧化，所以本发明的制法不需进行有机保焊剂工艺，且通过简易的化镀工艺形成该保护层23，因而能有效降低制作成本。
图3A至图3D为绘示本发明的半导体封装件3,3’的制法的剖视示意图。
如图3A所示，接续图2I的工艺以进行封装工艺，通过粘着层250将至少一半导体组件25设于该第一封装胶体21的第一表面21a的置晶区D上（即作为置晶垫的第一电性连接垫221’上），再以多条焊线26电性连接该半导体组件25与该置晶区D外围的第一电性连接垫221。于其它实施例中，该半导体组件25也可利用覆晶（flip chip）方式设置于并电性连接于该第一电性连接垫221。
接着，形成第二封装胶体27于该第一封装胶体21的第一表面21a上，以包覆该半导体组件25与焊线26。于本实施例中，该第二封装胶体27填入该框体20中。
如图3B所示，移除该保护层23，以外露该第一封装胶体21的第二表面21b与该第二电性连接垫222。
于本实施例中，以蚀刻方式移除该保护层23，所以会一并移除该第二电性连接垫222的部分材质，令该第二电性连接垫222’凹入该第一封装胶体21的第二表面21b下。
如图3C所示，进行植球工艺，形成多个焊球28于该些第二电性连接垫222’上，以形成该半导体封装件3。于该置晶区D处的焊球28可作为散热用。
于另一实施例中，如图3D所示，可沿该框体20的位置进行切割（如图3C所示的切割路径S），以形成另一半导体封装件3’。
本发明的半导体封装件3,3’的制法中，该些第二电性连接垫222’于进行植球工艺时才移除该保护层23，所以该些第二电性连接垫222’不易氧化，因而能减少该焊球28发生掉落的情况，进而提升植球率。
此外，当进行植球工艺前才移除该保护层23，所以该保护层23于工艺中能长期保护该第一封装胶体21，因而有效防止该第一封装胶体21刮伤或碎裂。
本发明提供一种封装基板2，其包括：第一封装胶体21、嵌埋于该第一封装胶体21中的多个导电组件22、以及设于该第一封装胶体21上的一保护层23。
所述的第一封装胶体21具有相对的第一表面21a与第二表面21b。
所述的导电组件22具有外露于该第一封装胶体21的第一表面21a的第一电性连接垫221,221’及设于该第一电性连接垫221上的第二电性连接垫222，且该第二电性连接垫222外露于该第一封装胶体21的第二表面21b。
于本实施例中，形成该第一电性连接垫221,221’的材质为铜，且形成该第二电性连接垫222的材质为铜。
所述的保护层23设于该第一封装胶体21的第二表面21b与该第二电性连接垫222上。
于本实施例中，形成该保护层23的材质为铜。
于一实施例中，所述的封装基板2还包括一框体20，其设于该第一封装胶体21的第一表面21a上，且位于该些第一电性连接垫221,221’的外围。
本发明还提供一种半导体封装件3,3’，其包括：第一封装胶体21、嵌埋于该第一封装胶体21中的多个导电组件22、设于该第一封装胶体21上的半导体组件25、以及包覆该半导体组件25的第二封装胶体27。
所述的第一封装胶体21具有相对的第一表面21a与第二表面21b。
于本实施例中，该第一封装胶体21的第一表面21a上定义有置晶区D，以供设置该半导体组件25。
所述的导电组件22具有外露于该第一封装胶体21的第一表面21a的第一电性连接垫221,221’及设于该第一电性连接垫221上的第二电性连接垫222’，且该第二电性连接垫222’外露于该第一封装胶体21的第二表面21b。
于本实施例中，形成该第一电性连接垫221,221’的材质为铜，且形成该第二电性连接垫222’的材质为铜。此外，部分的导电组件22设于该置晶区D外围，使该置晶区D内的第一电性连接垫221’作为置晶垫。又，该第二电性连接垫222’上可形成焊球28。
所述的半导体组件25设于该第一封装胶体21的第一表面21a上，并通过多条焊线26电性连接该置晶区D外围的第一电性连接垫221。
所述的第二封装胶体27形成于该第一封装胶体21的第一表面21a与该些第一电性连接垫221（或表面处理层24）上，以包覆该半导体组件25与焊线26。
于一实施例中，所述的半导体封装件3还包括一框体20，其设于该第一封装胶体21的第一表面21a上，且位于该半导体组件25（或该第二封装胶体27）的外围。
综上所述，本发明的封装基板及其制法暨半导体封装件及其制法，主要通过当进行封装工艺前，先以保护层遮盖该第一封装胶体，以防止该第一封装胶体刮伤或碎裂。
此外，当进行植球工艺前，先以化镀方式形成保护层于该第二电性连接垫上，以防止该第二电性连接垫氧化，所以本发明的制法不需进行有机保焊剂工艺，因而可降低制作成本。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如后述权利要求书所列。

Claims (33)

1.一种封装基板，其包括：
封装胶体，其具有相对的第一表面与第二表面；
多个导电组件，其嵌埋于该封装胶体中，各该导电组件具有外露于该封装胶体的第一表面的第一电性连接垫及外露于该封装胶体的第二表面的第二电性连接垫；以及
保护层，其形成于该封装胶体的第二表面与该第二电性连接垫上。
2.根据权利要求1所述的封装基板，其特征在于，形成该第一电性连接垫的材质为铜。
3.根据权利要求1所述的封装基板，其特征在于，形成该第二电性连接垫的材质为铜。
4.根据权利要求1所述的封装基板，其特征在于，形成该保护层的材质为金属。
5.根据权利要求4所述的封装基板，其特征在于，形成该保护层的材质为铜。
6.根据权利要求1所述的封装基板，其特征在于，该封装基板还包括框体，其设于该封装胶体的第一表面上，且位于该第一电性连接垫的外围。
7.一种半导体封装件，其包括：
第一封装胶体，其具有相对的第一表面与第二表面；
多个导电组件，其嵌埋于该第一封装胶体中，各该导电组件具有外露于该第一封装胶体的第一表面的第一电性连接垫及外露于该第一封装胶体的第二表面的第二电性连接垫，且各该第二电性连接垫凹入于该第一封装胶体的第二表面；以及
半导体组件，其设于该第一封装胶体的第一表面上，并电性连接至该第一电性连接垫。
8.根据权利要求7所述的半导体封装件，其特征在于，该第一封装胶体的第一表面上定义有置晶区，以供设置该半导体组件，且部分该导电组件位于该置晶区外围。
9.根据权利要求7所述的半导体封装件，其特征在于，形成该第一电性连接垫的材质为铜。
10.根据权利要求7所述的半导体封装件，其特征在于，形成该第二电性连接垫的材质为铜。
11.根据权利要求7所述的半导体封装件，其特征在于，该第二电性连接垫上设有焊球。
12.根据权利要求7所述的半导体封装件，其特征在于，该半导体组件通过多条焊线电性连接该些第一电性连接垫。
13.根据权利要求7所述的半导体封装件，其特征在于，该半导体封装件还包括第二封装胶体，其形成于该第一封装胶体的第一表面上，以包覆该半导体组件。
14.根据权利要求7所述的半导体封装件，其特征在于，该半导体封装件还包括框体，其设于该第一封装胶体的第一表面上，且位于该半导体组件的外围。
15.一种封装基板的制法，其包括：
提供一载板；
形成多个导电组件于该载板上，且各该导电组件具有设于该载板上的第一电性连接垫及电性连接该第一电性连接垫的第二电性连接垫；
形成具有相对的第一表面与第二表面的封装胶体于该载板与该些导电组件上，使该封装胶体的第一表面结合至该载板，且使该第二电性连接垫外露于该封装胶体的第二表面；
形成保护层于该封装胶体的第二表面与该第二电性连接垫上；以及
移除该载板，以外露该封装胶体的第一表面与该第一电性连接垫。
16.根据权利要求15所述的封装基板的制法，其特征在于，该载板的相对两侧具有金属层。
17.根据权利要求15所述的封装基板的制法，其特征在于，形成该第一电性连接垫的材质为铜。
18.根据权利要求15所述的封装基板的制法，其特征在于，形成该第二电性连接垫的材质为铜。
19.根据权利要求15所述的封装基板的制法，其特征在于，形成该保护层的材质为金属。
20.根据权利要求19所述的封装基板的制法，其特征在于，形成该保护层的材质为铜。
21.根据权利要求15所述的封装基板的制法，其特征在于，该封装胶体的第一表面与该些第一电性连接垫的外露，是藉移除部分该载板为之。
22.一种半导体封装件的制法，其包括：
提供一封装基板，其包含：
封装胶体，其具有相对的第一表面与第二表面；
多个导电组件，其嵌埋于该封装胶体中，各该导电组件具有外露于该封装胶体的第一表面的第一电性连接垫及外露于该封装胶体的第二表面的第二电性连接垫；及
保护层，其形成于该封装胶体的第二表面与该第二电性连接垫上；
设置半导体组件于该第一封装胶体的第一表面上，并电性连接至该第一电性连接垫；以及
移除该保护层，以外露该第一封装胶体的第二表面与该第二电性连接垫。
23.根据权利要求22所述的半导体封装件的制法，其特征在于，形成该第一电性连接垫的材质为铜。
24.根据权利要求22所述的半导体封装件的制法，其特征在于，形成该第二电性连接垫的材质为铜。
25.根据权利要求22所述的半导体封装件的制法，其特征在于，形成该保护层的材质为金属。
26.根据权利要求25所述的半导体封装件的制法，其特征在于，形成该保护层的材质为铜。
27.根据权利要求22所述的半导体封装件的制法，其特征在于，该第一封装胶体的第一表面上定义有置晶区，以供设置该半导体组件，而令部分导电组件位于该置晶区外围。
28.根据权利要求22所述的半导体封装件的制法，其特征在于，该半导体组件通过多条焊线电性连接该些第一电性连接垫。
29.根据权利要求22所述的半导体封装件的制法，其特征在于，该制法还包括形成第二封装胶体于该第一封装胶体的第一表面上，以包覆该半导体组件。
30.根据权利要求29所述的半导体封装件的制法，其特征在于，该封装基板还包括框体，其设于该第一封装胶体的第一表面上，且位于该第一电性连接垫的外围，以令该第二封装胶体形成于该框体中。
31.根据权利要求30所述的半导体封装件的制法，其特征在于，于形成该第二封装胶体后，还包括移除该框体。
32.根据权利要求22所述的半导体封装件的制法，其特征在于，于移除该保护层时，还包括使该第二电性连接垫凹入于该第一封装胶体的第二表面。
33.根据权利要求22或32所述的半导体封装件的制法，其特征在于，于移除该保护层后，还包括形成焊球于该第二电性连接垫上。
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