CN105470230A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

Info

Publication number
CN105470230A
CN105470230A CN201510516437.5A CN201510516437A CN105470230A CN 105470230 A CN105470230 A CN 105470230A CN 201510516437 A CN201510516437 A CN 201510516437A CN 105470230 A CN105470230 A CN 105470230A
Authority
CN
China
Prior art keywords
layer
dielectric
making
conductive layer
bearing part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510516437.5A
Other languages
English (en)
Inventor
白裕呈
邱士超
林俊贤
范植文
陈嘉成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105470230A publication Critical patent/CN105470230A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种封装结构及其制法，该制法包括：提供一具有相对的两表面的承载件，且于该承载件的两表面上分别形成一介电体，各该介电体中嵌埋有线路层与形成于该线路层上的导电层，之后移除该承载件，藉由在该承载件的相对两表面上分别制作线路层、导电层与介电体，以提高产能。

Description

封装结构及其制法
技术领域
本发明有关一种封装结构，尤指一种供半导体封装的线路封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，许多高阶电子产品都逐渐朝往轻、薄、短、小等高集积度方向发展，且随着封装技术的演进，晶片的封装技术也越来越多样化，半导体封装件的尺寸或体积亦随之不断缩小，藉以使该半导体封装件达到轻薄短小的目的。
图1A至图1C为现有封装结构1的制法的剖视图。
如图1A所示，于一承载件上形成一介电体11，且该介电体11中嵌埋有线路层12与形成于该线路层12上的导电层13。接着，移除部分该承载件，使保留的承载件作为支撑架10。之后，于该介电体11上设置电子元件14，且该电子元件14藉由多个如焊锡材料或铜柱的导电元件140电性连接该线路层12。
如图1B所示，将上述结构设于模具90中。
如图1C所示，于模具90的填充空间900中灌注封装胶体15，再移除该模具90与支撑架10。
惟，现有封装结构1的制法中，该承载件需作为支撑架10，故仅能于该承载件的其中一侧形成封装结构1，导致产能(unitsperhour，简称UPH)较低。
此外，由于该支撑架10抵靠模具90，使该模具90与该介电体11之间产生间隙，导致模压后的封装胶体15的最小厚度等于该支撑架10的高度h，故该封装胶体15的厚度h’需大于或等于支撑架10的高度h(亦即原本承载件的厚度)，而无法形成较薄的封装胶体15，导致该现有封装结构1无法满足薄化电子产品的需求。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种封装结构及其制法，以提高产能。
本发明的封装结构，包括：承载件，其具有相对的两表面；以及二介电体，其分别形成于该承载件的两表面上，且各该介电体中嵌埋有第一线路层与形成于该第一线路层上的第一导电层。
本发明还提供一种封装结构的制法，包括：提供一具有相对的两表面的承载件；于该承载件的两表面上分别形成一介电体，且各该介电体中嵌埋有第一线路层与形成于该第一线路层上的第一导电层；以及移除该承载件。
前述的制法中，还包括设置电子元件于该介电体上，且该电子元件电性连接至该第一线路层，且形成封装胶体于该介电体上，使该封装胶体包覆该电子元件；或者，形成底胶于该介电体与该电子元件之间，使该底胶固定该电子元件。
前述的封装结构及其制法中，该承载件的两表面为金属表面。
前述的封装结构及其制法中，先于该承载件的两表面上形成该第一线路层，使该第一线路层结合于该承载件上，再形成该第一导电层于该第一线路层的部分表面上，之后形成该介电体于该承载件的两表面上。或者，先于该承载件的两表面上藉由第一感光型介电层形成该第一线路层，再藉由第二感光型介电层形成该第一导电层于该第一线路层的部分表面上，并令该第一与第二感光型介电层作为该介电体。
前述的封装结构及其制法中，该第一导电层外露于该介电体。例如，先形成该介电体于该承载件的两表面上，且该第一导电层未外露于该介电体的表面，再移除该介电体的部分表面，使该第一导电层外露于该介电体的表面。
前述的封装结构及其制法中，形成该介电体的材质为模压树脂、预浸材或感光型介电层。
前述的封装结构及其制法中，还包括形成第二线路层于该介电体上，且该第二线路层电性连接该第一导电层。
依上述，还包括形成绝缘保护层于该介电体与第二线路层上。
依上述，还包括形成第二导电层于该第二线路层上，再形成介电层于该介电体上，且该介电层包覆该第二线路层与第二导电层。进一步地，还包括形成第三线路层于该介电层上，且该第三线路层电性连接该第二导电层。更进一步地，还包括形成绝缘保护层于该介电层与第三线路层上。
由上可知，本发明的封装结构及其制法中，主要藉由该承载件的相对两表面上分别制作线路层、导电层与介电材，故相较于现有技术的单面制作，本发明可将产量增加一倍，因而有效提高产能。
再者，藉由移除该承载件，以避免形成现有支撑架，故于形成该封装胶体时，模具的填充空间能依需求调整降低，以利于缩小结构高度，因而能满足薄化电子产品的需求。
又，本发明的制法先形成线路层及导电层，再形成介电部，之后外露该导电层，以电性连接后续形成的线路，故此种方式无需于该介电部上使用激光钻孔来制作该导电层，因而能降低制作成本
附图说明
图1A至图1C为现有封装结构的制法的剖面示意图；
图2A至图2E为本发明的封装结构的制法的第一实施例的剖面示意图；其中，图2B’及图2B”为图2B的不同实施例，图2E’为图2E的另一实施例；
图3A至图3D为本发明的封装结构的制法的第二实施例的剖面示意图；以及
图4A至图4E为本发明的封装结构的制法的第三实施例的剖面示意图。
符号说明
1,2,2’,3,4封装结构
10支撑架
11,21,21’,21”介电体
12线路层
13导电层
14,24电子元件
140,240,27导电元件
15,25封装胶体
20承载件
20a,20b表面
200板体
201金属层
22第一线路层
220第一感光型介电层
23第一导电层
230第二感光型介电层
26底胶
31绝缘保护层
32第二线路层
41介电层
42第三线路层
43第二导电层
90模具
900填充空间
h高度
h’厚度。
具体实施方式
以下藉由特定的具体实例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。本发明也可藉由其他不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域的技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2E为显示本发明的封装结构2的制法的第一实施例的剖视图。
如图2A所示，提供一具有相对的两表面20a,20b的承载件20。
于本实施例中，该承载件20的两表面20a,20b为金属表面。具体地，该承载件20具有如金属板、半导体晶圆或玻璃板的板体200与设于该板体200两侧的金属层201，该金属层201为铜箔，且于该板体200与该金属层201之间也可依需求设有如离形膜、粘着材或绝缘材等的结合层(图略)，以利于后续分离作业。
如图2B所示，于该承载件20的两表面20a,20b上分别形成有一介电体21，且各该介电体21中嵌埋有一第一线路层22与形成于该第一线路层22的部分表面上的一第一导电层23。
于本实施例中，形成该介电体21的材质如模压树脂(moldingcompound)、预浸材(prepreg)或感光型介电层，但不限于此，且该介电体21、第一线路层22与第一导电层23的制作顺序并无特殊限制。
例如，可先于该承载件20的两表面20a,20b上藉由第一光阻形成一第一线路层22，再藉由第二光阻形成一第一导电层23于该第一线路层22的部分表面上，之后移除该第一光阻与第二光阻，再以模封(molding)或压合(laminate)方式形成该介电体21于该承载件20的两表面20a,20b上。
或者，可先于该承载件20的两表面20a,20b上藉由第一感光型介电层220形成一第一线路层22，再藉由第二感光型介电层230形成一第一导电层23于该第一线路层22的部分表面上，令该第一与第二感光型介电层220,230作为该介电体21’，如图2B’所示。
又，该第一导电层23外露于该介电体21的表面。例如，以模封或压合方式形成该介电体21”于该承载件20的两表面20a,20b上，如图2B”所示，该第一导电层23未外露于该介电体21”的表面，再以研磨(grinding)方式移除该介电体21”的部分上表面，使该第一导电层23外露于该介电体21的表面；或者，直接形成如图2B所示的介电体21的实施例。
另外，该第一线路层22结合于该承载件20的两表面20a,20b上。
如图2C所示，以分离方式，移除该承载件20的板体200。
如图2D所示，蚀刻移除该介电体21上的金属层201，使该第一线路层22的表面低于该介电体21。
于本实施例中，蚀刻该金属层201的同时，还蚀刻该第一导电层23的表面，使该第一导电层23的表面低于该介电体21。
如图2E所示，设置至少一电子元件24于该介电体21上，且该电子元件24电性连接至该第一线路层22。
于本实施例中，形成封装胶体25于该介电体21上，使该封装胶体25包覆该电子元件24。
此外，该电子元件24为主动元件、被动元件或其组合者，且该主动元件为例如半导体晶片，而该被动元件为例如电阻、电容及电感。
又，该电子元件24藉由多个如焊锡材料或铜柱的导电元件240电性连接至该第一线路层22，且该封装胶体25包覆该些导电元件240。于其它方式中，该电子元件24也可依需求藉由打线方式(wirebonding)电性连接该第一线路层22。
另外，该第一导电层23上形成有多个如焊锡材料的导电元件27。
于另一实施例中，如图2E’所示，也可先形成底胶26于该介电体21与该电子元件24之间，使该底胶26包覆该些导电元件240并固定该电子元件24，再形成封装胶体25于该介电体21上，使该封装胶体25包覆该电子元件24与该底胶26。
本发明的制法于该承载件20的上下表面20a,20b分别制作第一线路层22、第一导电层23与介电体21,21’，故相较于现有技术的单面制作，本发明的制法可将产量增加一倍，因而有效提高产能。
此外，由于移除该承载件20，因而不会形成现有支撑架，故于形成该封装胶体25时，模具的填充空间能依需求调整降低，以利于缩小本发明的封装结构2’的高度，因此，本发明的封装结构2’能满足薄化电子产品的需求。
又，本发明的制法先形成第一线路层22及第一导电层23，再形成该介电体21，之后外露该第一导电层23，以电性连接后续形成的线路，故此种方式无需于该介电体21上使用激光钻孔以制作该第一导电层23，因而能降低制作成本。
请参阅图3A至图3D为显示本发明的封装结构3的制法的第二实施例的剖视图。
如图3A所示，提供一如图2B的结构。
于本实施例中，有关图3A的结构的制作方式可参考上述图2A至图2B的制程的说明。
如图3B所示，藉由图案化制程，形成一第二线路层32于该介电体21上，且该第二线路层32电性连接该第一导电层23。
如图3C所示，形成一绝缘保护层31于该介电体21与第二线路层32上。
于本实施例中，该第二线路层32外露于该绝缘保护层31的表面。例如，先以压合方式形成该绝缘保护层31于该介电体21上，该第二线路层32未外露于该绝缘保护层31的表面，再以研磨方式移除该绝缘保护层31的部分上表面，使该第二线路层32的表面齐平该绝缘保护层31的表面，而令该第二线路层32外露于该绝缘保护层31的表面。
如图3D所示，先以分离方式移除该承载件20的板体200，再蚀刻移除该介电体21上的金属层201，使该第一线路层22的表面低于该介电体21。
于本实施例中，蚀刻该金属层201的同时，还蚀刻该第二线路层32的表面，使该第二线路层32的表面低于该绝缘保护层31。
本发明的制法为先形成第一线路层22及第一导电层23，再形成该介电体21，之后外露该第一导电层23，以电性连接该第二线路层32，故此种方式无需于该介电体21上使用激光钻孔以制作该第一导电层23，因而能降低制作成本。
请参阅图4A至图4E为显示本发明的封装结构4的制法的第二实施例的剖视图。
如图4A所示，其为接续图2B的制程，形成一第二线路层32于该介电体21上，且该第二线路层32电性连接该第一导电层23，再形成一第二导电层43于该第二线路层32的部分表面上。
于本实施例中，可先于该介电体21上藉由第一光阻形成一第二线路层32，再藉由第二光阻形成一第二导电层43于该第二线路层32的部分表面上，之后移除该第一光阻与第二光阻。
如图4B所示，形成一介电层41于该介电体21上，且该介电层41包覆该第二线路层32与第二导电层43。
于本实施例中，形成该介电层41的材质如模压树脂、预浸材或感光型介电层，但不限于此，且该介电层41的材质与该介电体21的材质可相同或不同。
此外，可以模封或压合方式形成该介电层41于该介电体21上。或者，以如图2B’所示的方式制作该介电层41。
又，该第二导电层43外露于该介电层41的表面。例如，以如图2B”所示的方式形成该介电层41；或者，直接形成如图4B所示的介电层41的实施例。
另外，该介电层41、第二线路层32与第二导电层43的制作顺序并无特殊限制。
如图4C所示，藉由图案化制程，形成一第三线路层42于该介电层41上，且该第三线路层42电性连接该第二导电层43。
如图4D所示，形成一绝缘保护层31于该介电层41与第三线路层42上。
于本实施例中，该第三线路层42外露于该绝缘保护层31的表面。例如，先以压合方式形成该绝缘保护层31于该介电层41上，该第三线路层42未外露于该绝缘保护层31的表面，再以研磨方式移除该绝缘保护层31的部分上表面，使该第三线路层42的表面齐平该绝缘保护层31的表面，而令该第三线路层42外露于该绝缘保护层31的表面。
如图4E所示，先以分离方式移除该承载件20的板体200，再蚀刻移除该介电体21上的金属层201，使该第一线路层22的表面低于该介电体21。
于本实施例中，蚀刻该金属层201的同时，还蚀刻该第三线路层42的表面，使该第三线路层42的表面低于该绝缘保护层31。
本发明的制法为先形成第二线路层32及第二导电层43，再形成该介电层41，之后外露该第二导电层43，以电性连接该第三线路层42，故此种方式无需于该介电层41上使用激光钻孔以制作该第二导电层43，因而能降低制作成本。
本发明提供一种封装结构2,3,4，包括：一具有相对两表面20a,20b的承载件20、以及分别形成于该承载件20的两表面20a,20b上的二介电体21,21’。
所述的介电体21,21’中嵌埋有一第一线路层22与形成于该第一线路层22上的一第一导电层23。
于一实施例中，该承载件20的两表面20a,20b为金属表面。
于一实施例中，该第一线路层22结合于该承载件20上。
于一实施例中，该第一导电层23外露于该介电体21。
于一实施例中，形成该介电体21,21’的材质为模压树脂、预浸材或感光型介电层。
于一实施例中，所述的封装结构3,4还包括形成于该介电体21上的第二线路层32，且该第二线路层32电性连接该第一导电层23。
依上述，该封装结构3又包括形成于该介电体21与第二线路层32上的一绝缘保护层31。
或者，该封装结构4又包括形成于该第二线路层32上的一第二导电层43、及形成于该介电体21上的一介电层41，且该介电层41包覆该第二线路层32与第二导电层43。该封装结构4另包括形成于该介电层41上的一第三线路层42、及形成于该介电层41与第三线路层42上的一绝缘保护层31，且该第三线路层42电性连接该第二导电层43。
综上所述，本发明封装结构及其制法，藉由该承载件的上、下表面分别制作线路层、导电层与介电材，故相较于现有技术的单面制作，本发明的制法可将产量增加一倍，因而有效提高产能。
此外，由于移除该承载件，因而不会形成现有支撑架，故于形成该封装胶体时，模具的填充空间能依需求调整降低，以利于缩小本发明的封装结构的高度，因此，本发明的封装结构能满足薄化电子产品的需求。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域的技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (25)

1.一种封装结构，其特征为，该封装结构包括：
承载件，其具有相对的两表面；以及
二介电体，其分别形成于该承载件的两表面上，且各该介电体中嵌埋有第一线路层与形成于该第一线路层上的第一导电层。
2.如权利要求1所述的封装结构，其特征为，该承载件的两表面为金属表面。
3.如权利要求1所述的封装结构，其特征为，该第一线路层结合于该承载件上。
4.如权利要求1所述的封装结构，其特征为，该第一导电层外露于该介电体。
5.如权利要求1所述的封装结构，其特征为，形成该介电体的材质为模压树脂、预浸材或感光型介电层。
6.如权利要求1所述的封装结构，其特征为，该封装结构还包括形成于该介电体上的第二线路层，且该第二线路层电性连接该第一导电层。
7.如权利要求6所述的封装结构，其特征为，该封装结构还包括形成于该介电体与第二线路层上的绝缘保护层。
8.如权利要求6所述的封装结构，其特征为，该封装结构还包括形成于该第二线路层上的第二导电层、及形成于该介电体上的介电层，且该介电层包覆该第二线路层与第二导电层。
9.如权利要求8所述的封装结构，其特征为，该封装结构还包括形成于该介电层上的第三线路层，且该第三线路层电性连接该第二导电层。
10.如权利要求9所述的封装结构，其特征为，该封装结构还包括形成于该介电层与第三线路层上的绝缘保护层。
11.一种封装结构的制法，其特征为，该制法包括：
提供一具有相对的两表面的承载件；
于该承载件的两表面上分别形成一介电体，且各该介电体中嵌埋有第一线路层与形成于该第一线路层上的第一导电层；以及
移除该承载件。
12.如权利要求11所述的封装结构的制法，其特征为，该承载件的两表面为金属表面。
13.如权利要求11所述的封装结构的制法，其特征为，先于该承载件的两表面上形成该第一线路层，再形成该导电层于该第一线路层的部分表面上，之后形成该介电体于该承载件的两表面上。
14.如权利要求11所述的封装结构的制法，其特征为，先于该承载件的两表面上藉由第一感光型介电层形成该第一线路层，再藉由第二感光型介电层形成该第一导电层于该第一线路层的部分表面上，并令该第一与第二感光型介电层作为该介电体。
15.如权利要求11所述的封装结构的制法，其特征为，该第一导电层外露于该介电体。
16.如权利要求15所述的封装结构的制法，其特征为，先形成该介电体于该承载件的两表面上，且该第一导电层未外露于该介电体的表面，再移除该介电体的部分表面，使该第一导电层外露于该介电体的表面。
17.如权利要求11所述的封装结构的制法，其特征为，形成该介电体的材质为模压树脂、预浸材或感光型介电层。
18.如权利要求11所述的封装结构的制法，其特征为，该制法还包括设置电子元件于该介电体上，且该电子元件电性连接至该第一线路层。
19.如权利要求18所述的封装结构的制法，其特征为，该制法还包括形成封装胶体于该介电体上，使该封装胶体包覆该电子元件。
20.如权利要求18所述的封装结构的制法，其特征为，该制法还包括形成底胶于该介电体与该电子元件之间，使该底胶固定该电子元件。
21.如权利要求11所述的封装结构的制法，其特征为，该制法还包括形成第二线路层于该介电体上，且该第二线路层电性连接该第一导电层。
22.如权利要求21所述的封装结构的制法，其特征为，该制法还包括形成绝缘保护层于该介电体与第二线路层上。
23.如权利要求21所述的封装结构的制法，其特征为，该制法还包括形成第二导电层于该第二线路层上，再形成介电层于该介电体上，且该介电层包覆该第二线路层与第二导电层。
24.如权利要求23所述的封装结构的制法，其特征为，该制法还包括形成第三线路层于该介电层上，且该第三线路层电性连接该第二导电层。
25.如权利要求24所述的封装结构的制法，其特征为，该制法还包括形成绝缘保护层于该介电层与第三线路层上。
CN201510516437.5A 2014-09-26 2015-08-21 封装结构及其制法 Pending CN105470230A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW103133456 2014-09-26
TW103133456 2014-09-26
TW104124217 2015-07-27
TW104124217A TWI570816B (zh) 2014-09-26 2015-07-27 封裝結構及其製法

Publications (1)

Publication Number Publication Date
CN105470230A true CN105470230A (zh) 2016-04-06

Family

ID=55585267

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510516437.5A Pending CN105470230A (zh) 2014-09-26 2015-08-21 封装结构及其制法

Country Status (3)

Country Link
US (1) US20160093546A1 (zh)
CN (1) CN105470230A (zh)
TW (1) TWI570816B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275967B2 (en) * 2014-01-06 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
TWI559829B (zh) 2014-10-22 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
CN105931997B (zh) * 2015-02-27 2019-02-05 胡迪群 暂时性复合式载板
KR101706470B1 (ko) * 2015-09-08 2017-02-14 앰코 테크놀로지 코리아 주식회사 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법
US11749616B2 (en) * 2017-10-05 2023-09-05 Texas Instruments Incorporated Industrial chip scale package for microelectronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1980541A (zh) * 2005-12-07 2007-06-13 新光电气工业株式会社 制造布线基板的方法和制造电子元件安装结构的方法
CN102903680A (zh) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 半导体封装件及其制法
US20130083503A1 (en) * 2011-09-30 2013-04-04 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
US20130256012A1 (en) * 2009-06-03 2013-10-03 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing the same
CN104009006A (zh) * 2013-02-27 2014-08-27 矽品精密工业股份有限公司 封装基板及其制法暨半导体封装件及其制法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100956688B1 (ko) * 2008-05-13 2010-05-10 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US8686300B2 (en) * 2008-12-24 2014-04-01 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
LT2394351T (lt) * 2009-02-05 2021-01-11 Evr Motors Ltd. Elektrinė mašina
TWI388019B (zh) * 2009-09-02 2013-03-01 Unimicron Technology Corp 封裝結構之製法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1980541A (zh) * 2005-12-07 2007-06-13 新光电气工业株式会社 制造布线基板的方法和制造电子元件安装结构的方法
US20130256012A1 (en) * 2009-06-03 2013-10-03 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing the same
CN102903680A (zh) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 半导体封装件及其制法
US20130083503A1 (en) * 2011-09-30 2013-04-04 Unimicron Technology Corporation Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure
CN104009006A (zh) * 2013-02-27 2014-08-27 矽品精密工业股份有限公司 封装基板及其制法暨半导体封装件及其制法

Also Published As

Publication number Publication date
TWI570816B (zh) 2017-02-11
TW201624577A (zh) 2016-07-01
US20160093546A1 (en) 2016-03-31

Similar Documents

Publication Publication Date Title
CN105470230A (zh) 封装结构及其制法
CN104025288A (zh) 半导体封装及其制造方法
TWI628761B (zh) 一種封裝結構及其製造方法
CN103177977A (zh) 通过选择性处理暴露封装件中的连接件
CN103021982A (zh) 集成电路及制造方法
CN103400830B (zh) 多层芯片堆叠结构及其实现方法
CN105304584A (zh) 中介基板及其制造方法
CN105489565A (zh) 嵌埋元件的封装结构及其制法
US9293398B2 (en) Land structure for semiconductor package and method therefor
CN105514053B (zh) 半导体封装件及其制法
CN105633052B (zh) 封装结构及其制法
CN104124212A (zh) 半导体封装件及其制法
US9474162B2 (en) Circuit substrate and method of manufacturing same
CN105575915A (zh) 封装结构及其制法
CN105762132A (zh) 单层线路式封装基板及制法、单层线路式封装结构及制法
CN105489580A (zh) 半导体衬底及半导体封装结构
CN104576406A (zh) 一种封装基板的制作方法及所对应的封装基板
CN105428326A (zh) 封装结构及其制法
CN106298728A (zh) 封装结构及其制法
US20150366085A1 (en) Package structure and fabrication method thereof
CN108074894B (zh) 半导体器件封装
CN106169427B (zh) 基于薄膜的扇出及多晶粒封装平台
CN115458511A (zh) 一种滤波器电路封装结构及其制作方法
TWI566330B (zh) 電子封裝結構之製法
CN107920413B (zh) 多层电路板及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160406