TWI570816B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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TWI570816B
TWI570816B TW104124217A TW104124217A TWI570816B TW I570816 B TWI570816 B TW I570816B TW 104124217 A TW104124217 A TW 104124217A TW 104124217 A TW104124217 A TW 104124217A TW I570816 B TWI570816 B TW I570816B
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layer
dielectric
carrier
dielectric body
package structure
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TW104124217A
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TW201624577A (zh
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白裕呈
邱士超
林俊賢
范植文
陳嘉成
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矽品精密工業股份有限公司
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Priority to TW104124217A priority Critical patent/TWI570816B/zh
Priority to CN201510516437.5A priority patent/CN105470230A/zh
Priority to US14/833,102 priority patent/US20160093546A1/en
Publication of TW201624577A publication Critical patent/TW201624577A/zh
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Publication of TWI570816B publication Critical patent/TWI570816B/zh

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種供半導體封裝之線路封裝結構及其製法。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。
第1A至1C圖係為習知封裝結構1之製法的剖視圖。
如第1A圖所示，於一承載件上形成一介電體11，且該介電體11中係嵌埋有線路層12與形成於該線路層12上之導電層13。接著，移除部分該承載件，使保留之承載件作為支撐架10。之後，於該介電體11上設置電子元件14，且該電子元件14藉由複數如銲錫材料或銅柱之導電元件140電性連接該線路層12。
如第1B圖所示，將上述結構設於模具90中。
如第1C圖所示，於模具90之填充空間900中灌注封 裝膠體15，再移除該模具90與支撐架10。
惟，習知封裝結構1之製法中，該承載件需作為支撐架10，故僅能於該承載件之其中一側形成封裝結構1，導致產能(units per hour，簡稱UPH)較低。
再者，由於該支撐架10抵靠模具90，使該模具90與該介電體11之間產生間隙，導致模壓後之封裝膠體15之最小厚度等於該支撐架10的高度h，故該封裝膠體15的厚度h’需大於或等於支撐架10的高度h(亦即原本承載件的厚度)，而無法形成較薄之封裝膠體15，導致該習知封裝結構1無法滿足薄化電子產品之需求。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種封裝結構，係包括：承載件，係具有相對之兩表面；以及二介電體，係分別形成於該承載件之兩表面上，且各該介電體中係嵌埋有第一線路層與形成於該第一線路層上之第一導電層。
本發明復提供一種封裝結構之製法，係包括：提供一具有相對之兩表面之承載件；於該承載件之兩表面上分別形成一介電體，且各該介電體中係嵌埋有第一線路層與形成於該第一線路層上之第一導電層；以及移除該承載件。
前述之製法中，復包括設置電子元件於該介電體上，且該電子元件係電性連接至該第一線路層，且形成封裝膠 體於該介電體上，使該封裝膠體包覆該電子元件；或者，形成底膠於該介電體與該電子元件之間，使該底膠固定該電子元件。
前述之封裝結構及其製法中，該承載件之兩表面係為金屬表面。
前述之封裝結構及其製法中，係先於該承載件之兩表面上形成該第一線路層，使該第一線路層結合於該承載件上，再形成該第一導電層於該第一線路層之部分表面上，之後形成該介電體於該承載件之兩表面上。或者，先於該承載件之兩表面上藉由第一感光型介電層形成該第一線路層，再藉由第二感光型介電層形成該第一導電層於該第一線路層之部分表面上，並令該第一與第二感光型介電層作為該介電體。
前述之封裝結構及其製法中，該第一導電層係外露於該介電體。例如，先形成該介電體於該承載件之兩表面上，且該第一導電層未外露於該介電體之表面，再移除該介電體之部分表面，使該第一導電層外露於該介電體之表面。
前述之封裝結構及其製法中，形成該介電體之材質係為模壓樹脂、預浸材或感光型介電層。
前述之封裝結構及其製法中，復包括形成第二線路層於該介電體上，且該第二線路層電性連接該第一導電層。
依上述，復包括形成絕緣保護層於該介電體與第二線路層上。
依上述，復包括形成第二導電層於該第二線路層上， 再形成介電層於該介電體上，且該介電層包覆該第二線路層與第二導電層。進一步地，復包括形成第三線路層於該介電層上，且該第三線路層電性連接該第二導電層。更進一步地，復包括形成絕緣保護層於該介電層與第三線路層上。
由上可知，本發明之封裝結構及其製法中，主要藉由該承載件之相對兩表面上分別製作線路層、導電層與介電材，故相較於習知技術之單面製作，本發明可將產量增加一倍，因而有效提高產能。
再者，藉由移除該承載件，以避免形成習知支撐架，故於形成該封裝膠體時，模具之填充空間能依需求調整降低，以利於縮小結構高度，因而能滿足薄化電子產品之需求。
又，本發明之製法係先形成線路層及導電層，再形成介電部，之後外露該導電層，以電性連接後續形成之線路，故此種方式無需於該介電部上使用雷射鑽孔來製作該導電層，因而能降低製作成本
1,2,2’,3,4‧‧‧封裝結構
10‧‧‧支撐架
11,21,21’,21”‧‧‧介電體
12‧‧‧線路層
13‧‧‧導電層
14,24‧‧‧電子元件
140,240,27‧‧‧導電元件
15,25‧‧‧封裝膠體
20‧‧‧承載件
20a,20b‧‧‧表面
200‧‧‧板體
201‧‧‧金屬層
22‧‧‧第一線路層
220‧‧‧第一感光型介電層
23‧‧‧第一導電層
230‧‧‧第二感光型介電層
26‧‧‧底膠
31‧‧‧絕緣保護層
32‧‧‧第二線路層
41‧‧‧介電層
42‧‧‧第三線路層
43‧‧‧第二導電層
90‧‧‧模具
900‧‧‧填充空間
h‧‧‧高度
h’‧‧‧厚度
第1A至1C圖係為習知封裝結構之製法的剖面示意圖；第2A至2E圖係為本發明之封裝結構之製法之第一實施例的剖面示意圖；其中，第2B’及2B”係為第2B圖之不同態樣，第2E’圖係第2E圖之另一態樣；第3A至3D圖係為本發明之封裝結構之製法之第二實 施例的剖面示意圖；以及第4A至4E圖係為本發明之封裝結構之製法之第三實施例的剖面示意圖。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
請參閱第2A至2E圖係顯示本發明之封裝結構2之製法之第一實施例的剖視圖。
如第2A圖所示，提供一具有相對之兩表面20a,20b之 承載件20。
於本實施例中，該承載件20之兩表面20a,20b係為金屬表面。具體地，該承載件20具有如金屬板、半導體晶圓或玻璃板之板體200與設於該板體200兩側之金屬層201，該金屬層201係為銅箔，且於該板體200與該金屬層201之間亦可依需求設有如離形膜、黏著材或絕緣材等之結合層(圖略)，以利於後續分離作業。
如第2B圖所示，於該承載件20之兩表面20a,20b上分別形成有一介電體21，且各該介電體21中係嵌埋有一第一線路層22與形成於該第一線路層22之部分表面上之一第一導電層23。
於本實施例中，形成該介電體21之材質如模壓樹脂(molding compound)、預浸材(prepreg)或感光型介電層，但不限於此，且該介電體21、第一線路層22與第一導電層23之製作順序並無特殊限制。
例如，可先於該承載件20之兩表面20a,20b上藉由第一光阻形成一第一線路層22，再藉由第二光阻形成一第一導電層23於該第一線路層22之部分表面上，之後移除該第一光阻與第二光阻，再以模封(molding)或壓合(laminate)方式形成該介電體21於該承載件20之兩表面20a,20b上。
或者，可先於該承載件20之兩表面20a,20b上藉由第一感光型介電層220形成一第一線路層22，再藉由第二感光型介電層230形成一第一導電層23於該第一線路層22 之部分表面上，令該第一與第二感光型介電層220,230作為該介電體21’，如第2B’圖所示。
又，該第一導電層23係外露於該介電體21之表面。例如，以模封或壓合方式形成該介電體21”於該承載件20之兩表面20a,20b上，如第2B”圖所示，該第一導電層23未外露於該介電體21”之表面，再以研磨(grinding)方式移除該介電體21”之部分上表面，使該第一導電層23外露於該介電體21之表面；或者，直接形成如第2B圖所示之介電體21之態樣。
另外，該第一線路層22係結合於該承載件20之兩表面20a,20b上。
如第2C圖所示，以分離方式，移除該承載件20之板體200。
如第2D圖所示，蝕刻移除該介電體21上之金屬層201，使該第一線路層22之表面低於該介電體21。
於本實施例中，蝕刻該金屬層201之同時，亦蝕刻該第一導電層23之表面，使該第一導電層23之表面低於該介電體21。
如第2E圖所示，設置至少一電子元件24於該介電體21上，且該電子元件24係電性連接至該第一線路層22。
於本實施例中，形成封裝膠體25於該介電體21上，使該封裝膠體25包覆該電子元件24。
再者，該電子元件24係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係 例如電阻、電容及電感。
又，該電子元件24藉由複數如銲錫材料或銅柱之導電元件240電性連接至該第一線路層22，且該封裝膠體25包覆該些導電元件240。於其它方式中，該電子元件24亦可依需求藉由打線方式(wire bonding)電性連接該第一線路層22。
另外，該第一導電層23上形成有複數如銲錫材料之導電元件27。
於另一實施例中，如第2E’圖所示，亦可先形成底膠26於該介電體21與該電子元件24之間，使該底膠26包覆該些導電元件240並固定該電子元件24，再形成封裝膠體25於該介電體21上，使該封裝膠體25包覆該電子元件24與該底膠26。
本發明之製法係於該承載件20之上下表面20a,20b分別製作第一線路層22、第一導電層23與介電體21,21’，故相較於習知技術之單面製作，本發明之製法可將產量增加一倍，因而有效提高產能。
再者，由於移除該承載件20，因而不會形成習知支撐架，故於形成該封裝膠體25時，模具之填充空間能依需求調整降低，以利於縮小本發明之封裝結構2’之高度，因此，本發明之封裝結構2’能滿足薄化電子產品之需求。
又，本發明之製法係先形成第一線路層22及第一導電層23，再形成該介電體21，之後外露該第一導電層23，以電性連接後續形成之線路，故此種方式無需於該介電體 21上使用雷射鑽孔以製作該第一導電層23，因而能降低製作成本。
請參閱第3A至3D圖係顯示本發明之封裝結構3之製法之第二實施例的剖視圖。
如第3A圖所示，係提供一如第2B圖之結構。
於本實施例中，有關第3A圖之結構之製作方式係可參考上述第2A至2B圖之製程的說明。
如第3B圖所示，藉由圖案化製程，形成一第二線路層32於該介電體21上，且該第二線路層32電性連接該第一導電層23。
如第3C圖所示，形成一絕緣保護層31於該介電體21與第二線路層32上。
於本實施例中，該第二線路層32係外露於該絕緣保護層31之表面。例如，先以壓合方式形成該絕緣保護層31於該介電體21上，該第二線路層32未外露於該絕緣保護層31之表面，再以研磨方式移除該絕緣保護層31之部分上表面，使該第二線路層32之表面齊平該絕緣保護層31之表面，而令該第二線路層32外露於該絕緣保護層31之表面。
如第3D圖所示，先以分離方式移除該承載件20之板體200，再蝕刻移除該介電體21上之金屬層201，使該第一線路層22之表面低於該介電體21。
於本實施例中，蝕刻該金屬層201之同時，亦蝕刻該第二線路層32之表面，使該第二線路層32之表面低於該 絕緣保護層31。
本發明之製法係先形成第一線路層22及第一導電層23，再形成該介電體21，之後外露該第一導電層23，以電性連接該第二線路層32，故此種方式無需於該介電體21上使用雷射鑽孔以製作該第一導電層23，因而能降低製作成本。
請參閱第4A至4E圖係顯示本發明之封裝結構4之製法之第二實施例的剖視圖。
如第4A圖所示，係接續第2B圖之製程，形成一第二線路層32於該介電體21上，且該第二線路層32電性連接該第一導電層23，再形成一第二導電層43於該第二線路層32之部分表面上。
於本實施例中，可先於該介電體21上藉由第一光阻形成一第二線路層32，再藉由第二光阻形成一第二導電層43於該第二線路層32之部分表面上，之後移除該第一光阻與第二光阻。
如第4B圖所示，形成一介電層41於該介電體21上，且該介電層41包覆該第二線路層32與第二導電層43。
於本實施例中，形成該介電層41之材質如模壓樹脂、預浸材或感光型介電層，但不限於此，且該介電層41之材質與該介電體21之材質可相同或不同。
再者，可以模封或壓合方式形成該介電層41於該介電體21上。或者，以如第2B’圖所示之方式製作該介電層41。
又，該第二導電層43係外露於該介電層41之表面。 例如，以如第2B”圖所示之方式形成該介電層41；或者，直接形成如第4B圖所示之介電層41之態樣。
另外，該介電層41、第二線路層32與第二導電層43之製作順序並無特殊限制。
如第4C圖所示，藉由圖案化製程，形成一第三線路層42於該介電層41上，且該第三線路層42電性連接該第二導電層43。
如第4D圖所示，形成一絕緣保護層31於該介電層41與第三線路層42上。
於本實施例中，該第三線路層42係外露於該絕緣保護層31之表面。例如，先以壓合方式形成該絕緣保護層31於該介電層41上，該第三線路層42未外露於該絕緣保護層31之表面，再以研磨方式移除該絕緣保護層31之部分上表面，使該第三線路層42之表面齊平該絕緣保護層31之表面，而令該第三線路層42外露於該絕緣保護層31之表面。
如第4E圖所示，先以分離方式移除該承載件20之板體200，再蝕刻移除該介電體21上之金屬層201，使該第一線路層22之表面低於該介電體21。
於本實施例中，蝕刻該金屬層201之同時，亦蝕刻該第三線路層42之表面，使該第三線路層42之表面低於該絕緣保護層31。
本發明之製法係先形成第二線路層32及第二導電層43，再形成該介電層41，之後外露該第二導電層43，以電 性連接該第三線路層42，故此種方式無需於該介電層41上使用雷射鑽孔以製作該第二導電層43，因而能降低製作成本。
本發明提供一種封裝結構2,3,4，係包括：一具有相對兩表面20a,20b之承載件20、以及分別形成於該承載件20之兩表面20a,20b上之二介電體21,21’。
所述之介電體21,21’中係嵌埋有一第一線路層22與形成於該第一線路層22上之一第一導電層23。
於一實施例中，該承載件20之兩表面20a,20b係為金屬表面。
於一實施例中，該第一線路層22係結合於該承載件20上。
於一實施例中，該第一導電層23係外露於該介電體21。
於一實施例中，形成該介電體21,21’之材質係為模壓樹脂、預浸材或感光型介電層。
於一實施例中，所述之封裝結構3,4復包括形成於該介電體21上之第二線路層32，且該第二線路層32電性連接該第一導電層23。
依上述，該封裝結構3又包括形成於該介電體21與第二線路層32上之一絕緣保護層31。
或者，該封裝結構4又包括形成於該第二線路層32上之一第二導電層43、及形成於該介電體21上之一介電層41，且該介電層41包覆該第二線路層32與第二導電層 43。該封裝結構4另包括形成於該介電層41上之一第三線路層42、及形成於該介電層41與第三線路層42上之一絕緣保護層31，且該第三線路層42電性連接該第二導電層43。
綜上所述，本發明封裝結構及其製法，藉由該承載件之上、下表面分別製作線路層、導電層與介電材，故相較於習知技術之單面製作，本發明之製法可將產量增加一倍，因而有效提高產能。
再者，由於移除該承載件，因而不會形成習知支撐架，故於形成該封裝膠體時，模具之填充空間能依需求調整降低，以利於縮小本發明之封裝結構之高度，因此，本發明之封裝結構能滿足薄化電子產品之需求。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
20‧‧‧承載件
20a,20b‧‧‧表面
21‧‧‧介電體
22‧‧‧第一線路層
23‧‧‧第一導電層

Claims (11)

  1. 一種封裝結構，係包括：承載件，係具有相對之兩表面，且該承載件之兩表面係為金屬表面；以及二介電體，係分別接觸地形成於該承載件之兩表面上，且各該介電體中係嵌埋有第一線路層與形成於該第一線路層上之第一導電層，其中，該第一導電層係外露於該介電體。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該第一線路層係結合於該承載件上。
  3. 如申請專利範圍第1項所述之封裝結構，其中，形成該介電體之材質係為模壓樹脂、預浸材或感光型介電層。
  4. 一種封裝結構之製法，係包括：提供一具有相對之兩表面之承載件，且該承載件之兩表面係為金屬表面；於該承載件之兩表面上分別接觸地形成一介電體，且各該介電體中係嵌埋有第一線路層與形成於該第一線路層上之第一導電層，其中，該第一導電層係外露於該介電體；以及移除該承載件。
  5. 如申請專利範圍第4項所述之封裝結構之製法，其中，係先於該承載件之兩表面上形成該第一線路層，再形成該第一導電層於該第一線路層之部分表面上，之後 形成該介電體於該承載件之兩表面上。
  6. 如申請專利範圍第4項所述之封裝結構之製法，其中，係先於該承載件之兩表面上藉由第一感光型介電層形成該第一線路層，再藉由第二感光型介電層形成該第一導電層於該第一線路層之部分表面上，並令該第一與第二感光型介電層作為該介電體。
  7. 如申請專利範圍第4項所述之封裝結構之製法，其中，係先形成該介電體於該承載件之兩表面上，且該第一導電層未外露於該介電體之表面，再移除該介電體之部分表面，使該第一導電層外露於該介電體之表面。
  8. 如申請專利範圍第4項所述之封裝結構之製法，其中，形成該介電體之材質係為模壓樹脂、預浸材或感光型介電層。
  9. 如申請專利範圍第4項所述之封裝結構之製法，復包括設置電子元件於該介電體上，且該電子元件係電性連接至該第一線路層。
  10. 如申請專利範圍第9項所述之封裝結構之製法，復包括形成封裝膠體於該介電體上，使該封裝膠體包覆該電子元件。
  11. 如申請專利範圍第9項所述之封裝結構之製法，復包括形成底膠於該介電體與該電子元件之間，使該底膠固定該電子元件。
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