TW201603213A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TW201603213A
TW201603213A TW103123435A TW103123435A TW201603213A TW 201603213 A TW201603213 A TW 201603213A TW 103123435 A TW103123435 A TW 103123435A TW 103123435 A TW103123435 A TW 103123435A TW 201603213 A TW201603213 A TW 201603213A
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layer
semiconductor package
semiconductor
encapsulation layer
opening
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TWI557860B (zh
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賴杰隆
戴瑞豐
陳賢文
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矽品精密工業股份有限公司
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Priority to CN201410362827.7A priority patent/CN105321894B/zh
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Abstract

一種半導體封裝件之製法，係先提供一設有半導體元件之承載件，再形成一具有至少一開口的封裝層於該承載件上，使該封裝層包覆該半導體元件，且該開口之側面係呈平滑表面；接著，形成線路層於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體，之後移除該承載件，以藉由同時製成該封裝層與該開口，不僅能避免該開口之壁面過於粗糙，且能大幅縮短製程時間。本發明復提供該半導體封裝件。

Description

半導體封裝件及其製法
本發明係有關一種封裝製程，特別是關於一種能避免雷射鑽孔之問題的半導體封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，例如，扇出式封裝堆疊(Fan Out Package on package，簡稱FO PoP)等，以配合各種晶片上大幅增加之輸入/出埠數量，進而將不同功能之積體電路整合於單一封裝結構，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1A至1F圖係為習知封裝堆疊裝置之其中一半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，設置一如晶片之半導體元件10於一承載件11之熱化離形層110上，再形成一封裝層13於該 熱化離形層110上以包覆該半導體元件10。
如第1B圖所示，將具有銅箔120之另一承載件12設於該封裝層13上。
如第1C圖所示，移除該承載件11及其熱化離形層110，以露出該半導體元件10與封裝層13。
如第1D圖所示，以雷射方式形成複數開口130於該半導體元件10周邊之封裝層13上。
如第1E圖所示，藉由該銅箔120電鍍導電材料於該些開口130中，以形成導電柱14，再於該封裝層13上形成複數線路重佈層(redistribution layer，簡稱RDL)15，以令該線路重佈層15電性連接該導電柱14與該半導體元件10之電極墊100。
如第1F圖所示，移除該另一承載件12，再利用該銅箔120進行圖案化線路製程，以形成一線路結構16，之後再進行切單製程。
惟，習知半導體封裝件1之製法中，因以雷射方式形成複數開口130，故雷射之熱效應會造成該開口130之壁面極為粗糙(如第1C圖所示之粗糙表面130a)，以致於當電鍍製作該導電柱14時，電鍍品質不佳，因而造成良率過低及產品可靠度不佳等問題。
再者，雖可使用蝕刻方式形成該開口130以避免發生該粗糙表面130a之狀況，但若要形成直徑100um以上的開口130，蝕刻方式之製程時間過長，因而會大幅增加成本。
另外，該熱化離形層110具有撓性，且其熱膨脹係數 (Coefficient of thermal expansion,CTE)與該封裝層13注入封裝用之模具時之膠體流動所產生之側推力，將一同影響該半導體元件10固定之精度，亦即容易使半導體元件10產生偏移，致使該半導體元件10未置於該熱化離形層之預定位置上。故而，該線路重佈層15與該半導體元件10之電極墊100間的對位將產生偏移，當該承載件11之尺寸越大時，各該半導體元件10間之位置公差亦隨之加大，而當偏移公差過大時，將使該線路重佈層15無法與該電極墊100連接，亦即對該線路重佈層15與該半導體元件10間之電性連接造成極大影響，因而造成良率過低及產品可靠度不佳等問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種半導體封裝件，係包括：至少一半導體元件；一具有相對之第一表面與第二表面的封裝層，係包覆該半導體元件，該封裝層係具有至少一開口及至少一開槽，該開口係連通該第一及第二表面，該開槽係連通該第二表面並呈現絕緣狀態，其中，該開口之側面與該開槽之側面係呈平滑表面；以及線路層，係設於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體。
本發明復提供一種半導體封裝件之製法，係包括：提供一設有至少一半導體元件之承載件；形成一具有至少一 開口的封裝層於該承載件上，使該封裝層包覆該半導體元件，且該封裝層與該開口係一同製成，該封裝層係具有相對之第一表面與第二表面，該第一表面係結合該承載件，該開口係連通該第一及第二表面，其中，該開口之側面係呈平滑表面；形成線路層於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體；以及移除該承載件。
前述之半導體封裝件中，該開槽係位於該半導體元件與該開口之間。
前述之製法中，該封裝層係以模封製程或壓合製程形成者。
前述之製法中，該封裝層之製程係包括：提供一其內具有至少一凸部之模具；設置該承載件與該半導體元件於該模具中，且形成封裝材於該模具中，以令該封裝材成為該封裝層，且該封裝層於對應該凸部之處係成為該開口；以及移除該模具。例如，該封裝層之步驟係包括：將該封裝材形成於該模具中；將該承載件與該半導體元件設於該模具中；以及壓合該封裝材與該承載件，使該封裝層包覆該半導體元件。或者，該封裝層之步驟係包括：將該承載件與該半導體元件設於該模具中；以及將該封裝材填入該模具中，使該封裝層包覆該半導體元件。
依上述，該模具內復設有至少一定位塊，使該半導體元件受制於該定位塊而定位。因此，於形成該封裝材後，該封裝層復形成有連通該第二表面之開槽，且該開槽係位於該半導體元件與該開口之間，又該開槽係呈現絕緣狀 態，其中，該開槽之側面係呈平滑表面，而該開槽之型式係為長條狀或孔狀。
前述之半導體封裝件及其製法中，該半導體元件之作用面係齊平該封裝層之第一表面。
前述之半導體封裝件及其製法中，該半導體元件之非作用面係齊平該封裝層之第二表面。
前述之半導體封裝件及其製法中，形成該導電體之材質係包含銅、鋁、鈦或其至少二者之組合。
前述之半導體封裝件及其製法中，復包括形成絕緣保護層於該封裝層之第二表面與該線路層上，且該絕緣保護層係露出該線路層之部分表面。
另外，前述之半導體封裝件及其製法中，復包括移除該承載件之後，形成線路結構於該封裝層之第一表面上，且該線路結構電性連接該導電體及/或該半導體元件。例如，該線路結構係包含至少一線路重佈層。
由上可知，本發明之半導體封裝件及其製法中，藉由該封裝層與該些開口一同製成，使該開口之壁面之粗糙度極低，因而當電鍍製作該導電體時，能提升電鍍品質，以避免良率過低及產品可靠度不佳等問題。
再者，藉由該封裝層與該些開口一同製成，能大幅縮短製程時間。
又，藉由模具之定位塊，以於形成該封裝層時，能限制該半導體元件之位移，而達到定位該半導體元件之目的。
1,2,2’,4‧‧‧半導體封裝件
10,20‧‧‧半導體元件
100,200‧‧‧電極墊
11,21‧‧‧承載件
110‧‧‧熱化離形層
12‧‧‧另一承載件
120‧‧‧銅箔
13,23‧‧‧封裝層
130,230‧‧‧開口
130a‧‧‧粗糙表面
14‧‧‧導電柱
15,260‧‧‧線路重佈層
16,26‧‧‧線路結構
20a‧‧‧作用面
20b‧‧‧非作用面
210‧‧‧間隔層
22‧‧‧封裝材
23a‧‧‧第一表面
23b‧‧‧第二表面
231‧‧‧開槽
24‧‧‧線路層
240‧‧‧導電體
241‧‧‧電性接觸墊
242‧‧‧表面處理層
25‧‧‧絕緣保護層
250‧‧‧開孔
27,28‧‧‧導電元件
3‧‧‧電子裝置
40‧‧‧封裝基板
41‧‧‧晶片
9‧‧‧模具
9a‧‧‧第一模體
9b‧‧‧第二模體
90‧‧‧凸部
91‧‧‧定位塊
92‧‧‧離形膜
S‧‧‧切割路徑
第1A至1F圖係為習知半導體封裝件之製法之剖面示意圖；第2A至2H圖係為本發明半導體封裝件之製法之剖視示意圖；其中，第2A’圖係為第2A圖之承載件與半導體晶片之上視平面圖，第2A”圖係為第2A圖之第一模體之局部上視平面圖，第2B’圖係為第2B圖之另一方式，第2H’圖係為第2H圖之另一實施例；以及第3圖係為本發明半導體封裝件之後續應用之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明半導體封裝件2之製法之剖視示意圖。
如第2A及2A’圖所示，提供一設有複數半導體元件20之承載件21，且提供一其內具有複數凸部90及複數定位塊91之模具9。
於本實施例中，各該半導體元件20具有相對之作用面20a與非作用面20b，且該作用面20a具有複數電極墊200。
再者，該承載件21可選用金屬板、半導體晶圓或玻璃板，且該承載件21具有一如離形膜、黏著材、絕緣材等之間隔層210，以供接合該半導體元件20之作用面20a。
又，該模具9係包含第一模體9a與第二模體9b，該些凸部90及定位塊91係設於該第一模體9a，且該第一模體9a表面設有一離形膜92。
另外，該凸部90係為錐形柱結構，該些定位塊91係為尖錐，且該凸部90之長度係大於該定位塊91之長度，該些定位塊91並對應該半導體元件20之形狀排設，而該些凸部90係位於該些定位塊91之外圍，如第2A”圖所示。
如第2B圖所示，將如樹脂之封裝材22形成於該模具9之第一模體9a上，且將該承載件21與該半導體元件20設於該模具9之第二模體9b上。
如第2C圖所示，壓合該第一模體9a與第二模體9b(即壓合該封裝材22與該承載件21)，使該封裝材22成為封裝層23而包覆該半導體元件20，且該封裝層23於對應各該凸部90之處係成為開口230，而該封裝層23於對應各 該定位塊91之處係成為開槽231。
於本實施例中，該封裝層23、該些開口230與該些開槽231係一同製成，且於形成該封裝層23時，該定位塊91會限制該半導體元件20之位移範圍，使該半導體元件20不會受該封裝材22壓迫而過度位移，故藉由該定位塊91之設計能達到定位該半導體元件20之效果。
於另一實施例中，亦可先將該承載件21與該半導體元件20設於該模具9中，如第2B’圖所示，再以模封(molding)方式將封裝材22填入該模具9中，使該封裝層23包覆該半導體元件20。
再者，該開槽231之型式可為長條狀或孔狀，如依該定位塊91之形狀。
如第2D圖所示，移除該模具9，以外露出該半導體元件20之非作用面20b、該承載件21與該封裝層23，且藉由該離形膜92以利於分離該模具9與該封裝層23。
於本實施例中，該封裝層23具有相對之第一表面23a及第二表面23b，且該第一表面23a係結合於該承載件21。
再者，各該開口230係位於該半導體元件20周邊區域並連通該第一及第二表面23a,23b。
又，各該開槽231係連通該第二表面23b而未連通該第一表面23a並位於該半導體元件20與該些開口230之間。
另外，該半導體元件20之非作用面20b係齊平該封裝層23之第二表面23b。
如第2E圖所示，進行RDL製程，以形成一線路層24於該封裝層23之第二表面23b上，且該線路層24具有形成於該開口230中之導電體240。
於本實施例中，該導電體240係為導電柱，且形成該導電體240之材質係包含銅、鋁、鈦或其至少二者之組合。
再者，形成一絕緣保護層25於該封裝層23之第二表面23b與該線路層24上，且該絕緣保護層25係形成有複數開孔250，以令該線路層24之部分表面外露出該些開孔250，俾供作為電性接觸墊241。
又，各該電性接觸墊241上可依需求形成表面處理層242，且形成該表面處理層242之材質係為鎳、鈀、金所組群組之合金、多層金屬或有機保焊劑(Organic Solderability Preservative，簡稱OSP)所組成之群組中之其中一者，例如，電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)等，但不限於上述。
另外，各該開槽231係呈現絕緣狀態，例如，該絕緣保護層25填滿各該開槽231。
如第2F圖所示，移除該承載件21及其該間隔層210，以外露出該半導體元件20之作用面20a、該封裝層23之第一表面23a與導電體240之底端。
於本實施例中，該半導體元件20之作用面20a係齊平該封裝層23之第一表面23a。
如第2G圖所示，形成一線路結構26於該封裝層23 之第一表面23a上，使該線路結構26電性連接該導電體240與該半導體元件20之電極墊200。
於本實施例中，該線路結構26係包含至少一線路重佈層(redistribution layer,RDL)260與設於最外層線路重佈層260上之複數導電元件27，且該導電元件27係包含銲錫材料。
如第2H圖所示，沿如第2G圖所示之切割路徑S進行切單製程，以獲取複數該半導體封裝件2。
於另一實施例中，當該模具9未具有定位塊91時，該封裝層23不會形成開槽231，因而將製成如第2H’圖所示之半導體封裝件2’，且於此製程中，該模具9之凸部90可依需求兼具定位該半導體元件20之用，例如該凸部90之位置更靠近該半導體元件20。
本發明之製法中，藉由在模封或壓合製程的模具9上設置凸部90，以利用該些凸部90形成該開口230，使該封裝層23與該些開口230係一同製成，故該開口230之壁面之粗糙度極低(例如，該開口230之側面與該開槽231之側面係呈平滑表面)，因而當電鍍製作該導電體240時，能提升電鍍品質，以避免良率過低及產品可靠度不佳等問題。
再者，於模封或壓合製程時，同時製成該封裝層23與該些開口230，因而能大幅縮短製程時間，故若要形成直徑100um以上的開口230，其製程時間極短，因而利於降低成本。
又，藉由在模具9上設置定位塊91，以於模封或壓合製程時限制該半導體元件20之位移，故於量產時，當該承載件21之尺寸越大時，該半導體元件20間之位置公差不會隨之加大。因此，於製作該線路結構26時，該線路重佈層260與該電極墊200間之電性連接能有效對接，因而能提高良率及提升產品可靠度。
另外，於後續製程中，如第3圖所示，該半導體封裝件2可藉由該些導電元件27接置如電路板之電子裝置3，且該些電性接觸墊241可藉由複數導電元件28接置另一半導體封裝件4，以形成封裝堆疊裝置，其中，該另一半導體封裝件4係包含一封裝基板40與至少一晶片41。
本發明提供一種半導體封裝件2，係包括：一半導體元件20、一具有相對之第一表面23a與第二表面23b的封裝層23、以及一線路層24。
所述之半導體元件20係具有相對之作用面20a與非作用面20b，且該作用面20a具有複數電極墊200。
所述之封裝層23係包覆該半導體元件20，且該封裝層23具有至少一開口230及至少一開槽231，該開口230係連通該第一及第二表面23a,23b，該開槽231係連通該第二表面23b而未連通該第一表面23a並呈現絕緣狀態，其中，該開口230之側面與該開槽231之側面係呈平滑表面。
所述之線路層24係設於該封裝層23之第二表面23b上，且該線路層24具有形成於該開口230中之導電體240。
於一實施例中，該開槽231係位於該半導體元件20 與該開口230之間。
於一實施例中，形成該導電體240之材質係包含銅、鋁、鈦或其至少二者之組合。
於一實施例中，所述之半導體封裝件2復包括一絕緣保護層25，係設於該封裝層23之第二表面23b與該線路層24上，且該絕緣保護層25係露出該線路層24之部分表面。
於一實施例中，所述之半導體封裝件2復包括一線路結構26，係設於該封裝層23之第一表面23a上，且該線路結構26電性連接該導電體240與該半導體元件20。該線路結構26係包含至少一線路重佈層260。
綜上所述，本發明之半導體封裝件及其製法中，藉由該封裝層與該些開口一同製成，不僅能避免該開口之壁面過於粗糙，且能大幅縮短製程時間。
再者，藉由模具之定位塊，以於形成該封裝層時限制該半導體元件之位移，而達到定位該半導體元件之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20‧‧‧半導體元件
21‧‧‧承載件
210‧‧‧間隔層
23‧‧‧封裝層
230‧‧‧開口
231‧‧‧開槽
9‧‧‧模具
9a‧‧‧第一模體
9b‧‧‧第二模體
90‧‧‧凸部
91‧‧‧定位塊

Claims (26)

  1. 一種半導體封裝件，係包括：至少一半導體元件；一具有相對之第一表面與第二表面的封裝層，係包覆該半導體元件，該封裝層係具有至少一開口及至少一開槽，該開口係連通該第一及第二表面，該開槽係連通該第二表面並呈現絕緣狀態，其中，該開口之側面係呈平滑表面；以及線路層，係設於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之作用面係齊平該封裝層之第一表面。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之非作用面係齊平該封裝層之第二表面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該開槽之側面係呈平滑表面。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該開槽係位於該半導體元件與該開口之間。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該開槽之型式係為長條狀或孔狀。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，形成該導電體之材質係包含銅、鋁、鈦或其至少二者之組合。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣保護層，係設於該封裝層之第二表面與該線路層上，且該絕緣保護層係露出該線路層之部分表面。
  9. 如申請專利範圍第1項所述之半導體封裝件，復包括線路結構，係設於該封裝層之第一表面上，且該線路結構電性連接該導電體及/或該半導體元件。
  10. 如申請專利範圍第9項所述之半導體封裝件，其中，該線路結構係包含至少一線路重佈層。
  11. 一種半導體封裝件之製法，係包括：提供一設有至少一半導體元件之承載件；形成一具有至少一開口的封裝層於該承載件上，使該封裝層包覆該半導體元件，且該封裝層與該開口係一同製成，該封裝層係具有相對之第一表面與第二表面，該第一表面係結合該承載件，該開口係連通該第一及第二表面，其中，該開口之側面係呈平滑表面；形成線路層於該封裝層之第二表面上，且該線路層具有形成於該開口中之導電體；以及移除該承載件。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該封裝層係以模封製程或壓合製程形成者。
  13. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該封裝層之製程係包括：提供一其內具有至少一凸部之模具；設置該承載件與該半導體元件於該模具中，且形 成封裝材於該模具中，以令該封裝材成為該封裝層，且該封裝層於對應該凸部之處係成為該開口；以及移除該模具。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該封裝層之步驟係包括：將該封裝材形成於該模具中；將該承載件與該半導體元件設於該模具中；以及壓合該封裝材與該承載件。
  15. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該封裝層之步驟係包括：將該承載件與該半導體元件設於該模具中；以及將該封裝材填入該模具中。
  16. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該模具內復設有至少一定位塊，使該半導體元件受制於該定位塊而定位。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，其中，於形成該封裝材後，該封裝層復形成有連通該第二表面之開槽，且該開槽之側面係呈平滑表面。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該開槽係位於該半導體元件與該開口之間。
  19. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該開槽係呈現絕緣狀態。
  20. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該開槽之型式係為長條狀或孔狀。
  21. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該半導體元件之作用面係齊平該封裝層之第一表面。
  22. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該半導體元件之非作用面係齊平該封裝層之第二表面。
  23. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，形成該導電體之材質係包含銅、鋁、鈦或其至少二者之組合。
  24. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括形成絕緣保護層於該封裝層之第二表面與該線路層上，且該絕緣保護層係露出該線路層之部分表面。
  25. 如申請專利範圍第11項所述之半導體封裝件之製法，復包括移除該承載件之後，形成線路結構於該封裝層之第一表面上，且該線路結構電性連接該導電體及/或該半導體元件。
  26. 如申請專利範圍第25項所述之半導體封裝件之製法，其中，該線路結構係包含至少一線路重佈層。
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