CN105321894B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN105321894B
CN105321894B CN201410362827.7A CN201410362827A CN105321894B CN 105321894 B CN105321894 B CN 105321894B CN 201410362827 A CN201410362827 A CN 201410362827A CN 105321894 B CN105321894 B CN 105321894B
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semiconductor package
encapsulated layer
package part
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CN105321894A (zh
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赖杰隆
戴瑞丰
陈贤文
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该制法为先提供一设有半导体元件的承载件，再形成一具有至少一开口的封装层于该承载件上，使该封装层包覆该半导体元件，且该开口的侧面呈平滑表面；接着，形成线路层于该封装层的第二表面上，且该线路层具有形成于该开口中的导电体，之后移除该承载件，以藉由同时制成该封装层与该开口，不仅能避免该开口的壁面过于粗糙，且能大幅缩短制程时间。

Description

半导体封装件及其制法
技术领域
本发明涉及一种封装制程，特别是关于一种能避免激光钻孔的问题的半导体封装件及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂开发出不同的立体封装技术，例如，扇出式封装堆迭(Fan Out Package on package，简称FO PoP)等，以配合各种晶片上大幅增加的输入/出埠数量，进而将不同功能的积体电路整合于单一封装结构，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：记忆体、中央处理器、绘图处理器、影像应用处理器等，藉由堆迭设计达到系统的整合，适合应用于轻薄型各种电子产品。
图1A至图1F为现有封装堆迭装置的其中一半导体封装件1的制法的剖面示意图。
如图1A所示，设置一如晶片的半导体元件10于一承载件11的热化离形层110上，再形成一封装层13于该热化离形层110上以包覆该半导体元件10。
如图1B所示，将具有铜箔120的另一承载件12设于该封装层13上。
如图1C所示，移除该承载件11及其热化离形层110，以露出该半导体元件10与封装层13。
如图1D所示，以激光方式形成多个开口130于该半导体元件10周边的封装层13上。
如图1E所示，藉由该铜箔120电镀导电材料于该些开口130中，以形成导电柱14，再于该封装层13上形成多个线路重布层(redistribution layer，简称RDL)15，以令该线路重布层15电性连接该导电柱14与该半导体元件10的电极垫100。
如图1F所示，移除该另一承载件12，再利用该铜箔120进行图案化线路制程，以形成一线路结构16，之后再进行切单制程。
惟，现有半导体封装件1的制法中，因以激光方式形成多个开口130，所以激光的热效应会造成该开口130的壁面极为粗糙(如图1C所示的粗糙表面130a)，以致于当电镀制作该导电柱14时，电镀品质不佳，因而造成良率过低及产品可靠度不佳等问题。
此外，虽可使用蚀刻方式形成该开口130以避免发生该粗糙表面130a的状况，但若要形成直径100um以上的开口130，蚀刻方式的制程时间过长，因而会大幅增加成本。
另外，该热化离形层110具有挠性，且其热膨胀系数(Coefficient of thermalexpansion,CTE)与该封装层13注入封装用的模具时的胶体流动所产生的侧推力，将一同影响该半导体元件10固定的精度，也就是容易使半导体元件10产生偏移，致使该半导体元件10未置于该热化离形层的预定位置上。故而，该线路重布层15与该半导体元件10的电极垫100间的对位将产生偏移，当该承载件11的尺寸越大时，各该半导体元件10间的位置公差也随之加大，而当偏移公差过大时，将使该线路重布层15无法与该电极垫100连接，也就是对该线路重布层15与该半导体元件10间的电性连接造成极大影响，因而造成良率过低及产品可靠度不佳等问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的目的为提供一种半导体封装件及其制法，不仅能避免该开口的壁面过于粗糙，且能大幅缩短制程时间。
本发明的半导体封装件，包括：至少一半导体元件；一具有相对的第一表面与第二表面的封装层，其包覆该半导体元件，该封装层具有至少一开口及至少一开槽，该开口连通该第一及第二表面，该开槽连通该第二表面并呈现绝缘状态，其中，该开口的侧面与该开槽的侧面呈平滑表面；以及线路层，其设于该封装层的第二表面上，且该线路层具有形成于该开口中的导电体。
本发明还提供一种半导体封装件的制法，包括：提供一设有至少一半导体元件的承载件；形成一具有至少一开口的封装层于该承载件上，使该封装层包覆该半导体元件，且该封装层与该开口为一同制成，该封装层具有相对的第一表面与第二表面，该第一表面结合该承载件，该开口连通该第一及第二表面，其中，该开口的侧面呈平滑表面；形成线路层于该封装层的第二表面上，且该线路层具有形成于该开口中的导电体；以及移除该承载件。
前述的半导体封装件中，该开槽位于该半导体元件与该开口之间。
前述的制法中，该封装层以模封制程或压合制程形成者。
前述的制法中，该封装层的制程包括：提供一其内具有至少一凸部的模具；设置该承载件与该半导体元件于该模具中，且形成封装材于该模具中，以令该封装材成为该封装层，且该封装层于对应该凸部之处成为该开口；以及移除该模具。例如，该封装层的步骤包括：将该封装材形成于该模具中；将该承载件与该半导体元件设于该模具中；以及压合该封装材与该承载件，使该封装层包覆该半导体元件。或者，该封装层的步骤包括：将该承载件与该半导体元件设于该模具中；以及将该封装材填入该模具中，使该封装层包覆该半导体元件。
依上述，该模具内还设有至少一定位块，使该半导体元件受制于该定位块而定位。因此，于形成该封装材后，该封装层还形成有连通该第二表面的开槽，且该开槽位于该半导体元件与该开口之间，又该开槽呈现绝缘状态，其中，该开槽的侧面呈平滑表面，而该开槽的型式为长条状或孔状。
前述的半导体封装件及其制法中，该半导体元件的作用面齐平该封装层的第一表面。
前述的半导体封装件及其制法中，该半导体元件的非作用面齐平该封装层的第二表面。
前述的半导体封装件及其制法中，形成该导电体的材质包含铜、铝、钛或其至少二者的组合。
前述的半导体封装件及其制法中，还包括形成绝缘保护层于该封装层的第二表面与该线路层上，且该绝缘保护层露出该线路层的部分表面。
另外，前述的半导体封装件及其制法中，还包括移除该承载件之后，形成线路结构于该封装层的第一表面上，且该线路结构电性连接该导电体及/或该半导体元件。例如，该线路结构包含至少一线路重布层。
由上可知，本发明的半导体封装件及其制法中，藉由该封装层与该些开口一同制成，使该开口的壁面的粗糙度极低，因而当电镀制作该导电体时，能提升电镀品质，以避免良率过低及产品可靠度不佳等问题。
此外，藉由该封装层与该些开口一同制成，能大幅缩短制程时间。
又，藉由模具的定位块，以于形成该封装层时，能限制该半导体元件的位移，而达到定位该半导体元件的目的。
附图说明
图1A至图1F为现有半导体封装件的制法的剖面示意图；
图2A至图2H为本发明半导体封装件的制法的剖视示意图；其中，图2A’为图2A的承载件与半导体晶片的上视平面图，图2A”为图2A的第一模体的局部上视平面图，图2B’为图2B的另一方式，图2H’为图2H的另一实施例；以及
图3为本发明半导体封装件之后续应用的剖视示意图。
符号说明
1,2,2’,4 半导体封装件
10,20 半导体元件
100,200 电极垫
11,21 承载件
110 热化离形层
12 另一承载件
120 铜箔
13,23 封装层
130,230 开口
130a 粗糙表面
14 导电柱
15,260 线路重布层
16,26 线路结构
20a 作用面
20b 非作用面
210 间隔层
22 封装材
23a 第一表面
23b 第二表面
231 开槽
24 线路层
240 导电体
241 电性接触垫
242 表面处理层
25 绝缘保护层
250 开孔
27,28 导电元件
3 电子装置
40 封装基板
41 晶片
9 模具
9a 第一模体
9b 第二模体
90 凸部
91 定位块
92 离形膜
S 切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2H为本发明半导体封装件2的制法的剖视示意图。
如图2A及图2A’所示，提供一设有多个半导体元件20的承载件21，且提供一其内具有多个凸部90及多个定位块91的模具9。
于本实施例中，各该半导体元件20具有相对的作用面20a与非作用面20b，且该作用面20a具有多个电极垫200。
此外，该承载件21可选用金属板、半导体晶圆或玻璃板，且该承载件21具有一如离形膜、粘着材、绝缘材等的间隔层210，以供接合该半导体元件20的作用面20a。
又，该模具9包含第一模体9a与第二模体9b，该些凸部90及定位块91设于该第一模体9a，且该第一模体9a表面设有一离形膜92。
另外，该凸部90为锥形柱结构，该些定位块91为尖锥，且该凸部90的长度大于该定位块91的长度，该些定位块91并对应该半导体元件20的形状排设，而该些凸部90位于该些定位块91的外围，如图2A”所示。
如图2B所示，将如树脂的封装材22形成于该模具9的第一模体9a上，且将该承载件21与该半导体元件20设于该模具9的第二模体9b上。
如图2C所示，压合该第一模体9a与第二模体9b(即压合该封装材22与该承载件21)，使该封装材22成为封装层23而包覆该半导体元件20，且该封装层23于对应各该凸部90之处成为开口230，而该封装层23于对应各该定位块91之处成为开槽231。
于本实施例中，该封装层23、该些开口230与该些开槽231为一同制成，且于形成该封装层23时，该定位块91会限制该半导体元件20的位移范围，使该半导体元件20不会受该封装材22压迫而过度位移，所以藉由该定位块91的设计能达到定位该半导体元件20的效果。
于另一实施例中，也可先将该承载件21与该半导体元件20设于该模具9中，如图2B’所示，再以模封(molding)方式将封装材22填入该模具9中，使该封装层23包覆该半导体元件20。
此外，该开槽231的型式可为长条状或孔状，如依该定位块91的形状。
如图2D所示，移除该模具9，以外露出该半导体元件20的非作用面20b、该承载件21与该封装层23，且藉由该离形膜92以利于分离该模具9与该封装层23。
于本实施例中，该封装层23具有相对的第一表面23a及第二表面23b，且该第一表面23a结合于该承载件21。
此外，各该开口230位于该半导体元件20周边区域并连通该第一及第二表面23a,23b。
又，各该开槽231连通该第二表面23b而未连通该第一表面23a并位于该半导体元件20与该些开口230之间。
另外，该半导体元件20的非作用面20b齐平该封装层23的第二表面23b。
如图2E所示，进行RDL制程，以形成一线路层24于该封装层23的第二表面23b上，且该线路层24具有形成于该开口230中的导电体240。
于本实施例中，该导电体240为导电柱，且形成该导电体240的材质包含铜、铝、钛或其至少二者的组合。
此外，形成一绝缘保护层25于该封装层23的第二表面23b与该线路层24上，且该绝缘保护层25形成有多个开孔250，以令该线路层24的部分表面外露出该些开孔250，以供作为电性接触垫241。
又，各该电性接触垫241上可依需求形成表面处理层242，且形成该表面处理层242的材质为镍、钯、金所组群组的合金、多层金属或有机保焊剂(Organic SolderabilityPreservative,简称OSP)所组成的群组中的其中一者，例如，电镀镍/金、化学镀镍/金、化镍浸金(ENIG)、化镍钯浸金(ENEPIG)、化学镀锡(Immersion Tin)等，但不限于上述。
另外，各该开槽231呈现绝缘状态，例如，该绝缘保护层25填满各该开槽231。
如图2F所示，移除该承载件21及其该间隔层210，以外露出该半导体元件20的作用面20a、该封装层23的第一表面23a与导电体240的底端。
于本实施例中，该半导体元件20的作用面20a齐平该封装层23的第一表面23a。
如图2G所示，形成一线路结构26于该封装层23的第一表面23a上，使该线路结构26电性连接该导电体240与该半导体元件20的电极垫200。
于本实施例中，该线路结构26包含至少一线路重布层(redistribution layer,RDL)260与设于最外层线路重布层260上的多个导电元件27，且该导电元件27包含焊锡材料。
如图2H所示，沿如图2G所示的切割路径S进行切单制程，以获取多个该半导体封装件2。
于另一实施例中，当该模具9未具有定位块91时，该封装层23不会形成开槽231，因而将制成如图2H’所示的半导体封装件2’，且于此制程中，该模具9的凸部90可依需求兼具定位该半导体元件20之用，例如该凸部90的位置更靠近该半导体元件20。
本发明的制法中，藉由在模封或压合制程的模具9上设置凸部90，以利用该些凸部90形成该开口230，使该封装层23与该些开口230为一同制成，所以该开口230的壁面的粗糙度极低(例如，该开口230的侧面与该开槽231的侧面呈平滑表面)，因而当电镀制作该导电体240时，能提升电镀品质，以避免良率过低及产品可靠度不佳等问题。
此外，于模封或压合制程时，同时制成该封装层23与该些开口230，因而能大幅缩短制程时间，所以若要形成直径100um以上的开口230，其制程时间极短，因而利于降低成本。
又，藉由在模具9上设置定位块91，以于模封或压合制程时限制该半导体元件20的位移，所以于量产时，当该承载件21的尺寸越大时，该半导体元件20间的位置公差不会随之加大。因此，于制作该线路结构26时，该线路重布层260与该电极垫200间的电性连接能有效对接，因而能提高良率及提升产品可靠度。
另外，于后续制程中，如图3所示，该半导体封装件2可藉由该些导电元件27接置如电路板的电子装置3，且该些电性接触垫241可藉由多个导电元件28接置另一半导体封装件4，以形成封装堆迭装置，其中，该另一半导体封装件4包含一封装基板40与至少一晶片41。
本发明提供一种半导体封装件2，包括：一半导体元件20、一具有相对的第一表面23a与第二表面23b的封装层23、以及一线路层24。
所述的半导体元件20具有相对的作用面20a与非作用面20b，且该作用面20a具有多个电极垫200。
所述的封装层23包覆该半导体元件20，且该封装层23具有至少一开口230及至少一开槽231，该开口230连通该第一及第二表面23a,23b，该开槽231连通该第二表面23b而未连通该第一表面23a并呈现绝缘状态，其中，该开口230的侧面与该开槽231的侧面呈平滑表面。
所述的线路层24设于该封装层23的第二表面23b上，且该线路层24具有形成于该开口230中的导电体240。
于一实施例中，该开槽231位于该半导体元件20与该开口230之间。
于一实施例中，形成该导电体240的材质包含铜、铝、钛或其至少二者的组合。
于一实施例中，所述的半导体封装件2还包括一绝缘保护层25，其设于该封装层23的第二表面23b与该线路层24上，且该绝缘保护层25露出该线路层24的部分表面。
于一实施例中，所述的半导体封装件2还包括一线路结构26，其设于该封装层23的第一表面23a上，且该线路结构26电性连接该导电体240与该半导体元件20。该线路结构26包含至少一线路重布层260。
综上所述，本发明的半导体封装件及其制法中，藉由该封装层与该些开口一同制成，不仅能避免该开口的壁面过于粗糙，且能大幅缩短制程时间。
此外，藉由模具的定位块，以于形成该封装层时限制该半导体元件的位移，而达到定位该半导体元件的目的。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (24)

1.一种半导体封装件，包括：
至少一半导体元件；
一具有相对的第一表面与第二表面的封装层，其包覆该半导体元件，该封装层具有至少一开口及至少一开槽，该开口连通该第一及第二表面，该开槽连通该第二表面并呈现绝缘状态，其中，该开口的侧面呈平滑表面；
线路层，其设于该封装层的第二表面上，且该线路层具有形成于该开口中的导电体；以及
绝缘保护层，其设于该封装层的第二表面与该线路层上并填满各该开槽，且该绝缘保护层露出该线路层的部分表面。
2.如权利要求1所述的半导体封装件，其特征为，该半导体元件的作用面齐平该封装层的第一表面。
3.如权利要求1所述的半导体封装件，其特征为，该半导体元件的非作用面齐平该封装层的第二表面。
4.如权利要求1所述的半导体封装件，其特征为，该开槽的侧面呈平滑表面。
5.如权利要求1所述的半导体封装件，其特征为，该开槽位于该半导体元件与该开口之间。
6.如权利要求1所述的半导体封装件，其特征为，该开槽的型式为长条状或孔状。
7.如权利要求1所述的半导体封装件，其特征为，形成该导电体的材质包含铜、铝、钛或其至少二者的组合。
8.如权利要求1所述的半导体封装件，其特征为，该半导体封装件还包括线路结构，其设于该封装层的第一表面上，且该线路结构电性连接该导电体及/或该半导体元件。
9.如权利要求8所述的半导体封装件，其特征为，该线路结构包含至少一线路重布层。
10.一种半导体封装件的制法，其包括：
提供一设有至少一半导体元件的承载件；
形成一具有至少一开口的封装层于该承载件上，使该封装层包覆该半导体元件，且该封装层与该开口为一同制成，该封装层具有相对的第一表面与第二表面，该第一表面结合该承载件，该开口连通该第一及第二表面，其中，该开口的侧面呈平滑表面，且该封装层还形成有连通该第二表面的开槽；
形成线路层于该封装层的第二表面上，且该线路层具有形成于该开口中的导电体；
形成绝缘保护层于该封装层的第二表面与该线路层上并填满各该开槽，且该绝缘保护层露出该线路层的部分表面；以及
移除该承载件。
11.如权利要求10所述的半导体封装件的制法，其特征为，该封装层为以模封制程或压合制程形成者。
12.如权利要求10所述的半导体封装件的制法，其特征为，该封装层的制程包括：
提供一其内具有至少一凸部的模具；
设置该承载件与该半导体元件于该模具中，且形成封装材于该模具中，以令该封装材成为该封装层，且该封装层于对应该凸部之处成为该开口；以及
移除该模具。
13.如权利要求12所述的半导体封装件的制法，其特征为，该封装层的步骤包括：
将该封装材形成于该模具中；
将该承载件与该半导体元件设于该模具中；以及
压合该封装材与该承载件。
14.如权利要求12所述的半导体封装件的制法，其特征为，该封装层的步骤包括：
将该承载件与该半导体元件设于该模具中；以及
将该封装材填入该模具中。
15.如权利要求12所述的半导体封装件的制法，其特征为，该模具内还设有至少一定位块，使该半导体元件受制于该定位块而定位。
16.如权利要求15所述的半导体封装件的制法，其特征为，该开槽的侧面呈平滑表面。
17.如权利要求16所述的半导体封装件的制法，其特征为，该开槽位于该半导体元件与该开口之间。
18.如权利要求16所述的半导体封装件的制法，其特征为，该开槽呈现绝缘状态。
19.如权利要求16所述的半导体封装件的制法，其特征为，该开槽的型式为长条状或孔状。
20.如权利要求10所述的半导体封装件的制法，其特征为，该半导体元件的作用面齐平该封装层的第一表面。
21.如权利要求10所述的半导体封装件的制法，其特征为，该半导体元件的非作用面齐平该封装层的第二表面。
22.如权利要求10项所述的半导体封装件的制法，其特征为，形成该导电体的材质包含铜、铝、钛或其至少二者的组合。
23.如权利要求10所述的半导体封装件的制法，其特征为，该制法还包括移除该承载件之后，形成线路结构于该封装层的第一表面上，且该线路结构电性连接该导电体及/或该半导体元件。
24.如权利要求23所述的半导体封装件的制法，其特征为，该线路结构包含至少一线路重布层。
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