CN109216309A - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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Publication number
CN109216309A
CN109216309A CN201810182944.3A CN201810182944A CN109216309A CN 109216309 A CN109216309 A CN 109216309A CN 201810182944 A CN201810182944 A CN 201810182944A CN 109216309 A CN109216309 A CN 109216309A
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layer
conductive
conducting element
semiconductor device
device packages
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CN109216309B (zh
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方仁广
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
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Abstract

本公开揭示一种半导体封装装置，其包含载体、第一电子组件，及在所述载体上的导电元件。所述第一电子组件在所述载体上方。所述导电元件在所述载体上且将所述第一电子组件电连接到所述载体。所述导电元件包含至少一个导电颗粒及覆盖所述导电颗粒的焊料材料，且所述导电颗粒包含金属芯、覆盖所述金属芯的阻挡层，以及覆盖所述阻挡层的金属层。

Description

半导体封装装置及其制造方法
技术领域
本公开大体来说涉及半导体封装装置及其制造方法。更特定来说，本公开涉及包含导电柱的半导体封装装置及其制造方法。
背景技术
导电柱广泛用于裸片与衬底之间或衬底与另一衬底之间的互连。在类似技术中，导电柱通常通过电镀形成。然而，电镀技术增加用于制造导电柱的成本及时间。
发明内容
在一或多个实施例中，导电颗粒包含金属芯、阻挡层、第一导电层及第二导电层。所述阻挡层环绕所述金属芯。所述第一导电层环绕所述阻挡层。所述第二导电层环绕所述第一导电层。
在一或多个实施例中，半导体封装装置包含载体、第一电子组件，及在所述载体上的导电元件。所述第一电子组件在所述载体上方。所述导电元件在所述载体上且将所述第一电子组件电连接到所述载体。所述导电元件包含至少一个导电颗粒及覆盖所述导电颗粒的焊料材料，且所述导电颗粒包含金属芯、覆盖所述金属芯的阻挡层，以及覆盖所述阻挡层的金属层。
在一或多个实施例中，半导体装置封装包含载体及导电元件。所述载体具有第一表面且包含在所述载体的所述第一表面上的导电垫。导电元件包含由焊料材料环绕的多个导电颗粒，且所述导电元件安置在所述载体的所述导电垫上，其中所述导电元件的部分被所述导电垫覆盖。
在一或多个实施例中，半导体装置封装包含电子组件、导电元件及第一封装主体。所述导电元件在所述电子组件上，且所述导电元件具有侧表面及在所述侧表面上的多个凹部。所述第一封装主体囊封所述导电元件且延伸到所述凹部中。
在一或多个实施例中，制造半导体封装的方法包含：提供RDL；将绝缘层安置在所述RDL上，所述绝缘层具有开口；及通过将包含至少一个导电颗粒的糊料(paste)填充到所述开口中来安置导电元件，其中所述导电颗粒包含囊封金属芯的焊料层。
附图说明
当与附图一起阅读时可从以下详细描述最佳理解本公开的方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述的清楚起见而任意增大或减小。
图1A说明根据本公开的一些实施例的半导体封装装置的横截面图。
图1B说明根据本公开的一些实施例的如图1A中所展示的导电柱的内部结构；
图1C说明由图1A中的虚线框A围绕的半导体封装装置的部分的放大图；
图1D说明由图1A中的虚线框A围绕的半导体封装装置的部分的放大图；
图2A、图2B、图2C、图2D、图2E、图2F、图2G及图2H为根据本公开的一些实施例的在各种阶段制造的半导体结构的横截面图；
图3A说明根据本公开的一些实施例的图2B中所展示的糊料的成分；
图3B说明根据本公开的一些实施例的如图3A中所展示的导电颗粒的放大图；
图3C说明根据本公开的一些实施例的如图3A中所展示的导电颗粒的放大图；
图3D说明根据本公开的一些实施例的如图3A中所展示的导电颗粒的放大图；
图4A、图4B及图4C说明根据本公开的一些实施例的不同类型的导电柱；
图5说明根据本公开的一些实施例的半导体封装装置的横截面图；
图6说明根据本公开的一些实施例的半导体封装装置的横截面图；
图7A、图7B、图7C、图7D及图7E为根据本公开的一些实施例的在各种阶段制造的半导体结构的横截面图；
图8说明根据本公开的一些实施例的用于计算如图3A及3B中所展示的导电柱与导电颗粒之间的关系的方法；及
图9A及图9B说明根据本公开的一些实施例的不同类型的半导体封装装置。
贯穿图式和详细描述使用共同参考标号指示相同或类似元件。本公开从结合附图进行的以下详细描述将更显而易见。
具体实施方式
图1A说明根据本公开的一些实施例的半导体封装装置1的横截面图。半导体封装装置1包含衬底(或载体)10，重布层(RDL)11，电子组件12a、12b，一或多个导电柱(或导电元件)13及隔离层(或封装主体)14、15。
在一些实施例中，RDL 11包含介电层11d及由介电层11d囊封或覆盖的导电层11m1、11m2(或金属层)。导电层11m1、11m2通过导电互连件11v(例如，通孔)电连接。在一些实施例中，RDL 11可根据数个不同实施例包含任何数目个介电层及导电层。例如，RDL 11可包含N个介电层及导电层，其中N为整数。导电层11m1经从介电层11d 暴露以在RDL 11的第一表面111(还被称作顶部表面)上提供电连接。导电层11m2经从介电层11d暴露以在RDL 11的第二表面112(还被称作底部表面)上提供电连接。
电子组件12a安置在RDL 11的第一表面111上且与导电层11m1电连接。电子组件12a可为包含半导体衬底的裸片或芯片、一或多个集成电路装置及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其组合的无源装置。
电子组件12b安置在RDL 11的第二表面112上且通过电触点或导电触点12b1(例如，焊料球)与导电层11m2电连接。在一些实施例中，电子组件12b通过RDL 11与电子组件12a电连接。电子组件12b可为包含半导体衬底的裸片或芯片、一或多个集成电路装置及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其组合的无源装置。
导电柱13安置在RDL 11的第二表面112上且通过RDL 11与电子组件12a或电子组件12b电连接。在一些实施例中，取决于不同实施例，导电柱13可为球体柱或立方体柱。
隔离层14安置在RDL 11的第二表面112上且覆盖RDL 11的第二表面112的部分、电子组件12b及导电柱13的第一部分。导电柱13的第二部分从隔离层14暴露。在一些实施例中，隔离层14包含例如有机材料(例如，模塑料、双马来酰亚胺三嗪(BT)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、阻焊剂、味之素(Ajinomoto)内置膜(ABF)、聚丙烯(PP) 或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。导电柱13的熔点可能大于导电触点12b1的熔点。
导电柱13的经暴露部分(例如，第二部分)安置在衬底10的表面101(也被称作第一表面或顶部表面)上且电连接到衬底10的表面101上的导电垫10p1上。衬底10可为例如印刷电路板，例如纸基铜箔层压板、复合铜箔层压板或聚合物浸渍玻璃纤维基铜箔层压板。衬底10可包含互连结构，例如RDL或接地元件。衬底10具有与表面101相对的表面102(还被称作第二表面或底部表面)。衬底10的第一表面101上的导电垫10p1 通过衬底10内的导电垫10v电连接到衬底10的第二表面102上的导电垫10p2。电触点 10b(例如，受控塌陷芯片连接(C4)垫)安置在导电垫10p2上以在衬底10与外部装置之间提供电连接。
隔离层15安置在衬底10的第一表面101上且覆盖由电子组件12a、RDL 11与隔离层14以及导电柱13的第二部分界定的基本上共面的侧表面。在一些实施例中，隔离层 15可覆盖RDL 11的第一表面111的部分。在一些实施例中，隔离层15包含例如有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。在一些实施例中，隔离层15 及隔离层14是由相同材料形成。替代地，隔离层15及隔离层14是由不同材料形成。在一些实施例中，第一封装主体14界定多个容纳空间以容纳相应导电元件13，且容纳空间中的每一个的轮廓由相应导电元件13界定。
图1B说明根据本公开的一些实施例的如图1A中所展示的导电柱13的内部结构；如在图1B中所展示，导电柱13由多个导电颗粒13b及覆盖导电颗粒13b的导电层或矩阵13b4形成。
导电颗粒13b包含金属芯13b1、阻挡层13b2及导电层13b3。金属芯13b1可提供用于导电柱13的支撑结构。在一些实施例中，金属芯13b1可包含例如铜(Cu)、银(Ag)、金(Au)、铂(Pt)或其它金属或合金。阻挡层13b2安置在金属芯13b1上以环绕金属芯13b1。在一些实施例中，金属芯13b1可包含例如镍(Ni)、钛(Ti)、钨(W)或其它金属或合金。导电层13b3安置在阻挡层上13b2以环绕阻挡层13b2。在一些实施例中，导电层13b3为焊料层，包含例如Cu、Ag、Au、Pt或具有低熔点的其它金属或合金。
导电层13b4环绕导电层13b3。在一些实施例中，导电层13b4包含例如锡(Sn)、Ag或具有低熔点的其它金属或合金。在一些实施例中，阻挡层13b2或导电层13b3的熔点大于导电层13b4的熔点。
在一些实施例中，可从导电颗粒13b省略阻挡层13b2。在此状况下，金属间化合物(IMC)可形成在金属芯13b1与导电层13b3之间(例如，金属芯13b1与导电层13b3之间的边界)，此可能导致导电柱13的破裂或缺乏。另外，在无阻挡层13b2的情况下，金属芯13b1与导电层13b3之间的边界可能为粗糙的，此可能影响导电柱13的导电率。如在本公开的图1B中所展示，通过将阻挡层13b2放置在金属芯13b1与导电层13b3之间，边界的IMC问题及粗糙性可被克服，此将增加导电柱13的导电率及坚固性。
图1C说明由图1A中的虚线框A围绕的半导体封装装置1的部分的放大图。如图 1C中所展示，将导电柱13安置在衬底10的第一表面101上的导电垫10p1上。所有导电颗粒13b在衬底10的第一表面101上的导电垫10p1上方。
图1D说明由图1A中的虚线框A围绕的半导体封装装置1的部分的放大图。如图 1D中所展示，导电柱13的部分安置在衬底10的第一表面101上的导电垫10p1上且导电柱13的另一部分延伸到导电垫10p1。例如，导电颗粒13b的部分延伸到衬底10的第一表面101上的导电垫10p1中。例如，导电颗粒13b的部分在衬底10的第一表面101 上的导电垫10p1的表面10p11下方。
图2A、2B、2C、2D、2E、2F、2G及2H为根据本公开的一些实施例的在各种阶段处制作的半导体结构的横截面视图。各种图已经简化以更佳地理解本公开的方面。
参考图2A，提供电子组件22a(例如，裸片或芯片)。电子组件22a具有有源表面22a1。 RDL 21形成在电子组件22a的有源表面22a1上。在一些实施例中，RDL 21包含介电层21d及由介电层21d囊封或覆盖的导电层21m1、21m2(或金属层)。导电层21m1、21m2 通过导电互连件21v(例如，通孔)电连接。在一些实施例中，导电层21m1、21m2是通过热喷涂技术(借以将熔融(或经加热)材料喷涂到表面上)形成或安置。在一些实施例中， RDL 21可根据数个不同实施例包含任何数目个介电层及导电层。例如，RDL 21可包含 N个介电层及导电层，其中N为整数。导电层21m1经从介电层21d暴露以在RDL 21 的第一表面211上提供电连接。导电层21m2经从介电层21d暴露以在RDL 21的第二表面212上提供电连接。
参考图2B，将光致抗蚀剂29或掩模或其它绝缘层安置在RDL 21上。光致抗蚀剂 29具有或界定多个开口29h以暴露RDL 21的导电层21m2的至少部分。在一些实施例中，光致抗蚀剂29可通过涂布、层压或其它合适的过程来形成。
参考图2C，将糊料23'填充在由光致抗蚀剂29界定的开口29h内。在一些实施例中，可通过刮削、印刷或其它合适的过程来将糊料23'填充在开口29h内。在一些实施例中，在将糊料23'填充到开口29h中，将格网放置在光致抗蚀剂29上。格网具有对应于光致抗蚀剂29的开口29h的多个开口。以此方式，可对格网(而非对光致抗蚀剂29)实施印刷过程以防止糊料23'的溶剂残留在光致抗蚀剂29上。
参考图2D，在将糊料23'填充在开口29h内，实施回流过程以形成导电柱23。在回流过程之后，溶剂可能蒸发，且部分熔剂可能残留。在一些实施例中，可在回流过程之后将残留熔剂移除。在一些实施例中，导电柱23的成分类似于如图1B中所展示的导电柱13的成分。每一导电颗粒23b的导电层23b4经熔融且组合在一起以覆盖包含金属芯 23b1、阻挡层23b2及第一导电层23b3(参见图3A及图3B)的导电颗粒23b的剩余部分。
参考图2E，将光致抗蚀剂29移除且将电子组件22b放置在RDL 21的第二表面212上。电子组件22b可通过倒装芯片或导线接合技术电连接到RDL 21。
参考图2F，将干膜28放置或安置在导电柱23上以覆盖导电柱23的部分。隔离层 24形成或安置在RDL 21的第二表面212上以覆盖RDL 21的第二表面212的部分、电子组件22b及未被干膜28覆盖的导电柱23的第一部分。在一些实施例中，隔离层24 包含例如有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。隔离层24 可通过成型技术(例如传递成型或压缩成型)形成。
参考图2G，将干膜28从导电柱23移除以暴露导电柱23的部分。将导电柱23放置在衬底20上。导电柱23的经暴露部分与衬底20的导电垫20p1电连接。
参考图2H，隔离层25形成或安置在衬底20上以覆盖由电子组件22a、RDL 21与隔离层24以及导电柱23的经暴露部分界定的基本上共面的侧表面。在一些实施例中，隔离层25包含例如有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。在一些实施例中，隔离层25及隔离层24是由相同材料形成。替代地，隔离层25及隔离层24是由不同材料形成。电触点20b(例如，C4垫)形成或安置在导电垫20p2上以在衬底10与外部装置之间提供电连接。在一些实施例中，图2A到2H中所说明的方法可被称作“后芯片”过程。
图3A说明根据本公开的一些实施例的图2B中所展示的糊料23'的成分。如图3A 中所展示，糊料23'包含多个导电颗粒23b及包含溶剂及熔剂的混合物23a。混合物23a 覆盖或囊封导电颗粒23b。在一些实施例中，混合物23a不包含焊料。
图3B说明根据本公开的一些实施例的如图3A中所展示的导电颗粒23b的放大图。导电颗粒23b包含金属芯23b1、阻挡层23b2、第一导电层23b3及第二导电层23b4。
在一些实施例中，金属芯23b1可包含例如Cu、Ag、Au、Pt或其它金属或合金。阻挡层23b2安置在金属芯23b1以环绕金属芯23b1。在一些实施例中，阻挡层23b2可包含例如Ni、Ti、W或其它金属或合金。第一导电层23b3(例如，下伏层)安置在阻挡层13b2以环绕阻挡层13b2。在一些实施例中，第一导电层23b3为焊料层，包含例如 Cu、Ag、Au、Pt或具有低熔点的其它金属或合金。第二导电层23b4安置在第一导电层 23b3上以环绕第一导电层23b3。在一些实施例中，第二导电层23b4包含例如Sn、Ag 或具有低熔点的其它金属或合金。在一些实施例中，阻挡层23b2或第一导电层23b3的熔点大于第二导电层23b4的熔点。在一些实施例中，导电颗粒23b为球体、立方体(例如，图3C中所展示的导电颗粒23b')或不规则形状(例如，图3D中所展示的导电颗粒 23b”)。
如上文所提及，阻挡层23b2可避免IMC形成在金属芯23b1与第一导电层23b3的边界处。在一些实施例中，第二导电层23b4(例如，焊料层)可通过电镀直接形成或安置在阻挡层23b2上。然而，由于阻挡层23b2与焊料层之间的电势差，阻挡层23b2与焊料层可能并非彼此直接附接。因此，使用电镀技术来在阻挡层23b2上形成焊料层可能增加制造成本。根据一些实施例，将薄金属层(例如，第一导电层23b3)溅射在阻挡层23b2 上以促进焊料层(例如，第二导电层23b4)的形成，且未使用电镀过程，此可能减少制造成本及时间。在一些实施例中，薄金属层(例如，第一导电层23b3)可通过电镀技术形成；然而，形成薄金属层的时间比在无薄金属层的互连结构中形成相对厚焊料层的时间少得多。
图4A、4B及4C说明根据本公开的一些实施例的不同类型的导电柱。图4A、4B 及4C中所展示的导电柱可应用于图1A中所展示的半导体封装装置1。
如图4A中所展示，所有导电颗粒13b被导电层13b4(例如，焊料层)囊封或覆盖。如图4B中所展示，导电颗粒13b的部分从导电层13b4(例如，焊料层)暴露。如在图4C 中所展示，导电柱包含沿垂直方向堆叠的多个导电柱13'、13”，且隔离层包含沿垂直方向堆叠的多个隔离层14'、14”。在一些实施例中，导电柱13'的导电颗粒13b'大于导电柱 13”的导电颗粒13b”(或以其它方式具有不同于其的平均大小)。
图5说明根据本公开的一些实施例的半导体封装装置5的横截面图。半导体封装装置5类似于图1中所展示的半导体封装装置1，除了半导体封装装置5的导电通孔50v 包含与导电柱13相同或相似结构。例如，导电通孔50v包含如图1B中所展示的多个导电颗粒及导电层。另外，导电柱(或导电元件)53的侧壁并非平面的。在一些实施例中，在回流过程之后，导电柱53的导电颗粒中的每一个的焊料层(例如，图1B中所展示的导电层13b4)可连接在一起。由于焊料的表面张力，导电柱53的侧壁并不平坦。如在图 5中所展示，导电柱53的侧壁包含许多凹部(或凹陷)53s。在模塑料(例如，隔离层14) 经形成或安置以覆盖导电柱53时，凹部53s将被模塑料填充，以便增加导电柱53与模塑料之间的粘结强度，此可防止导电柱53从导电垫10p1剥落。
图6说明根据本公开的一些实施例的半导体封装装置6的横截面图。半导体封装装置6包含RDL 61、电子组件62、导电柱63及隔离层64。
在一些实施例中，RDL 61包含介电层61d及由介电层61d囊封或覆盖的导电层61m1、61m2(或金属层)。导电层61m1、61m2通过导电互连件61v(例如，通孔)电连接。在一些实施例中，RDL 61可根据数个不同实施例包含任何数目个介电层及导电层。例如，RDL 61可包含N个介电层及导电层，其中N为整数。导电层61m1经从介电层61d 暴露以在RDL 61的第一表面61d1(还被称作顶部表面)上提供电连接。在一些实施例中，导电层61m1并非平面的。例如，导电层61m1可包含凹部。导电层61m2经从介电层61d暴露以在RDL 61的第二表面61d2(还被称作底部表面)上提供电连接。电触点60b(例如，焊料球)电连接到导电层61m2的经暴露部分。
导电柱63安置在导电层61m1的凹部内且电连接到导电层61m1。在一些实施例中，取决于不同实施例，导电柱63可为球体柱或立方体柱。在一些实施例中，导电柱63与导电柱13、导电柱53或任何其它合适导电柱相同或相似。
电子组件62安置在导电柱63上。电子组件62通过导电柱63电连接到RDL 61。电子组件62可为例如包含半导体衬底的裸片或芯片、一或多个集成电路装置及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置及/或例如电阻器、电容器、电感器或其组合的无源装置。
隔离层64安置在RDL 61的第一表面61d1上且覆盖RDL 61的第一表面61d1的部分、导电柱63及电子组件62的有源表面与侧表面。在一些实施例中，隔离层64包含例如有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。
图7A、7B、7C、7D、7E为根据本公开的一些实施例的在各种阶段处制作的半导体结构的横截面视图。各种图已经简化以更佳地理解本公开的方面。
参考图7A，提供电子组件72(例如，裸片或芯片)。光致抗蚀剂79形成或安置在电子组件72的有源表面上。光致抗蚀剂79包含多个开口79o以暴露电子组件72的导电垫72p。在一些实施例中，光致抗蚀剂79可通过涂布、层压或其它合适的过程来形成。
参考图7B，将糊料73'填充在由光致抗蚀剂79界定的开口79o内。在一些实施例中，可通过刮削、印刷或其它合适的过程来将糊料73'填充在开口79o内。在一些实施例中，在将糊料73'填充到开口79o中，将格网放置在光致抗蚀剂79上。格网具有对应于光致抗蚀剂的开口79o的多个开口。以此方式，可对格网(而非对光致抗蚀剂79)实施印刷过程以防止糊料73'的溶剂残留在光致抗蚀剂79上。在一些实施例中，糊料73'与图2C中所展示的糊料23'相同或相似。
参考图7C，实施回流过程以形成导电柱73。在一些实施例中，导电柱73可从光致抗蚀剂79的顶部表面突出。在回流过程之后，溶剂可能蒸发，且部分熔剂可能残留。在一些实施例中，可在回流过程之后将残留熔剂移除。在一些实施例中，导电柱73的成分类似于如图1B中所展示的导电柱13的成分。
参考图7D，将光致抗蚀剂79移除且将干膜78放置在导电柱73上以覆盖导电柱73的部分。隔离层74形成或安置在电子组件72的有源表面上以覆盖电子组件72的有源表面与侧表面以及未被干膜78覆盖的导电柱73的部分。在一些实施例中，隔离层74 包含例如有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或环氧基材料)，无机材料(例如，硅、玻璃、陶瓷或石英)，液体及/或干膜材料，或其组合。隔离层74 可通过成型技术(例如传递成型或压缩成型)形成或安置。
参考图7E，将干膜78从导电柱73移除以暴露导电柱73的部分。RDL 71形成或安置在隔离层74上且电连接到导电柱73的经暴露部分。在一些实施例中，RDL 71包含介电层71d及由介电层71d囊封或覆盖的导电层71m1、71m2(或金属层)。导电层71m1、 71m2通过导电互连件71v(例如，通孔)电连接。在一些实施例中，导电层71m1、71m2 是通过热喷涂技术(借以将熔融(或经加热)材料喷涂到表面上)形成或安置。在一些实施例中，RDL 71可根据数个不同实施例包含任何数目个介电层及导电层。例如，RDL 71可包含N个介电层及导电层，其中N为整数。导电层71m2从介电层71d暴露。接着将电子触点70b安置在导电层71m2的经暴露部分上以形成如图6中所展示的半导体封装装置6。在一些实施例中，图7A到7E中所说明的方法可被称作“先芯片”过程。
图8说明根据本公开的一些实施例的用于计算如图3A及3B中所展示的导电柱23与导电颗粒23b之间的关系的方法。如图8中所展示，导电柱23的顶部表面的半径由R 表示，导电柱60的高度由H表示，金属芯23b1的中心与第一导电层23b3的外表面之间的距离由为r表示且第一导电层23b3的外表面与第二导电层23b4之间的距离由t表示。
导电柱23的体积Vp为：
Vp＝πR2×H 方程式(1)
一个导电颗粒23b的体积Vs为：
Vs＝4π(r+t)3/3 方程式(2)
为将所有n个导电颗粒23b限制在导电柱23内，应满足以下条件：
n×4π(r+t)3/3≤πR2×H 方程式(3)
在计算之后，导电柱23与导电柱23b之间的关系可如下导出：
及1≤n≤(3HR2)/(4r3) 方程式(4)
假定约5微米(μm)≤R≤约50μm，约0.05μm≤r≤约5μm，约0.04μm≤t≤约10μm，t对r的比率(例如，t/r)是从约0.04到约110.0且金属芯23b1、阻挡层23b2 及第一导电层23b3的体积的和对第二导电层23b4的体积的比率为从约0.1到约200。在一些实施例中，1≤(3H(R×kf)2)/(4r3)，其中约0.2<kf≤约1.2且约5μm≤R×kf≤约50μm，约0.05μm≤r≤约5μm。
图9A及9B说明根据本公开的一些实施例的不同类型的半导体封装装置。
如在图9A中所展示，将多个芯片90或裸片安置在正方形载体91上。在一些实施例中，载体91可包含有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)或无机材料(例如，硅、玻璃、陶瓷或石英)。
如在图9B中所展示，将多个芯片90或裸片安置在圆形载体92上。在一些实施例中，载体92可包含有机材料(例如，模塑料、BT、PI、PBO、阻焊剂、ABF、PP或基于环氧树脂的材料)或无机材料(例如，硅、玻璃、陶瓷或石英)。
如本文中所使用，术语“大约”、“基本上”、“基本”、及“约”被用于描述及考虑小变化。在结合事件或情形使用时，所述术语可是指其中确切地发生事件或情形的例子以及其中近似地发生事件或情形的例子。举例来说，当结合数值使用时，所述术语可是指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么所述值可被认为“基本上”或“约”相同。举例来说，“基本上”平行可能是指小于或等于±10°的相对于0°的角度变化范围，诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可能是指小于或等于±10°的相对于90°的角度变化范围，诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm，不大于2μm，不大于1μm，或不大于0.5μm，那么两个表面可被认为共面或基本上共面。
如本文中所使用，术语“导电”、“导电”及“导电率”是指传输电流的能力。导电材料通常指示展现对电流流动的极少或零对抗的那些材料。导电性的一个度量为西门子 /米(S/m)。通常，导电材料为具有大于大约104S/m的导电率的材料，例如至少105S/m 或至少106S/m。材料的导电率有时可随温度变化。除非另有一规定，否则材料的导电性是在室温下进行测量。
如本文中所使用，除非上下文另有明确指示，否则单数术语“一(a)”、“一(an)”和“所述”可包含复数对象。在一些实施例的描述中，提供在另一组件的“上”或“上方”的组件可囊括其中后一组件直接在前一组件上(例如，物理接触)的状况，以及其中一或多个介入组件可位于前一组件与后一组件之间的状况。
虽然已参考本公开的特定实施例描述并说明本公开，但这些描述及说明并不限制本公开。所属领域的技术人员可清楚地理解，在不背离如随附权利要求书所界定的本公开的真实精神及范围的情况下，可做出各种改变且可在实施例内替代等效组件。说明可不必按比例绘制。由于制造过程中的变量等等，因此本公开中的精巧呈现与实际设备之间可存在差异。可存在本公开的未具体说明的其它实施例。说明书及图式应视为说明性而非限制性。可进行修改以使特定情况、材料、物质组合物、方法或过程适应本公开的目的、精神及范围。所有此些修改意欲属于随附的权利要求书的范围内。虽然已参考以特定次序执行的特定操作来描述本文中所揭示的方法，但可理解，可在不背离本公开的教示的情况下将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中特别指明，否则操作的次序及分组并非本公开的限制。

Claims (31)

1.一种导电颗粒，其包括：
金属芯；
阻挡层，其环绕所述金属芯；
第一导电层，其环绕所述阻挡层；以及
第二导电层，其环绕所述第一导电层。
2.根据权利要求1所述的导电颗粒，其中所述第二导电层的厚度(t)对所述金属芯的中心与所述第一导电层的外表面之间的距离(r1)的比率为从约0.04到约110。
3.根据权利要求2所述的导电颗粒，其中约0.05微米(μm)≤r1≤约5μm且约0.04μm≤t≤约10μm。
4.根据权利要求1所述的导电颗粒，其中所述金属芯、所述阻挡层及所述第一导电层的体积的和对所述第二导电层的体积的比率为从约0.1到约200。
5.根据权利要求1所述的导电颗粒，其中所述金属芯包括铜(Cu)、银(Ag)、金(Au)、铂(Pt)或其中的两个或多于两个的组合。
6.根据权利要求1所述的导电颗粒，其中所述阻挡层包括镍(Ni)、钛(Ti)、钨(W)或其中的两个或多于两个的组合。
7.根据权利要求1所述的导电颗粒，其中所述第一导电层包括Cu、Ag、Au、Pt，或其中的两个或多于两个的组合。
8.根据权利要求1所述的导电颗粒，其中所述第二导电层包括锡(Sn)、Ag，或其组合。
9.一种半导体装置封装，其包括：
载体；
第一电子组件，其在所述载体上方；及
导电元件，其在所述载体上且将所述第一电子组件电连接到所述载体，其中所述导电元件包括至少一个导电颗粒及覆盖所述导电颗粒的焊料材料，且所述导电颗粒包括金属芯、覆盖所述金属芯的阻挡层，以及覆盖所述阻挡层的金属层。
10.根据权利要求9所述的半导体装置封装，其中所述载体包括穿过所述载体的导电通孔，且所述导电通孔包括至少一个导电颗粒及覆盖所述导电颗粒的焊料材料。
11.根据权利要求9所述的半导体装置封装，其进一步包括重布层RDL，所述重布层RDL具有所述第一电子组件安置在其上的第一表面及与所述第一表面相对的第二表面，其中所述导电元件电连接到所述RDL的所述第二表面。
12.根据权利要求11所述的半导体装置封装，其进一步包括第二电子组件，所述第二电子组件安置在所述RDL的所述第二表面上，其中所述第二电子组件包括将所述第二电子组件电连接到所述RDL的电触点。
13.根据权利要求12所述的半导体装置封装，其中所述导电元件的熔点大于所述第二电子组件的所述电触点的熔点。
14.根据权利要求12所述的半导体装置封装，其进一步包括覆盖所述导电元件及所述第二电子组件的第一封装主体。
15.根据权利要求14所述的半导体装置封装，其进一步包括覆盖所述第一封装主体及所述第一电子组件的第二封装主体。
16.一种半导体装置封装，其包括：
载体，其具有第一表面且在所述载体的所述第一表面上包括导电垫；及
导电元件，其包括由焊料材料环绕的多个导电颗粒，所述导电元件安置在所述载体的所述导电垫上，其中所述导电元件的部分被所述导电垫覆盖。
17.根据权利要求16所述的半导体装置封装，其中所述导电颗粒中的每一个包括金属芯、覆盖所述金属芯的阻挡层及覆盖所述阻挡层的金属层。
18.根据权利要求17所述的半导体装置封装，其中由所述导电垫覆盖的所述导电元件的所述部分包括所述导电颗粒。
19.根据权利要求18所述的半导体装置封装，其中由所述导电垫覆盖的所述导电元件的所述部分包括所述焊料材料。
20.根据权利要求16所述的半导体装置封装，其中：
所述导电元件具有厚度(H)及半径(R)；
所述导电颗粒中的每一个具有半径(r)；且
1≤(3H(R×kf)2)/(4r3)，其中约0.2<kf≤约1.2。
21.根据权利要求20所述的半导体装置封装，其中约5微米(μm)≤R×kf≤约50μm，约0.05μm≤r≤约5μm。
22.一种半导体装置封装，其包括：
电子组件；
导电元件，其在所述电子组件上，所述导电元件具有侧表面及在所述侧表面上的多个凹部；及
第一封装主体，其囊封所述导电元件且延伸到所述凹部中。
23.根据权利要求22所述的半导体装置封装，其中所述导电元件进一步包含至少一个金属颗粒及囊封所述金属颗粒的焊料材料，所述金属颗粒包含金属芯、在所述金属芯上的阻挡层以及在所述阻挡层上的下伏层。
24.根据权利要求22所述的半导体装置封装，其进一步包括电路层，所述电路层具有垫及在所述垫上的凹部，其中所述导电元件将所述电子组件连接到所述电路层的所述垫。
25.根据权利要求24所述的半导体装置封装，其中所述至少一个金属颗粒安置在所述凹部中。
26.根据权利要求22所述的半导体装置封装，其进一步包括：
电路层，其具有垫及在所述垫上的凹部；及
第二封装主体，其囊封所述电路层、所述电子组件及所述导电元件，
其中所述导电元件将所述电子组件连接到所述电路层的所述垫。
27.根据权利要求26所述的半导体装置封装，其中所述至少一个金属颗粒安置在所述凹部中。
28.根据权利要求22所述的半导体装置封装，其中所述第一封装主体界定容纳空间以容纳所述导电元件，且所述容纳空间的轮廓是由所述导电元件界定。
29.一种制造半导体装置封装的方法，其包括：
提供RDL；
将绝缘层安置在所述RDL上，所述绝缘层具有开口；及
通过将包含至少一个导电颗粒的糊料填充到所述开口中来安置导电元件，其中所述导电颗粒包含囊封金属芯的焊料层。
30.根据权利要求29所述的方法，其中所述导电颗粒在所述金属芯与所述焊料层之间进一步包括阻挡层及金属层，其中所述阻挡层覆盖所述金属芯，所述金属层覆盖所述阻挡层且所述焊料层覆盖所述金属层。
31.根据权利要求29所述的方法，其进一步包括：
将所述绝缘层移除；
提供隔离层以囊封所述导电元件且暴露所述导电元件的部分；及
将所述导电元件的所述经暴露部分连接到载体的导电垫。
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