CN101887874B - 单层金属层基板结构及其制造方法、和应用之封装件结构 - Google Patents

单层金属层基板结构及其制造方法、和应用之封装件结构 Download PDF

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CN101887874B
CN101887874B CN2009101592867A CN200910159286A CN101887874B CN 101887874 B CN101887874 B CN 101887874B CN 2009101592867 A CN2009101592867 A CN 2009101592867A CN 200910159286 A CN200910159286 A CN 200910159286A CN 101887874 B CN101887874 B CN 101887874B
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layer
substrate
patterned metal
substrate material
metal layer
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CN101887874A (zh
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黄士辅
苏洹漳
陈嘉成
陈光雄
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种单层金属层的基板结构，应用于一封装件，基板结构包括一基底材、数个通孔、一图案化金属层、一图案化介电层和一第一表面处理层(Surface finish layer)。其中图案化金属层配置于基底材的上表面上方，且至少部份图案化金属层覆盖于通孔上，以形成下方对外电性连接的数个第一接点。图案化介电层形成于图案化金属层上方，且图案化介电层至少暴露出部分图案化金属层，以形成上方对外电性连接的数个第二接点。第一表面处理层则至少覆盖于该些第二接点的任一或多者的表面及侧壁。而封装件结构则是包括至少一晶粒(die)与上述基板的该些第二接点电性连接，和形成于基底材上表面处的胶体(Molding Compound)，胶体并覆盖图案化金属层、图案化介电层和晶粒。

Description

单层金属层基板结构及其制造方法、和应用之封装件结构
技术领域
本发明是有关于一种基板结构、应用之封装件结构及其制造方法，且特别是有关于一种具有单层金属层基板及其制造方法、和应用之封装件结构。
背景技术
集成电路(IC)构装技术是电子产业中重要的一环，电子构装主要的功用在于保护、支撑、线路配置与制造出散热途径，并提供零件一个模块化与规格标准。在1990年代主要是利用球栅数组(Ball Grid Array，BGA)的封装方式进行电子构装，其优点为散热性佳与电性好、接脚数可以大量增加，可有效缩小封装体面积。
然而，随着全球个人计算机、消费性电子产品及通讯产品不断要求轻薄短小更要具备高效能的趋势下，芯片所要求的电气特性不但要愈好，整体体积要愈小，但I/O端口的数目却是往上提高。随着I/O数量增加、集成化线路间距缩小，要想在BGA基板上高效率地布置走线变得困难，例如在点18工艺(线宽0.18μm)或是高速(如800MHz以上)的IC设计上，有大幅增加I/O密度的趋势。因此开发出具有高I/O、细微的线路间距、和优良电性的载板一直是各载板厂争相努力的目标。除了这些需求，下游产品系统整合化的要求将日趋明显，因此多芯片模块(Multi-chipModule，MCM)工艺对MCM载板的需求也大幅提高。而快速增加的微电子系统需求(特别是关于系统大小和芯片整合增益部分)也更加速了芯片级尺寸封装(ChipScale Packaging，CSP)技术的采用。
随着芯片级尺寸封装(CSP)技术的成熟，追求性能与成本的系统型半导体封装方式-系统封装(System in Package，SiP)也成为封装技术的主流，主要是因为产品的尺寸越来越小、功能越趋繁多，必须应用SiP技术以满足市场的需求。系统封装SiP包括了将芯片(chip)或是被动组件(Passive Components)或是其它模块进行构装。系统封装也包括了不同技术如PiP(Package in Package)、PoP(Package on Package)、平面型的多芯片模块封装、或是为节省面积将不同功能芯片堆栈(Stack)起来的3D堆栈封装，这些都属于系统封装(SiP)技术的发展范畴，该用何种型态封装也视应用需求而有所差异。因此SiP的定义十分广泛。在系统封装(SiP)技术中，所使用的接合技术也有很多种，例如是打线连接(Wire bonding)、覆晶式(Flip Chip)接合和使用多种接合技术(Hybrid-type)等等。
以系统封装(System in Package)裸晶为例，它可将不同数字或模拟功能的裸晶，以凸块(bump)或打线(wire bond)方式连结于芯片载板上，该载板中已有部分内埋被动组件或线路设计，此具有电性功能的载板，称为整合性基板(Integrated Substrate)或功能性基板(Functional Substrate)。请参照图1A～1F，其绘示一种传统整合性基板的工艺示意图。首先，提供一铜箔基板(copper clad laminate，CCL)，是在一中心层(core)102的上下表面各形成第一导电层103和第二导电层104，导电层的材料例如是金属铜，如图1A所示。接着，对铜箔基板进行钻孔，形成孔洞106，接着整体镀上铜层107，其铜层107是形成于第一导电层103和第二导电层104上方，和孔洞内壁，如图1B、1C所示。之后，对于中心层102上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形。如图1D所示，在中心层102上下两侧的金属铜层上分别形成(ex：曝光显影)图案化干膜108，再如图1E所示对金属铜层进行蚀刻，最后如图1F所示去除图案化干膜108，完成导线(metal traces)的制作。之后可以再进行后续工艺，例如印制上防焊绿漆(solder mask，SM)并对绿漆曝光/显影而暴露出所需的导线表面，再对导线表面进行处理如镀上镍/金(Ni/Au)，而完成最后产品。
另外，也有更高阶的整合性基板在工艺中是将通孔部份直接镀满导电材料(如金属铜)，再对于中心层上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形，如图2所示，其为另一种传统整合性基板的示意图。然而，将通孔镀满的技术较为复杂，也需较长时间镀制，且金属铜层115、116、117厚度控制不易(特别是金属铜层117的部份)。又图1F和图2所示的基板结构主要是有2层导电铜层分别形成于中心层102/112的上下两侧，因此又习称为”2层基板”。
当电子产品的体积日趋缩小，所采用的基板结构的体积和线路间距也必须随的减小。然而，在目前现有的基板结构和工艺技术能力下，不论是如图1F或图2所示的基板态样，要使基板再薄化和线路间距再缩小的可能性很小，不利于应用在小型尺寸的电子产品上。再者，对于定位在较低市场价格的小型电子产品，除了尺寸和性能，其基板的制造成本也是必须考虑的重要因素的一。因此，如何开发出新颖的薄型整合性基板，不但工艺快速简单又适合量产，并可兼具低制造成本和高产品良率的优点，以符合应用电子产品对于尺寸、外型轻薄化和价格的需求，实为相关业者努力的一大重要目标。
发明内容
本发明是有关于一种单层金属层基板及其制造方法、和应用之封装件结构。其基板制作主要是在一基底材的上表面处形成单层的图案化金属层，再于图案化金属层上方形成一图案化介电层，其特殊结构设计与制造方法使得所形成的基板结构整体厚度降低，且工艺简单快速，适合量产，亦可降低制造成本但保有高产品良率，符合市场产品轻薄化和低成本的需求。
根据本发明，提出一种单层金属层基板结构，其结构包括一基底材、贯穿基底材的上表面与下表面的数个通孔、一图案化金属层、一图案化介电层和一第一表面处理层(Surface finish layer)。其中图案化金属层配置于基底材的上表面上方，且至少部份图案化金属层覆盖于通孔上，以形成下方对外电性连接的数个第一接点。图案化介电层配置于图案化金属层上方，且图案化介电层至少暴露出部分图案化金属层，以形成上方对外电性连接的数个第二接点。第一表面处理层则至少覆盖于该些第二接点的任一或多者的表面及侧壁。
根据本发明，提出上述单层金属层基板的制造方法，包括：形成一基底材；形成贯穿基底材的上表面与下表面的数个通孔；形成一图案化金属层于基底材的上表面；形成一图案化介电层于图案化金属层上方；和形成一第一表面处理层，至少覆盖于该些第二接点任一或多者的表面及侧壁。其中，至少部份图案化金属层覆盖于通孔上，以形成下方对外电性连接的数个第一接点。而图案化介电层至少暴露出部分图案化金属层，以形成上方对外电性连接的数个第二接点。
根据本发明，提出一种封装件结构，包括：上述的基板结构；至少一晶粒(die)与基板的该些第二接点电性连接；和一胶体，形成于基底材的上表面上方，并覆盖图案化金属层、图案化介电层和晶粒。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1A～1F绘示一种传统整合性基板的工艺示意图。
图2为另一种传统整合性基板的示意图。
图3A～3F绘示本发明第一实施例的单层金属层基板的制造方法。
图4是绘示应用本发明第一实施例的图3F基板的封装件示意图。
图5A绘示依照本发明第一实施例所制作的另一种单层金属层基板的示意图。
图5B是绘示应用本发明第一实施例的图5A基板的封装件示意图。
图6A，其绘示依照本发明第一实施例所制作的再一种单层金属层基板的示意图。
图6B是绘示应用本发明第一实施例的图6A基板的封装件示意图。
图7A～7H，其绘示本发明第二实施例的单层金属层基板的制造方法。
图8是绘示应用本发明第二实施例的图7H基板的封装件示意图。
图9A，其绘示依照本发明第二实施例所制作的另一种单层金属层基板的示意图。
图9B是绘示应用本发明第二实施例的图9A基板的封装件示意图。
图10A，其绘示依照本发明第二实施例所制作的再一种单层金属层基板的示意图。
图10B是绘示应用本发明第二实施例的图10A基板的封装件示意图。
图11A～11I，其绘示本发明第三实施例的单层金属层基板的制造方法。
图12，其绘示依照本发明第三实施例所制作的另一种单层金属层基板的示意图。
图13，其绘示依照本发明第三实施例所制作的再一种单层金属层基板的示意图。
主要组件符号说明
102：中心层
103：第一导电层
104：第二导电层
106：孔洞
107、115、116、117：铜层
108：图案化干膜
202、202’、302、302’：芯板
203、203’：黏着层
205a、205b、205c、205d、205e、305a、305b、305c、305d、305e、405a、405b、405c、405d、405e：通孔
207、303、403：金属层
207’、303’、403’：图案化金属层
2071、3031、4031：芯片垫(die pads)
2073、2074、3033、3034、4033、4034：焊垫(bonding pads)
2075、2076、3035、3036、4035、4036：锡球垫(ball pads)
209、209a、209b、209c、308、308a、308b、308c、408、408a、408b、408c：图案化介电层
210a、210b、310a、310b、410a、410b：第一表面处理层
210c、310c、410c：第二表面处理层
213、313、413：黏性物质
215、315：晶粒
217、218、317、318：焊线
219、319：胶体
306、406：干膜
306’、406’：图案化干膜
40、50：载板
402、402’：基底材
61、62、63、64、65、66、67、68、69：基板结构
71、72、73、74、75、76、77、78、79：封装件结构
具体实施方式
本发明是提出一种单层金属层基板、应用的封装件结构、基板的制造方法和封装件的制造方法，主要是在一基底材的上表面处形成单层的图案化金属层，其中基底材的下表面具有数个通孔，而图案化金属层例如是包括了多个焊垫(bonding pads)和多个锡球垫(ball pads)，且基底材的通孔与图案化金属层的锡球垫位置相对应，在图案化金属层上方更形成一图案化介电层(patterned dielectric layer)，且介电层的图案部分或完全遮蔽住与锡球垫对应的基底材的该些通孔。其中至少部份图案化金属层覆盖于通孔上以形成下方对外电性连接的数个第一接点(即锡球垫)，而图案化介电层至少暴露出部分图案化金属层，以形成上方对外电性连接的数个第二接点(即焊垫)。
相较于传统的”2层基板”结构，本发明所提出的基板结构及应用此基板的封装件其整体厚度大为降低，轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出此基板结构及应用其的封装件的制造方法，不但工艺快速简单又适合量产，亦可兼具低制造成本和高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。特别是对于市场价格较低的小型电子产品，更是具有市场竞争力。
以下根据本发明提出多个实施例，以详细说明本发明的基板结构及应用封装件的制造方法。然而，实施例中所提出的基板结构仅为举例说明之用，并非作为限缩本发明保护范围之用。应用时可依实际条件的需求对基板的结构样式稍作修改。再者，实施例的图标仅绘示本发明技术的相关组件，省略不必要的组件，以清楚显示本发明的技术特点。
第一实施例
请参照图3A～3F，其绘示本发明第一实施例的单层金属层基板的制造方法。首先，提供一铜箔基板(copper clad laminate，CCL)，其结构例如是包括一芯板(Core)202和芯板202上下表面各贴附一铜箔(未显示)所组成，其中芯板202的材料例如是玻璃纤维和树脂所组成，制作时使玻璃纤维浸泡于树脂液中，形成的芯板202是有如经纬线交错的玻璃纤维与树脂含浸混和而成。树脂材料例如是二氟化铵树脂(Ammonium Bifluoride，ABF)、双马来酰亚胺树脂(Bismaleimide，BT)、玻璃布基有环氧树脂(FR4、FR5)、聚亚醯胺树脂(polyimide，PI)、液晶聚合树脂(LCP)、或环氧树脂(Epoxy)等。也可直接选用具单面铜箔的树脂作为芯板202。但本发明对此并不多作限制。之后，去除芯板202下上表面的两铜箔，并贴附一黏着层(adhesivelayer)203于芯板202的上表面，如第3A图所示。
接着，对芯板202和黏着层203进行钻孔并贯穿芯板202和黏着层203，以形成多个通孔205a、205b，如图3B所示。其中，可采用机械式钻孔方式，以降低制造成本；然而本发明并不仅限于此，其它可形成通孔205a、205b的方式亦视实际应用状况而采用。
然后，形成一金属层207于黏着层203’的上表面，并对金属层207进行图像转移，例如蚀刻，以形成一图案化金属层207’，如图3C、3D所示。在此实施例中，图案化金属层207’包括数个焊垫(bonding pads)2073、芯片垫(die pads)2071和锡球垫(ball pads)2075，其中锡球垫2075的位置对应于通孔205a、205b。再者，图案化金属层207’更可包括至少一无信号的金属导线(Dummy trace)(未显示)，以防止基板翘曲(Warpage)。
接着，形成一图案化介电层(patterned dielectric layer)209于图案化金属层207’的上方，且至少位于锡球垫2075上方的介电层209会遮蔽住与锡球垫2075对应的通孔205a、205b，如图3E所示。其中，图案化介电层209例如是包括至少一槽状开口(Slot opening)，以暴露出该些焊垫2073。图案化介电层209的材料例如是防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)等等，但本发明并不以此为限。
换句话说，自芯板202的上表面侧往下俯视，图案化介电层209会覆盖住与锡球垫2075对应的通孔205a、205b。
之后，可对芯片垫2071、焊垫2073和锡球垫2075任一者、多者或全部的表面处，如裸露于图案化介电层209外的部分，进行后续表面处理而完成基板结构61的制造；如图3F所示，形成第一表面处理层210a、210b和第二表面处理层210c，其中，第一表面处理层210a、210b分别覆盖芯片垫2071和焊垫2073的表面及侧壁处，而第二表面处理层210c则覆盖至少一或多个锡球垫2075的表面。其中第一、二表面处理层210a、210b、210c的材料例如是包括镍/金、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、OSP等，本发明对此并不多作限制。
图4是绘示应用本发明第一实施例的图3F基板的封装件示意图。如图4的封装件结构71所示，制作时是应用一黏性物质(例如环氧树脂)213将一晶粒215黏附在芯片垫2071上方，并且经由焊线217电性连接晶粒215的一主动表面与焊垫2073；之后，再形成一胶体(Molding Compound)219于芯板202的上方，以密封图案化金属层207’、图案化介电层209、晶粒215和焊线217。胶体219的材料一般为绝缘的封装材料，常见的例如是环氧树脂。另外，图4中，位于晶粒215下方的芯板202部分为整面的连续板，其芯板202的通孔205a、205b对应于晶粒215设置位置的区域范围外。再者，通孔205a、205b亦可填充一导体材料(未显示)使导体材料与锡球垫2075电性连接。
因此，对于图3F和图4的基板结构而言，其配置于黏着层203’上方的图案化金属层，至少部份图案化金属层207’覆盖于通孔205a、205b上，以形成下方对外电性连接的数个第一接点，即锡球垫2075。而位于图案化金属层207’上方的图案化介电层209至少暴露出部分图案化金属层207’，以形成上方对外电性连接的数个第二接点，即焊垫2073。
除了图3F所示的基板结构61，根据第一实施例的工艺也可稍微变化而制作其它态样的基板。
请参照图5A，其绘示依照本发明第一实施例所制作的另一种单层金属层基板的示意图。和图3F基板不同的是，制作如图5A所示的基板62时，在形成图案化介电层的步骤中，除了使位于锡球垫2075上方的介电层209a遮蔽住与锡球垫2075对应的通孔205a、205b外，也在芯片垫2071上形成介电层209b，以部分覆盖芯片垫2071。之后，再对裸露于图案化介电层209a、209b外的部分进行后续表面处理，如镍/金处理，所形成的第一表面处理层210a、210b部分覆盖芯片垫2071的表面及侧壁处，和焊垫2073的表面及侧壁处，而第二表面处理层210c则覆盖至少一或多个锡球垫2075的表面。和图3F相较，图5A的第一表面处理层210a是部分覆盖芯片垫2071的上表面但完全覆盖芯片垫2071的侧壁，而图3F的芯片垫2071的上表面和侧壁则被第一表面处理层210a完全覆盖，两种态样均为本发明可实施的型态，并没有特别限制。
图5B是绘示应用本发明第一实施例的图5A基板的封装件示意图。如图5B的封装件结构72所示，制作时亦应用一黏性物质(例如环氧树脂)213将晶粒215黏附在介电层209b(对应芯片垫2071处)的上方，并利用焊线217电性连接晶粒215的一主动表面与焊垫2073，利用焊线218电性连接晶粒215与芯片垫2071。之后，再以胶体219密封图案化金属层207’、图案化介电层209a、209b、晶粒215和焊线217、218。另外，图5B中，位于晶粒215下方的芯板202部分亦为整面的连续板，其芯板202的通孔205a、205b对应于晶粒215设置位置的区域范围外。同样的，对于图5A和图5B的基板结构而言，其配置于黏着层203’上方的图案化金属层，至少部份图案化金属层207’覆盖于通孔205a、205b上，以形成下方对外电性连接的数个第一接点，即锡球垫2075。而位于图案化金属层207’上方的图案化介电层209至少暴露出部分图案化金属层207’，以形成上方对外电性连接的数个第二接点，即焊垫2073。
另外，除了图3F和图5A所示的基板结构61、62，也可根据第一实施例的工艺制作出锡球垫位于晶粒设置区域范围内的基板态样。
请参照图6A，其绘示依照本发明第一实施例所制作的再一种单层金属层基板的示意图。和图3F基板不同的是，制作如图6A所示的基板结构63时，在钻孔时是在对应晶粒位置处形成多个通孔205c、205d、205e，而在图案化金属层的步骤中形成多个焊垫2074(bonding pads)和多个对应通孔205c、205d、205e位置的锡球垫2076(ball pads)。在形成图案化介电层后，该些锡球垫2076被图案化介电层209c完全覆盖。之后，亦可对裸露于图案化介电层209a外的部分进行后续表面处理(如镍/金处理)(未显示于图6A中)。另外，图6A中，该些通孔205c、205d、205e位于芯板202下表面的尺寸是大于该些通孔205c、205d、205e位于芯板202上表面的尺寸。
图6B是绘示应用本发明第一实施例的图6A基板的封装件示意图。如图6B的封装件结构73所示，制作时亦应用一黏性物质(例如环氧树脂)213将晶粒215黏附在图案化介电层209c的上方，并利用焊线217电性连接晶粒215的一主动表面与焊垫2074。之后，再以胶体219密封图案化金属层207’、图案化介电层209a和209c、晶粒215和焊线217。而此种封装件结构73可透过位于晶粒215正下方的锡球垫2076，使晶粒215与一外部组件(如电路板)作电性连接。同样的，对于图6A和图6B的基板结构而言，位于黏着层203’上方的图案化金属层207’，至少部份覆盖于通孔205c、205d、205e上，以形成下方对外电性连接的数个第一接点，即锡球垫2076。而位于图案化金属层207’上方的图案化介电层209a至少暴露出部分图案化金属层207’，以形成上方对外电性连接的数个第二接点，即焊垫2074。
虽然，如图6B所示的封装件结构73看似与图4和图5B所示的结构较为不同，但是位于晶粒215下方的该些锡球垫2076的位置也同样会被图案化介电层209c完全覆盖。因此，自芯板202的上表面侧往下俯视，图案化介电层209同样会覆盖住与锡球垫2076对应的通孔205c、205d、205e。
在第一实施例中应用黏着层203/203’进行基板制作，因此如图3F、5A、6A所示，芯板202’和黏着层203’构成基板结构61～63的一基底材。而相较于传统的基板结构，依照本发明所制作的基板结构仅具单层金属层以作为导线层，其基板结构厚度约40μm～130μm，使整体厚度大为降低，如此轻薄的外型十分适合小尺寸应用产品的需求。另外，相较于传统工艺，第一实施例所提出的工艺更为简易迅速，并可制作出细微的线路间距。
值得注意的是，虽然在第一实施例中已提出三种略微不同的基板结构61～63和相关封装件71～73作举例说明，但其最终结构仍是依照实际应用条件而作相关调整，例如封装时晶粒连接可采用打线或覆晶方式连接，芯板上通孔的数目和位置、介电层图案、金属层图案、...等等，该些选择并不局限于上述图式所绘制的态样。
第二实施例
在第一实施例中以黏着层黏附芯板进行基板制作的说明，然而本发明并不以此为限。在第二实施例中是经由一载板进行本发明的基板制作。
请参照图7A～7H，其绘示本发明第二实施例的单层金属层基板的制造方法。首先，提供一芯板(Core)302，并形成一金属层303于芯板302的上表面，如图7A所示。芯板302同样可以透过移除一铜箔基板(CCL)上下表面所贴附的铜箔至少其中之一而获得。其中，芯板302作为第二实施例的基板结构的一基底材。
接着，例如是以钻孔方式在芯板302处形成多个通孔305a、305b，再将芯板302’的下表面设置于一载板(carrier)40上，如图7B所示。其中，可采用机械式钻孔方式，以降低制造成本；然而本发明并不仅限于此，其它可形成通孔305a、305b的方式亦视实际应用状况而采用。
然后，进行金属层303图案化的步骤。如图7C所示，形成一干膜(dry film)306于金属层303上，再透过曝光显影以形成图案化干膜306’，如图7D所示。之后根据图案化干膜306’对金属层303进行影像转移例如蚀刻，以形成一图案化金属层303’，最后移除图案化干膜306’，如图7E所示。在此结构中，图案化金属层303’包括数个焊垫(bonding pads)3033、芯片垫(die pads)3031和锡球垫(ball pads)3035，其中锡球垫3035的位置对应于通孔305a、305b。另外，图案化金属层303’同样可更包括至少一无信号的金属导线(未显示)，以防止基板翘曲。
接着，形成一图案化介电层(patterned dielectric layer)308于图案化金属层303’的上方，且至少位于锡球垫3035上方的介电层308会遮蔽住与锡球垫3035对应的通孔305a、305b，如图7F所示。其中，图案化介电层308例如是包括至少一槽状开口(Slot opening)，以暴露出该些焊垫3033。图案化介电层308的材料例如是防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)等等，但本发明并不以此为限。
同样的，自芯板302的上方往下俯视，图案化介电层308会覆盖住与锡球垫3035对应的通孔305a、305b。
之后，可对芯片垫3031、焊垫3033和锡球垫3035任一者、多者或全部的表面处，如裸露于图案化介电层308外的部分，进行后续表面处理，而完成基板结构64的制造；如图7G所示。形成第一表面处理层310a、310b和第二表面处理层310c，其中，第一表面处理层310a、310b分别覆盖芯片垫3031和焊垫3033的表面及侧壁处(且芯片垫3031的表面及侧壁被第一表面处理层310a完全覆盖)，而第二表面处理层310c则覆盖至少一或多个锡球垫3035的表面。其中第一、二表面处理层310a、310b、310c的材料包括镍/金、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、OSP等，本发明对此并不多作限制。
最后，移除载板40，而完成如图7H所示的基板结构64的制造。
图8绘示应用本发明第二实施例的图7H基板的封装件示意图。如图8的封装件结构74所示，制作时亦应用一黏性物质(例如环氧树脂)313将一晶粒315黏附在芯片垫3031上方，并且经由焊线317电性连接晶粒315的一主动表面与焊垫3073；之后，再形成一胶体(Molding Compound)319于芯板302’的上方，以密封图案化金属层303’、图案化介电层308、晶粒315和焊线317。胶体219的材料例如是环氧树脂或其它绝缘材料。另外，图8中，位于晶粒315下方的芯板302部分为整面的连续板，其芯板302的通孔305a、305b对应于晶粒315设置位置的区域范围外。再者，通孔305a、305b亦可填充一导体材料(未显示)使导体材料与锡球垫3035电性连接。
因此，对于图7H和图8的基板结构而言，至少部份图案化金属层303’覆盖于通孔305a、305b上，以形成下方对外电性连接的数个第一接点，即锡球垫3035。而位于图案化金属层303’上方的图案化介电层308至少暴露出部分图案化金属层303’，以形成上方对外电性连接的数个第二接点，即焊垫3033。
同样的，除了图7H所示的基板结构64，根据第二实施例的工艺也可稍微变化而制作其它态样的基板结构。
请参照图9A，其绘示依照本发明第二实施例所制作的另一种单层金属层基板的示意图。和图7H基板不同的是，制作如图9A所示的基板65时，在形成图案化介电层的步骤中，除了使位于锡球垫3035上方的介电层308a遮蔽住与锡球垫3035对应的通孔305a、305b外，也在芯片垫3031上形成介电层308b，以部分覆盖芯片垫3031。之后，可再对裸露于图案化介电层308a、308b外的部分进行后续处理，如镍/金处理，所形成的第一表面处理层310a、310b部分覆盖芯片垫3031和焊垫3033的表面及侧壁处，而第二表面处理层310c则覆盖至少一或多个锡球垫3035的表面。
图9B绘示应用本发明第二实施例的图9A基板的封装件示意图。如图9B的封装件结构75所示，制作时亦应用一黏性物质(例如环氧树脂)313将晶粒315黏附在介电层308b(对应芯片垫3031处)的上方，并利用焊线317电性连接晶粒315与焊垫3033，利用焊线318电性连接晶粒315的一主动表面与芯片垫3031。之后，再以胶体319密封图案化金属层303’、图案化介电层308a、308b、晶粒315和焊线317、318。另外，图9B中，位于晶粒315下方的芯板302部分亦为整面的连续板，其芯板302的通孔305a、305b对应于晶粒315设置位置的区域范围外。同样的，对于图9A和图9B的基板结构而言，至少部份图案化金属层303’覆盖于通孔305a、305b上，以形成下方对外电性连接的数个第一接点，即锡球垫3035。而位于图案化金属层303’上方的图案化介电层308至少暴露出部分图案化金属层303’，以形成上方对外电性连接的数个第二接点，即焊垫3033。
另外，除了图7H和图9A所示的基板结构64、65，也可根据第二实施例的工艺制作出锡球垫位于晶粒设置区域范围内的基板态样。
请参照图10A，其绘示依照本发明第二实施例所制作的再一种单层金属层基板的示意图。和图7H基板64不同的是，制作如图10A所示的基板结构66时，在钻孔时在对应晶粒位置处形成多个通孔305c、305d、305e，而在图案化金属层的步骤中形成多个焊垫3034(bonding pads)和多个与通孔305c、305d、305e位置对应的锡球垫3036(ball pads)。在形成图案化介电层后，该些锡球垫3036被图案化介电层308c完全覆盖。之后，亦可对裸露于图案化介电层308a外的部分进行后续处理(如镍/金处理)(未显示于图10A中)。
图10B绘示应用本发明第二实施例的图10A基板的封装件示意图。如图10B的封装件结构76所示，制作时亦应用一黏性物质(例如环氧树脂)313将晶粒315黏附在图案化介电层308c的上方，并利用焊线317电性连接晶粒315的一主动表面与焊垫3034。之后，再以胶体319密封图案化金属层303’、图案化介电层308a和308c、晶粒315和焊线317。而此种封装件结构76可透过位于晶粒315正下方的锡球垫3036，使晶粒315与一外部组件(如一电路板，未显示)作电性连接。同样的，对于图10A和图10B的基板结构而言，至少部份图案化金属层303’覆盖于通孔305c、305d、305e上，以形成下方对外电性连接的数个第一接点，即锡球垫3036。而位于图案化金属层303’上方的图案化介电层308a至少暴露出部分图案化金属层303’，以形成上方对外电性连接的数个第二接点，即焊垫3034。
虽然，如图10B所示的封装件结构76看似与图8和图9B所示的结构较为不同，但是位于晶粒315下方的该些锡球垫3036的位置也同样会被图案化介电层308c完全覆盖。因此，自芯板302的上表面侧往下俯视，图案化介电层308同样会覆盖住与锡球垫3036对应的通孔305c、305d、305e。
与第一实施例制法不同的是，第二实施例是经由一载板40进行基板制作，因此根据第二实施例所制成的基板结构64、65、66并无黏着层203’(第3H、5A、6A图)的存在。另外，虽然在第一、二实施例以铜箔基板(CCL)的中心层作为芯板302的举例说明，但本发明并不以此为限，也可选用其它材质作为实施例基板结构的基底材，而对基底材图案化(ex形成通孔)的方式亦可因基底材料的不同作适当选择。
第三实施例
在第三实施例中同样运用一载板进行本发明的基板制作。但第三实施例与第二实施例的步骤略有不同。
请参照第11A～11I图，其绘示本发明第三实施例的单层金属层基板的制造方法。首先，提供一基底材402，并将基底材402设置于一载板50上，如图11A所示。在此实施例中，以一ABF膜材为例作说明，但本发明并不以此为限。之后，于基底材402的上表面形成一金属层403，例如一铜层，如图11B所示。
然后，进行金属层403图案化的步骤。如图11C所示，形成一干膜(dry film)406于金属层403上，再透过曝光显影以形成图案化干膜406’，如图11D所示。之后根据图案化干膜406’对金属层403进行影像转移例如蚀刻，以形成一图案化金属层403’，之后移除图案化干膜406’，如图11E所示。在此结构中，图案化金属层403’包括数个焊垫(bonding pads)4033和芯片垫(die pads)4031。同样，制作图案化金属层403’时亦可包括形成至少一无信号的金属导线(未显示)，以防止基板翘曲。
之后，移除载板50，如图11F所示。
接着，如第11G图所示，在基底材402处形成多个通孔405a、405b，且通孔位置暴露出图案化金属层403’的部分下表面，以形成多个锡球垫(ball pads)4035。形成通孔405a、405b的方式没有特殊限制，而是视实际应用状况而定。若以ABF膜材作基底材402时，可利用激光钻孔方式形成该些通孔405a、405b。
然后，形成一图案化介电层(patterned dielectric layer)408于图案化金属层403’的上方，且至少位于锡球垫4035上方的介电层408会遮蔽住与锡球垫4035对应的通孔405a、405b，如图11H所示。其中，图案化介电层408例如是包括至少一槽状开口(Slot opening)，以暴露出该些焊垫4033。图案化介电层408的材料例如是防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)等等，但本发明并不以此为限。
同样的，自基底材402的上方往下俯视，图案化介电层408会覆盖住与锡球垫4035对应的通孔405a、405b。
之后，可对芯片垫4031、焊垫4033和锡球垫4035任一者、多者或全部的表面处，如裸露于图案化介电层408外的部分，进行后续处理，而完成基板结构67的制造；如图11I所示，可形成第一表面处理层410a、410b和第二表面处理层410c，其中，第一表面处理层410a、410b分别覆盖芯片垫4031和焊垫4033的表面及侧壁处(且芯片垫4031的表面及侧壁均被第一表面处理层410a完全覆盖)，而第二表面处理层410c则覆盖至少一或多个锡球垫4035的表面。其中第一、二表面处理层410a、410b、410c的材料包括镍/金、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、OSP等，本发明对此并不多作限制。
图11I所制成的基板结构67与图7H的基板结构64相同。而应用本发明第三实施例的图11I基板的封装件，其结构亦请参照图8，在此不再赘述。
同样的，除了图11I所示的基板结构67，根据第三实施例的工艺也制作出其它态样的基板结构。
请参照图12，其绘示依照本发明第三实施例所制作的另一种单层金属层基板的示意图。其制成的基板结构68和图9A所示的基板结构65相同。其中，在形成图案化介电层的步骤中，除了使位于锡球垫4035上方的介电层408a部分或完全遮蔽住与锡球垫4035对应的通孔405a、405b外，也在芯片垫4031上形成介电层408b，以部分覆盖芯片垫4031。之后，可再对裸露于图案化介电层408a、408b外的部分进行后续处理(如镍/金处理)，其制成的基板结构68请参照图9A，在此不再赘述。而应用本发明第三实施例的图12基板所制成的封装件，将晶粒315黏附在介电层408b(对应芯片垫4031处)的上方，其封装件结构亦同第二实施例的图9B，在此不再赘述。
另外，除了图11I和图12所示的基板结构67、68，同样也可根据第三实施例的工艺制作出锡球垫位于晶粒设置区域范围内的基板态样。
请参照图13，其绘示依照本发明第三实施例所制作的再一种单层金属层基板的示意图。在基底材402处形成多个通孔405c、405d、405e，在图案化金属层的步骤中形成多个焊垫4034(bonding pads)和锡球垫4036(ball pads)，且通孔405c、405d、405e与锡球垫4036的位置一一对应。在形成图案化介电层后，该些锡球垫4036被图案化介电层408c完全覆盖。之后，亦可对裸露于图案化介电层408a外的部分进行后续处理(如镍/金处理)(未显示于图13中)。其制成的基板结构69是和图10A所示的基板结构66相同，而应用本发明第三实施例的图13基板所制成的封装件，其结构亦同第二实施例的图10B，在此均不再赘述。
综上，第二、三实施例所提出的制法都是在工艺中使用载板，先将芯板302/基底材402的下表面先设置于载板上，再形成一图案化金属层于芯板302/基底材的上表面。但第二、三实施例制法不同的是，第二实施例先形成多个通孔于芯板302的下表面处，然后将芯板302设置于载板40上，再形成图案化金属层于芯板302的上表面。第三实施例则是先形成图案化金属层于基底材402的上表面，再形成多个通孔于基底材402的下表面处。两种方式都可制作出实施例所揭露的结构。
综上所述，根据本发明实施例所制作出的基板结构，其厚度范围可减薄至约40μm～130μm的范围，相较于传统的”2层基板”结构，本发明所提出的基板厚度、及应用此基板的封装件的整体厚度都可大为下降，其轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出此基板结构及应用其的封装件的制造方法，其工艺不但快速简单又十分适合量产，兼具低制造成本和高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。因此，比起传统的基板结构，本发明所提出的基板结构及应用其的封装件更是适合应用于市场价格较低的小型电子产品，十分具有市场竞争力。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视后附的权利要求书所界定者为准。

Claims (22)

1.一种单层金属层基板，其结构包括：
一基底材，具有一上表面和一下表面；
数个通孔，且该些通孔贯穿该基底材的该上表面与该基底材的该下表面；
一图案化金属层(patterned metal layer)，配置于该基底材的该上表面，其中至少部份该图案化金属层覆盖于该些通孔上以形成下方对外电性连接的数个第一接点；
一图案化介电层(patterned dielectric layer)，配置于该图案化金属层上方，其中该图案化介电层至少暴露出部分该图案化金属层以形成上方对外电性连接的数个第二接点；以及
一第一表面处理层(Surface finish layer)，至少覆盖于该些第二接点的任一或多者的表面及侧壁。
2.如权利要求1所述的基板，其中该图案化介电层更包括至少一槽状开口(Slotopening)，能够暴露出该些第二接点。
3.如权利要求1所述的基板，其中该些通孔位于该基底材的该下表面的尺寸大于该些通孔位于该基底材的该上表面的尺寸。
4.如权利要求1所述的基板，其中该第一表面处理层的材料包括镍/金、镍/银、金、锡、锡的合金、或银、OSP。
5.如权利要求1所述的基板，其中该基底材的材料包括二氟化铵树脂(Ammonium Bifluoride，ABF)、双马来酰亚胺树脂(Bismaleimide，BT)、液晶聚合树脂(LCP)、环氧树脂(Epoxy)、或具单面铜箔层的树脂。
6.权利要求1所述的基板，其中该图案化介电层的材料为防焊绿漆(soldermask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)。
7.如权利要求1所述的基板，其结构更包括一黏着层配置于该基底材的该上表面，该些通孔贯穿该基底材与该黏着层，且该图案化金属层配置于该黏着层的上方。
8.如权利要求1所述的基板，其厚度范围在40μm～130μm之间。
9.一种单层金属层基板的制造方法，包括：
形成一基底材，具有一上表面和一下表面；
形成数个通孔，且该些通孔贯穿该基底材的该上表面与该基底材的该下表面；
形成一图案化金属层(patterned metal layer)于该基底材的该上表面，其中至少部份该图案化金属层覆盖于该些通孔上，以形成下方对外电性连接的数个第一接点；
形成一图案化介电层(patterned dielectric layer)于该图案化金属层上方，其中该图案化介电层至少暴露出部分该图案化金属层，以形成上方对外电性连接的数个第二接点；和
形成一第一表面处理层(Surface finish layer)，至少覆盖于该些第二接点任一或多者的表面及侧壁。
10.如权利要求9所述基板的制造方法，其中形成该基底材的步骤中，包括：
提供一铜箔基板(copper clad laminate，CCL)，由一芯板(Core)和下上表面各贴附一铜箔而成；和
移除该芯板下上表面的两该铜箔。
11.如权利要求9所述基板的制造方法，其中形成该些通孔于该基底材的该上表面与下表面之间后，更包括步骤：
将该基底材的该下表面设置于一载板(carrier)上；以及
于上述形成该图案化金属层于该基底材的该上表面及形成该图案化介电层于该图案化金属层上方之后，再移除该载板。
12.如权利要求9所述基板的制造方法，其中在形成一基底材之后与形成该些通孔于该基底材之前，其步骤更包括：
将该基底材的该下表面设置于一载板(carrier)上；以及
并于形成该图案化金属层于该基底材的该上表面之后，移除该载板。
13.如权利要求9所述基板的制造方法，其中该图案化介电层更包括形成至少一槽状开口(Slot opening)，以暴露出该些第二接点。
14.如权利要求9所述基板的制造方法，更包括：
形成一黏着层于该基底材的该上表面，且该些通孔贯穿该基底材与该黏着层，其中该图案化金属层则形成于该黏着层的上方。
15.一种具有单层金属层基板的封装件结构，包括：
一单层金属层基板，其中该基板包含一基底材、数个通孔、一图案化金属层(patterned metal layer)、一图案化介电层(patterned dielectric layer)和一第一表面处理层(Surface finish layer)，该些通孔贯穿该基底材，该图案化金属层配置于该基底材的一上表面，且至少部份该图案化金属层覆盖于该些通孔上以形成下方对外电性连接的数个第一接点，该图案化介电层配置于该图案化金属层上方，且该图案化介电层至少暴露出部分该图案化金属层以形成上方对外电性连接的数个第二接点，而该第一表面处理层至少覆盖于该些第二接点的任一或多者的表面及侧壁；
至少一晶粒(die)与该些第二接点电性连接；以及
一胶体(Molding compound)，配置于该基底材的该上表面上方，并覆盖该图案化金属层、该图案化介电层和该晶粒。
16.如权利要求15所述的封装件结构，其中该图案化介电层更包括至少一槽状开口(Slot opening)，能够暴露出该些第二接点。
17.如权利要求15所述的封装件结构，其基板结构更包括一黏着层配置于该基底材的该上表面，该些通孔贯穿该基底材与该黏着层，且该图案化金属层配置于该黏着层的上方。
18.如权利要求15所述的封装件结构，其中该晶粒设置于该图案化介电层的上方，该些第一接点的位置对应于该晶粒的下方且被该图案化介电层部分或完全覆盖。
19.如权利要求15所述的封装件结构，其中该胶体的侧面与该基底材的侧面为一共平面。
20.如权利要求15所述的封装件结构，其中该第一表面处理层的材料包括镍/金、镍/银、金、锡、锡的合金、或银、OSP。
21.如权利要求15所述的封装件结构，其中该基底材包括二氟化铵树脂(Ammonium Bifluoride，ABF)、双马来酰亚胺树脂(Bismaleimide，BT)、液晶聚合树脂(LCP)、环氧树脂(Epoxy)、或具单面铜箔层的树脂。
22.如权利要求15所述的封装件结构，其中该图案化介电层的材料包括防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)。
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