TW201041105A - Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package - Google Patents

Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package Download PDF

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Publication number
TW201041105A
TW201041105A TW098124118A TW98124118A TW201041105A TW 201041105 A TW201041105 A TW 201041105A TW 098124118 A TW098124118 A TW 098124118A TW 98124118 A TW98124118 A TW 98124118A TW 201041105 A TW201041105 A TW 201041105A
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Taiwan
Prior art keywords
substrate
metal layer
patterned
layer
dielectric layer
Prior art date
Application number
TW098124118A
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English (en)
Inventor
Shih-Fu Huang
Yuan-Chang Su
Chia-Cheng Chen
Kuang-Hsiung Chen
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Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to US12/779,818 priority Critical patent/US8288869B2/en
Publication of TW201041105A publication Critical patent/TW201041105A/zh

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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Description

201041105 ‘ 1 wj->z/r/\ 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種基板結構、應用之封裝件結構及 其製造方法,且特別是有關於一種具有單層金屬層基板、 應用之封裳件結構、基板之製造方法和封裝件之製造方 法0 【先前技術】 積體電路(1C)構裝技術是電子產業中重要的一環,電 子構裝主要的功用在於保護、支撐、線路配置與製造出散 熱途徑’並提供零件一個模組化與規格標準。在丨990年代 主要是利用球柵陣列(Ball Grid Array,BGA)的封裝方式進 行電子構裝,其優點為散熱性佳與電性好、接腳數可以大 量增加,可有效縮小封裝體面積。 然而,隨著全球個人電腦、消費性電子產品及通訊產 品不斷要求輕薄短小更要具備高效能的趨勢下,晶片所要 求的電氣特性不但要愈好’整體體積要愈小,但I/O埠的 數目卻是往上提高。隨著I/O數量增加、積體化線路間距 縮小,要想在BGA基板上高效率地佈置走線變得困難, 例如在點18制程(線寬0.18μιη)或是高速(如8〇〇MHz以上) 的1C設計上,有大幅增加I/O密度的趨勢。因此開發出具 有高I/O、細微的線路間距、和優良電性的載板一直是各 載板廠爭相努力的目標。除了這些需求,下游產品系統整 合化的要求將日趨明顯,因此多晶片模組(Multi-chip 201041105
Module ’ MCM)製程對MCM載板的需求也大幅提高。而 快速增加的微電子系統需求(特別是關於系統大小和晶片 整合增益部分)也更加速了晶片級尺寸封裝(chip Scale Packaging ’ CSP)技術的採用。 隨著晶片級尺寸封裝(CSP)技術的成熟,追求性能與 成本的系統型半導體封裝方式-系統封裝(System比 Package,SiP)也成為封裝技術的主流,主要是因為產品的 尺寸越來越小、功能越趨繁多,必須應用Sip技術以滿足 〇 市場的需求。系統封裝SiP包括了將晶片(Chip)或是被動元 件(Passive Components)或是其他模組進行構裝。系統封裝 也包括了不同技術如PiP(package jn package)、
PoP(Package on Package)、平面型的多晶片模組封裝、或 是為節省面積將不同功能晶片堆疊(Stack)起來的3D堆疊 封裝,這些都屬於系統封裝^斤)技術的發展範疇,該用何 種型態封裝也視應用需求而有所差異。因此Sip的定義十 分廣泛。在系統封裝(SiP)技術令,所使用的接合技術也有 Ο很多種,例如是打線連接(Wire bonding)、覆晶式(Flip Chip) 接合和使用多種接合技術(Hybrid_type)等等。 以系統封裝(System in Package)裸晶為例,它可將不 Π數位或類比功此的裸晶,以凸塊(bump)或打線(评丨代b〇ncj) 方式連結於晶片載板上,該載板中已有部分内埋被動元件 或線路設計,此具有電性功能的載板,稱為整合性基板 (Integrated Substrate)或功能性基板(Functi〇nal
SubStrate)。請參照第1A〜IF圖,其繪示一種傳統整合性 基板之製程不意圖。首先,提供一銅箔基板沉dad 5 201041105
I W3WA laminate,CCL),係在一中心層(core) 102的上下表面各形 成第一導電層103和第二導電層1〇4,導電層的材料例如 是金屬銅,如第1A圖所示。接著,對銅箔基板進行鑽孔, 形成孔洞106,接著整體鍍上銅層107,其銅層107係形 成於第一導電層103和第二導電層104上方,和孔洞内 壁,如第IB、1C圖所示。之後,對於中心層102上下兩 側的金屬銅層進行圖案化,以形成整合性基板所需之線路 圖形。如第1D圖所示,在中心層1〇2上下兩侧的金屬銅 層上分別形成(ex:曝光顯影)圖案化乾膜1〇8,再如第1E圖 所示對金屬銅層進行蝕刻,最後如第1F圖所示去除圖案 化乾膜108,完成導線(metal traces)之製作。之後可以再進 行後續製程’例如印製上防銲綠漆(s〇lder mask,SM)並對 綠漆曝光/顯影而暴露出所需之導線表面,再對導線表面進 行處理如鍍上鎳/金(Ni/Au),而完成最後產品。 另外,也有更高階的整合性基板在製程中是將通 份直接鍍滿導電材料(如金屬銅),再對於中心層上 的金屬銅層進行圖案化,以形成整合性基板所需之線路= 形’如第2圖所示,其為另—種傳統整合性基板 圖 ==技:^,也需較長時心: 117 _。又第1F圖和第2圖所不示易之 有2層導電銅層分別形成於中心層则112的:下兩^ 因此又習稱為”2層基板”。 幻上下兩側, 當電子產品的體積曰趨縮小,所採 積和線路間距也必嶋之減 :=構的體 …、而在目刖現有的基板 201041105 1 yy 結構和製程技術能力下,不論是如第IF圖或第2圖所示 之基板態樣,要使基板再薄化和線路間距再縮小的可能性 很小,不利於應用在小型尺寸的電子產品上。再者,對於 定位在較低市場價格的小裂電子產品,除了尺寸和性能, 其基板的製造成本也是必須考慮的重要因素之一。因此, 如何開發出新穎的薄型整合性基板,不但製程快速簡單又 適合量產’並可兼具低製造成本和高產品良率的優點,以 符合應用電子產品對於尺彳、外型輕薄化和價格之需求, 〇 實為相關業者努力的一大重要目標。 【發明内容】
本發明係有關於一種單層金屬層基板、應用之封裝件 結構、基板之製造方法和封裝件之製造方法。其基板製作 主要是在一基底材之上表面處形成單層之圖案化金屬 層,再於圖案化金屬層上方形成一圖案化介電層,其特殊 結構設計與製造方法使得所形成之基板結構整體厚度降 低,且製程簡單快速,適合量產,亦可降低製造成本但保 有高產品良率,符合市場產品輕薄化和低成本之需求。 根據本發明第一方面,係提出一種單層金屬層基板結 構,其詰構包括一基底材、一黏著層、複數個通一^ 案化金屬層和一圖案化介電層。其中黏著層配置於基底材 的上表面,且該些通孔貫穿基底材與黏著層。圖案^金 層係配置於該黏著層之上方,且至少部份圖案化金屬層 蓋於通孔上’以形成下方對外電性連接的複數個覆 點。圖案化介電層配置於圖案化金屬層上方,Q 接 且圖案化介 201041105 1 = =案化金屬層,以形成上方對外電 根據本&明第二方面,係提出上述第—方面之單層金 屬層基板之製造方法,包括:形成—基底材;形成一黏著 層於基歸的上表面;形成貫穿基储與骑層之複數個 通孔;形成-圖案化金屬層於黏著層之上方;和形成一圖 案化介電層_案化金屬層上方。其中,至少部份圖案化 金^層覆蓋於通孔上’㈣成下謂外電性連接的複數個 第接點。而圖案化介電層係至少暴露出部分圖案化金屬 層’以形成上㈣外電性連接的複數㈣二接點。 根據本發明第二方面,係提出一種封裝件結構,包 括:本發明第—方面所述之基板結構;至少-晶粒(die)與 基板之該些第二接點電性連接;和一膠體 Compound),係形成於基底材之上表面上方, 化金屬層、圖案化介f層和絲。 ^圖案 卜根據本發明第四方面,係提出上述一種封裝件結構之 製ie方法包括.形成本發明第一方面所述之基板結構; 電性連接至少-晶粒與該些第二接點;和形成—膠體於基 底材之上表面上方’並覆蓋圖案化金屬層、圖案化二 和晶粒。 θ 根據本發明第五方面,係提出另一種單層金屬層基板 結構’其結構包括-基底材、貫穿基紐的上表面與下表 面之複數個通孔、一圖案化金屬層、一圖案化介電層和一 第一表面處理層(Surface finish layer)。其中圖案化金屬層 係配置於基底材之上表面上方,且至少部份圖案化金屬^ 覆蓋於通孔上,以形成下方對外電性連接的複數個第一接 點。圖案化介電層配置於圖案化金屬層上方,且圖案化介 電層係至少暴露出部分圖案化金屬層,以形成上方對外電 性連接的複數個第二接點。第一表面處理層則至少覆蓋於 該些第二接點的任一或多者之表面及側壁。 根據本發明第六方面,係提出上述第五方面之單層金 屬層基板之製造方法,包括:形成一基底材;形成貫穿基 底材的上表面與下表面之複數個通孔;形成一圖案化金屬 〇 層於基底材之上表面;形成一圖案化介電層於圖案化金屬 層上方;和形成一第一表面處理層,至少覆蓋於該些第二 接點任一或多者的表面及側壁。其中,至少部份圖案化金 屬層覆蓋於通孔上,以形成下方對外電性連接的複數個第 一接點。而圖案化介電層係至少暴露出部分圖案化金屬 層,以形成上方對外電性連接的複數個第二接點。 根據本發明第七方面,係提出一種封裝件結構,包 括:本發明第五方面所述之基板結構;至少一晶粒(die)與 〇 基板之該些第二接點電性連接;和一膠體,係形成於基底 材之上表面上方,並覆蓋圖案化金屬層、圖案化介電層和 晶粒。 根據本發明第八方面,係提出上述一種封裝件結構之 製造方法,包括:形成本發明第五方面所述之基板結構; 電性連接至少一晶粒與該些第二接點;和形成一膠體於基 底材之上表面上方,並覆蓋圖案化金屬層、圖案化介電層 和晶粒。 201041105
TW5527PA 為讓本發明之上述内容能更明顯易懂,下文特舉較佳 實施例,並配合所附圖式,作詳細說明如下: 【實施方式】 本發明係提出一種單層金屬層基板、應用之封裝件結 構、基板之製造方法和封裝件之製造方法,主要是在一基 底材之上表面處形成單層之圖案化金屬層,其中基底材之 下表面係具有複數個通孔,而圖案化金屬層例如是包括了 多個銲塾(bonding pads)和多個錫球塾(ball pads),且基底 材之通孔係與圖案化金屬層的錫球墊位置相對應,在圖案 化金屬層上方更形成一圖案化介電層(patterned dielectric layer),且介電層的圖案部分或完全遮蔽住與錫球墊對應的 基底材之該些通孔。其中至少部份圖案化金屬層覆蓋於通 孔上以形成下方對外電性連接的複數個第一接點(即錫球 墊)’而圖案化介電層係至少暴露出部分圖案化金屬層,以 形成上方對外電性連接的複數個第二接點(即銲墊)。 社構層基板”結構’本發料提出之基板 :外型m封裝件其整體厚度係大為降低,輕薄 提出此基:;;:=用產:的需求。再者,本發明所 快速簡單又適合量產 ,不但製程 的優點,符合應用電子產成本和高產品良率 格之需求。特別是對於市寸、外型輕薄化和低價 是具有市場競爭力。、豕較低的小型電子產品,更 以下係根據本發明 個實施例,,細說明本發 201041105 明之基板結似應狀封裝件㈣造枝。心,實施例 中所提出之基板結構僅為舉例說明之用,並非作為限縮本 發明保護範圍之用。應用時可依實際條件之需求對基板的 結構樣式猶作修改。再者,實_之圖示僅繪示本發明 技術之«元件’省略不必要之元件’以清楚顯示本發 明之技術特點。 第一實施例 〇 請參照第3A〜3F圖,其纷示本發明第一實施例之單 層金屬層基板之製造方法。首先,提供一銅猪基板(⑶卯打 clad laminate ’ CCL) ’其結構例如是包括一芯板(c〇re)2〇2 和芯板202上下表面各貼附一銅箔(未顯示)所組成,其中 芯板202的材料例如是玻璃纖維和樹脂所組成製作時係 使玻璃纖維浸泡於樹脂液中,形成的芯板202是有如經緯 線父錯的玻璃纖維與樹脂含浸混和而成。樹脂材料例如是 一氟化銨樹脂(Ammonium Bifluoride,ABF)、雙馬來酰亞 C)胺柄'脂(Bismaleimide,BT)、玻璃布基有環氧樹脂(FR4、 FR5)、聚亞醯胺樹脂(p〇iyimide,pi)、液晶聚合樹脂(LCp)、 或環氧樹脂(Epoxy)等。也可直接選用具單面銅箔之樹脂作 為芯板202。但本發明對此並不多作限制。之後,去除芯 板202下上表面之兩銅箔,並貼附一黏著層(adhesive layer)203於芯板202之上表面,如第3A圖所示。 接著,對芯板202和黏著層203進行鑽孔並貫穿芯板 202和黏著層203,以形成多個通孔205a、205b,如第3B 圖所示。其中,可採用機械式鑽孔方式,以降低製造成本; 201041105
1 W3WA 然而本發明並不僅限於此,其他可形成通孔205a、205b 之方式亦視實際應用狀況而採用。 然後’形成一金屬層207於黏著層203,之上表面,並 對金屬層207進行圖像轉移,例如蝕刻,以形成一圖案化 金屬層207’ ’如第3C、3D圖所示。在此實施例中,圖案 化金屬層207’係包括複數個辉墊(bonding pads)2073、晶片 塾(die pads)2071和錫球墊(ball pads)2075,其中錫球墊 2075的位置係對應於通孔2〇5a、2〇5b。再者,圖案化金 屬層207’更可包括至少一無訊號之金屬導線(Dummy trace)(未顯不),以防止基板勉曲(Warpage)。 接著,形成一圖案化介電層(patterned dielectric layer)209於圖案化金屬層207’之上方,且至少位於錫球墊 2075上方的介電層209會遮蔽住與錫球墊2075對應之通 孔205a、205b,如第3E圖所示。其中,圖案化介電層209 例如是包括至少一槽狀開口(Slot opening),以暴露出該些 銲墊2073。圖案化介電層209之材料例如是防得綠漆 (solder mask ’ SM)、液晶聚合物(liquid crystal polyester, LCP)、或聚丙烯(polypropylene ’ PP)等等,但本發明並不 以此為限。 換句話說,自芯板202的上表面側往下俯視,圖案化 介電層209會覆蓋住與錫球墊2075對應之通孔205a、 205b。 之後,可對晶片墊2071、銲墊2073和錫球墊2075 任一者、多者或全部之表面處,如裸露於圖案化介電層209 外之部分’進行後續表面處理而完成基板結構61之製造; 12 201041105 l TT I λ. ΓΎ 如第3F圖所示,形成第一表面處理層210a、210b和第二 表面處理層210c,其中,第一表面處理層210a、210b分 別覆蓋晶片墊2071和銲墊2073的表面及侧壁處,而第二 表面處理層210c則覆蓋至少一或多個錫球墊2075之表 面。其中第一、二表面處理層210a、21 Ob、210c之材料例 如是包括鎳/金、金、錫及其合金(如錫錯合金)、或銀。另 外,也可依實際應用條件,以其他材料進行後處理,例如 ENEPIG、OSP等,本發明對此並不多作限制。 Ο 第4圖係繪示應用本發明第一實施例之第3F圖基板 之封裝件示意圖。如第4圖之封裝件結構71所示,製作 時係應用一黏性物質(例如環氧樹脂)213將一晶粒215黏 附在晶片墊2071上方,並且經由銲線217電性連接晶粒 215之一主動表面與銲墊2073 ;之後,再形成一谬體 (Molding Compound)219於芯板202之上方,以密封圖案 化金屬層207’、圖案化介電層209、晶粒215和銲線217。 膠體219的材料一般為絕緣的封裝材料,常見的例如是環 C) 氧樹脂。另外’第4圖中’位於晶粒215下方的芯板202 部分係為整面的連續板,其芯板202之通孔205a、205b 係對應於晶粒215設置位置之區域範圍外。再者,通孔 205a、205b亦可填充一導體材料(未顯示)使導體材料與錫 球墊2075電性連接。 因此’對於第3F圖和第4圖的基板結構而言,其配 置於黏著層203’上方的圖案化金屬層,至少部份圖案化金 屬層207’覆蓋於通孔205a、205b上,以形成下方對外電 性連接的複數個第一接點,即錫球墊2075。而位於圖案化 13 201041105
iWWZ/PA 金屬層207’上方的圖案化介電層209係至少暴露出部分圖 案化金屬層207’ ’以形成上方對外電性連接的複數個第二 接點,即銲墊2073。 除了第3F圖所示之基板結構61 ’根據第一實施例之 製程也可稍微變化而製作其他態樣之基板。 請參照第5A圖,其繪示依照本發明第一實施例所製 作之另一種單層金屬層基板之示意圖。和第3F圖基板不 同的是,製作如第5A圖所示之基板62時,係在形成圖案 化介電層之步驟中,除了使位於錫球墊2075上方的介電 層209a遮蔽住與錫球墊2075對應之通孔205a 也在晶片墊2071上形成介電層209b,以部分覆蓋晶片墊 2071。之後,再對裸露於圖案化介電層2〇9a、2〇9b外之 部分進行後續表面處理,如鎳/金處理,所形成之第一表面 處理層210a、210b係部分覆蓋晶片墊2〇71的表面及侧壁 處’和銲墊2073的表面及側壁處,而第二表面處理層21如 則覆蓋至少一或多個錫球墊2〇75之表面。和第邛圖 較,第5A圖之第-表面處理層聽係部分覆蓋晶片塾 2071的上表面但完全覆蓋晶片塾2〇71的側壁,而第3 之晶片塾2G71的上表面和側壁則被第—表面處理層 疋全覆盍’兩種錢均為本發明可實施之型態 別限制。 业/又有特 第5Β圖係繪示應用本發明第一實 板之封裝件示意圖。如第沾圖之封裝件結構72所示= 作時亦應用-輯物質(例如環氧_)213將晶粒叫黏 14 附在介電層209b(對應晶片墊2071處)之上方,並利用銲 線217電性連接晶粒215之一主動表面與銲墊2073,利用 銲線218電性連接晶粒215與晶片墊2071。之後,再以膠 體219密封圖案化金屬層207’、圖案化介電層209a、209b、 晶粒215和銲線217、218。另外,第5B圖中,位於晶粒 215下方的芯板202部分亦為整面的連續板,其芯板202 之通孔205a、205b係對應於晶粒215設置位置之區域範 圍外。同樣的,對於第5 A圖和第5B圖的基板結構而言, 〇 其配置於黏著層203’上方的圖案化金屬層,至少部份圖案 化金屬層207’覆蓋於通孔205a、205b上,以形成下方對 外電性連接的複數個第一接點,即錫球墊2075。而位於圖 案化金屬層207’上方的圖案化介電層209係至少暴露出部 分圖案化金屬層207’,以形成上方對外電性連接的複數個 第二接點,即銲墊2073。 另外,除了第3F圖和第5A圖所示之基板結構61、 Ο 62 ’也可根據第一實施例之製程製作出錫球墊位於晶粒設 置區域範圍内之基板態樣。 請參照第6A圖,其繪示依照本發明第一實施例所製 作之再一種單層金屬層基板之示意圖。和第3F圖基板不 同的是,製作如第6A圖所示之基板結構63時,在鑽孔時 係在對應晶粒位置處形成多個通孔205c、205d、205e,而 在圖案化金屬層之步驟中係形成多個銲墊2074(bonding pads)和多個對應通孔205c、205d、205e位置之錫球塾 2076(ball pads)。在形成圖案化介電層後,該些錫球墊2076 15 201041105
1 W;)WA « 係被圖案化介電層209c完全覆蓋。之後,亦可對裸露於 圖案化介電層209a外之部分進行後續表面處理(如鎳/金處 理)(未顯示於第6A圖中)。另外,第6A圖中,該些通孔 205c、205d、205e位於芯板202下表面的尺寸係大於該些 通孔205c、205d、205e位於芯板202上表面的尺寸。 第6B圖係繪示應用本發明第一實施例之第6a圖基 板之封裝件示意圖。如第6B圖之封裝件結構73所示,製 作時亦應用一黏性物質(例如環氧樹脂)213將晶粒215黏 附在圖案化介電層209c之上方,並利用銲線217電性連 〇 接晶粒215之一主動表面與銲墊2074。之後,再以膠體 219密封圖案化金屬層2〇7’、圖案化介電層2〇9&和2〇如、 晶粒215和銲線217。而此種封裝件結構73可透過位於晶 粒215正下方之錫球墊2076,使晶粒215與一外部元件(如 電路板)作電性連接。同樣的,對於第6A圖和第6B圖的 基板結構而言,位於黏著層2〇3,上方的圖案化金屬層 207’ ’至少部份覆蓋於通孔205c、205d、205e上,以形成 下方對外電性連接的複數個第一接點,即錫球墊2076。而 ◎ 位於圖案化金屬層207,上方的圖案化介電層209a係至少 暴露出部分圖案化金屬層2〇7,,以形成上方對外電性連接 的複數個第二接點,即銲墊2〇74。 雖然’如第6B圖所示之封裝件結構73看似與第4 圖和第5B圖所示之結構較為不同,但是位於晶粒215下 方之該些錫球墊2076的位置也同樣會被圖案化介電層 2〇9c完全覆蓋。因此,自芯板202的上表面侧往下俯視, 圖案化介電層2〇9同樣會覆蓋住與錫球墊2076對應之通 16
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Λ ΨΨ t a. Λ X 孔 205c、205d、205e。 在第一實施例中係應用黏著層203/203’進行基板製 作’因此如第3F、5A、6A圖所示,芯板202,和黏著層203, 係構成基板結構61〜63之一基底材。而相較於傳統的基 板結構,依照本發明所製作的基板結構僅具單層金屬層以 作為導線層,其基板結構厚度約40μιη〜130μιη,使整體厚 度係大為降低,如此輕薄的外型十分適合小尺寸應用產品 〇 的需求。另外’相較於傳統製程,第一實施例所提出的製 程更為簡易迅速,並可製作出細微的線路間距。 值得注意的是’雖然在第一實施例中已提出三種略微 不同之基板結構61〜63和相關封裝件71〜73作舉例說 明,但其最終結構仍是依照實際應用條件而作相關調整, 例如封裝時晶粒連接可採用打線或覆晶方式連接,芯板上 通孔的數目和位置、介電層圖案、金屬層圖案、…等等, 該些選擇並不侷限於上述圖式所繪製之態樣。 〇 第二實施你丨 在第一實施例中係以黏著層黏附芯板進行基板製作 之說明,然而本發明並不以此為限。在第二實施例中係藉 由一載板進行本發明之基板製作。 請參照第7Α〜7Η圖,其緣示本發明第二實施例之單 層金屬層基板之製造方法。首先’提供一芯板(c〇re)302, 並形成一金屬層303於芯板302之上表面,如第7A圖所 示。芯板302同樣可以透過移除一銅箔基板(CCL)上下表 17 201041105
1 W”Z/PA 面所貼附的銅箔至少其中之一而獲得。其中,_ ' τ Ά板 302 係 作為第二實施例之基板結構的一基底材。 接著’例如是以鑽孔方式在芯板302處形成多個通孔 305a、305b ’再將芯板302’之下表面設置於一載板 (讓ier)40上,如第7B圖所示。其中,可採用機械式鑽孔 方式’以降低製造成本;然而本發明並不僅限於此,其他 可形成通孔305a、305b之方式亦視實際應用狀況而採用。 然後,進行金屬層303圖案化之步驟。如第圖所 示’形成一乾膜(dry film)306於金屬層3〇3上再透過曝 ◎ 光顯影以形成圖案化乾膜306’ ’如第7d圖所示。之後根 據圖案化乾膜306’對金屬層303進行影像轉移例如餘<刻, 以形成一圖案化金屬層303’,最後移除圖案化乾膜3〇6,, 如第7E圖所示。在此結構中,圖案化金屬層3〇3,係包括 複數個銲墊(bonding pads)3033 ' 晶片墊(die pads)3〇31 和 錫球墊(ball pads)3035,其中錫球墊3035的位置係對應於 通孔305a、305b。另外,圖案化金屬層303,同樣可更包括 至少一無訊號之金屬導線(未顯示),以防止基板魅曲。 ◎ 接著’形成一圖案化介電層(patterned dielectric layer)308於圖案化金屬層303’之上方,且至少位於錫球墊 3035上方的介電層308會遮蔽住與錫球墊3035對應之通 孔305a、305b,如第7F圖所示。其中,圖案化介電層308 例如是包括至少一槽狀開口(Slot opening),以暴露出該些 銲墊3033。圖案化介電層308之材料例如是防銲綠漆 (solder mask,SM)、液晶聚合物(liquid crystal polyester, LCP)、或聚丙稀(p〇lypr0pyiene,PP)等等’但本發明並不 18 201041105 以此為限。 同樣的’自芯板302的上方往下俯視,圖案化介電層 308會覆蓋住與錫球墊3035對應之通孔305a、305b。 之後’可對晶片墊3031、銲墊3033和錫球墊3035 任一者、多者或全部之表面處,如裸露於圖案化介電層3〇8 外之部分,進行後續表面處理,而完成基板結構64之製 造;如第7G圖所示。形成第一表面處理層310a、31 Ob和 第二表面處理層310c’其中,第一表面處理層310a、310b 〇 分別覆蓋晶片墊3031和銲墊3033的表面及側壁處(且晶片 墊3031的表面及側壁被第一表面處理層310a完全覆蓋), 而第二表面處理層310c則覆蓋至少一或多個錫球墊3035 之表面。其中第一、二表面處理層310a、310b、310c之材 料係包括鎳/金、金、錫及其合金(如錫鉛合金)、或銀。另 外’也可依實際應用條件,以其他材料進行後處理,例如 ENEPIG、OSP等,本發明對此並不多作限制。 最後’移除載板40,而完成如第7H圖所示之基板結 Ο 構64的製造。 第8圖係繪示應用本發明第二實施例之第7H圖基板 之封裝件示意圖。如第8圖之封裝件結構74所示,製作 時亦應用一黏性物質(例如環氧樹脂)313將一晶粒315黏 附在晶片墊3031上方,並且經由銲線317電性連接晶粒 315之一主動表面與銲墊3〇73 ;之後,再形成一膠體 (Molding Comp〇und)319於芯板302,之上方,以密封圖案 化金屬層303’、圖案化介電層308、晶粒315和銲線317。 膠體219的材料例如是環氧樹脂或其他絕緣材料。另外, 201041105
i VVJ WA 第8圖中’位於晶粒315下方的芯板302部分為整面的連 續板’其怒板302之通孔305a、305b係對應於晶粒315 設置位置之區域範圍外。再者,通孔305a、3〇5b亦可填 充一導體材料(未顯示)使導體材料與錫球墊3〇35電性連 接。 因此,對於第7H圖和第8圖的基板結構而言,至少 部份圖案化金屬層303,覆蓋於通孔305a、305b上,以形 成下方對外電性連接的複數個第一接點,即錫球墊35。 而位於圖案化金屬層303’上方的圖案化介電層3〇8係至少 暴露出部分圖案化金屬層303,,以形成上方對外電性連接 的複數個第二接點,即銲墊3033。 同樣的,除了第7H圖所示之基板結構64,根據第二 實施例之製程也可稍微變化而製作其他態樣之基板結構。 請參照第9A圖,其繪示依照本發明第二實施例所製 作之另-種單層金屬層基板之示意圖。和帛7H圖基板不 同的是,製作如第9A圖所示之基板65時,係在形成圖案 化介電層之步驟中,除了使位於錫球塾3〇35上方的介電 層308a遮蔽住與錫球墊3〇35對應之通孔3〇5a、3〇5b外, 也在晶片墊3031上形成介電層娜,以部分覆蓋晶片墊 031之後’可再對裸露於圖案化介電層外 之部分進行後續處理,如鎳/金處理,所形成之第一表面處 里層310a、310b係部分覆蓋晶片墊3〇31和銲墊3〇33的 表面及側壁處,而第二表面處理層則覆蓋至少一或 多個錫球墊3035之表面。 20 .201041105 第9B圖係繪示應用本發明第二實施例之第9A圖基 板之封裝件示意圖。如第9B圖之封裝件結構75所示,製 作時亦應用一黏性物質(例如環氧樹脂)313將晶粒315黏 附在介電層308b(對應晶片墊3031處)之上方,並利用銲 線317電性連接晶粒315與銲墊3033,利用銲線318電性 連接晶粒315之一主動表面與晶片墊3〇31。之後,再以膠 體319密封圖案化金屬層3〇3,、圖案化介電層3〇8a、3〇8b、 晶粒315和銲線317、318。另外,第9B圖中,位於晶粒 〇 315下方的芯板3〇2部分亦為整面的連續板,其芯板3〇2 之通孔305a、305b係對應於晶粒315設置位置之區域範 圍外。同樣的,對於第9A圖和第9B圖的基板結構而言, 至少部份圖案化金屬層303,覆蓋於通孔305a、305b上, 以形成下方對外電性連接的複數個第一接點,即錫球墊 3035。而位於圖案化金屬層3〇3’上方的圖案化介電層3〇8 係至少暴露出部分圖案化金屬層3〇3,,以形成上方對外電 性連接的複數個第二接點,即銲墊3〇33。 〇 另外,除了第7H圖和第9A圖所示之基板結構64、 65 ’也可根據第二實施例之製程製作出錫球墊位於晶粒設 置區域範圍内之基板態樣。 凊參照第10A圖,其續·示依照本發明第二實施例所 製作之再一種單層金屬層基板之示意圖。和第7H圖基板 64不同的是,製作如第1〇A圖所示之基板結構%時在 鑽孔時係在對應晶粒位置處形成多個通孔3〇5c、3〇5(1、 3〇5e,而在圖案化金屬層之步驟中係形成多個銲墊 21
I 201041105
i W:>WA 3034(bonding pads)和多個與通孔 305c、305d、305e 位置 對應之錫球墊3〇36(ball pads)。在形成圖案化介電層後, 該些錫球墊3036係被圖案化介電層308c完全覆蓋。之 後’亦可對裸露於圖案化介電層308a外之部分進行後續 處理(如鎳/金處理)(未顯示於第10A圖中)。 第10B圖係繪示應用本發明第二實施例之第1〇A圖 基板之封裝件示意圖。如第10B圖之封裝件結構76所示, 製作時亦應用一黏性物質(例如環氧樹脂)313將晶粒315 黏附在圖案化介電層308c之上方,並利用銲線317電性 ◎ 連接晶粒315之一主動表面與銲墊3034。之後,再以膠體 319密封圖案化金屬層3〇3’、圖案化介電層3〇8a和3〇8c、 晶粒315和鮮線317。而此種封裝件結構76可透過位於晶 粒315正下方之錫球墊3036’使晶粒315與一外部元件(如 一電路板,未顯示)作電性連接。同樣的,對於第1〇A圖 和第10B圖的基板結構而言,至少部份圖案化金屬層3〇3, 覆蓋於通孔305c、305d、305e上,以形成下方對外電性連 接的複數個第一接點,即錫球墊3036。而位於圖案化金屬❹ 層303’上方的圖案化介電層308a係至少暴露出部分圖案 化金屬層303’,以形成上方對外電性連接的複數個第二接 點’即銲墊3034。 雖然,如第10B圖所示之封裝件結構76看似與第8 圖和第9B圖所示之結構較為不同,但是位於晶粒315下 方之該些錫球墊3036的位置也同樣會被圖案化介電層 3〇8c完全覆蓋。因此,自芯板3〇2的上表面側往下俯視 圖案化介電層308同樣會覆蓋住與錫球墊3〇36對應之通 22 201041105 孔 305c 、 305d 、 305e 。 與第一實施例製法不同的是,第二實施例係藉由一載 板40進行基板製作,因此根據第二實施例所製成之基板 結構64、65、66並無黏著層203,(第3H、5A、6A圖)的 存在。另外,雖然在第一、二實施例係以銅箔基板(CCL) 的中心層作為芯板302之舉例說明,但本發明並不以此為 限,也可選用其他材質作為實施例基板結構之基底材,而 〇對基底材圖案化(ex形成通孔)之方式亦可因基底材料的不 同作適當選擇。 第三實施例 在第二實施例中同樣運用一載板進行本發明之基板 製作。但第三實施例與第二實施例之步驟略有不同。 請參照第11A〜111圖’其緣示本發明第三實施例之 單層金屬層基板之製造方法。首先,提供一基底材4〇2, 〇並將基底材402設置於-載板50上,如第UA圖所示。 在此實施例中,係以一 ABF膜材為例作說明但本發明並 不以此為限。之後,於基底材術之上表面形成一金屬層 403 ’例如一銅層,如第11]B圖所示。 然後,進行金屬層403圖案化之步驟。如第11C圖所 示,形成一乾膜(dry film)4〇6於金屬層4〇3上再透過曝 光顯影以形成圖案化乾膜406,,如第UD圖所示。之後根 據圖案化乾膜406,對金屬層4〇3進行影像轉移例如蝕刻’ 以形成一圖案化金屬層4〇3,,之後移除圖案化乾膜4〇6,, 23 201041105 1 W33Z/r/\ 如第11E圖所示。在此結構中,圖案化金屬層4〇3,係包括 複數個銲墊(bonding pads)4033 和晶片墊(die pads)4031。 同樣,製作圖案化金屬層403’時亦可包括形成至少一無訊 號之金屬導線(未顯示)’以防止基板翹曲。 之後’移除載板50,如第up圖所示。 接著’如第11G圖所示’在基底材402處形成多個通 孔405a、405b ’且通孔位置暴露出圖案化金屬層4〇3,的部 分下表面’以形成多個錫球塾(bail pa(js)4〇35。形成通孔 405a、405b的方式沒有特殊限制,而是視實際應用狀況而 定。若以ABF膜材作基底材402時,可利用雷射鑽孔方式 形成該些通孔405a、405b。 然後’形成一圖案化介電層(patterned dielectric layer)408於圖案化金屬層403’之上方,且至少位於錫球墊 4035上方的介電層408會遮蔽住與錫球墊4〇35對應之通 孔405a、405b ’如第11H圖所示。其中,圖案化介電層 408例如是包括至少一槽狀開口(siot opening),以暴露出 該些銲墊4033。圖案化介電層408之材料例如是防銲綠漆 (solder mask ’ SM)、液晶聚合物(liquid crystal polyester, LCP)、或聚丙烯(polypropylene ’ PP)等等,但本發明並不 以此為限。 同樣的’自基底材402的上方往下俯視,圖案化介電 層408會覆蓋住與錫球塾4035對應之通孔405a、405b。 之後’可對晶片墊4031、銲墊4033和錫球墊4035 任一者、多者或全部之表面處’如裸露於圖案化介電層408 外之部分,進行後續處理’而完成基板結構67的製造; 24 如第111圖所示,可形成第一表面處理層410a、410b和第 二表面處理層410c’其中,第一表面處理層410a、410b 分別覆蓋晶片墊4031和銲墊4033的表面及側壁處(且晶片 墊4031的表面及側壁均被第一表面處理層41〇a完全覆 蓋)’而第二表面處理層410c則覆蓋至少一或多個錫球墊 4035之表面。其中第一、二表面處理層41〇a、4i〇b、410c 之材料係包括鎳/金、金、錫及其合金(如錫鉛合金)、或銀。 另外,也可依實際應用條件,以其他材料進行後處理,例 〇 如ENEpIG、OSP等,本發明對此並不多作限制。 第111圖所製成之基板結構67係與第7H圖之基板結 構64相同。而應用本發明第三實施例之第UI圖基板之封 裝件’其結構亦請參照第8圖,在此不再贅述。 同樣的,除了第111圖所示之基板結構67,根據第三 實施例之製程也製作出其他態樣之基板結構。 請參照第12圖,其繪示依照本發明第三實施例所製 〇作之另一種單層金屬層基板之示意圖。其製成之基板結構 68係和第9A圖所示之基板結構65相同。其中,在形成 圖案化介電層之步驟中,除了使位於錫球墊4〇35上方的 介電層408a部分或完全遮蔽住與錫球墊4〇35對應之通孔 405a、405b外,也在晶片墊4〇31上形成介電層4〇訃,以 部分覆蓋晶片墊403卜之後,可再對裸露於圖案化介電層 408a、408b外之部分進行後續處理(如錄/金處理),其製成 之基板結構68請參照第9Affi,在此不再資述。而應用本 發明第三實施例之第12圖基板所製成之封褒件,係將晶 25 201041105 粒315黏附在介電層408b(對應晶片墊4031處)之上方, 其封裝件結構亦同第二實施例之第9B圖,在此不再贅述。 另外’除了第111圖和第12圖所示之基板結構、 68,同樣也可根據第三實施例之製程製作出錫球墊位於晶 粒設置區域範圍内之基板態樣。 請參照第13圖,其繪示依照本發明第三實施例所製 作之再一種單層金屬層基板之示意圖。在基底材4〇2處係 形成多個通孔405c、405d、405e,在圖案化金屬層之步驟 中係形成多個銲墊4034(bonding pads)和錫球墊4036(ball pads),且通孔405c、405d、405e係與錫球墊4036之位置 --對應。在形成圖案化介電層後,該些錫球墊4036係 被圖案化介電層408c完全覆蓋。之後,亦可對裸露於圖 案化介電層408a外之部分進行後續處理(如鎳/金處理)(未 顯示於第13圖中)。其製成之基板結構69係和第10A圖 所示之基板結構66相同,而應用本發明第三實施例之第 13圖基板所製成之封裝件,其結構亦同第二實施例之第 10B圖’在此均不再贅述。 綜上,第二、三實施例所提出之製法都是在製程中使 用載板,先將芯板302/基底材402之下表面先設置於載板 上,再形成一圖案化金屬層於芯板302/基底材之上表面。 但第二、三實施例製法不同的是,第二實施例先形成多個 通孔於芯板302的下表面處,然後將芯板302設置於載板 40上,再形成圖案化金屬層於芯板302之上表面。第三實 26 201041105 施例則是先形成圖案化金屬層於基底材402之上表面,再 形成多個通孔於基底材402之下表面處。兩種方式都可製 作出實施例所揭露之結構。 〇 〇 綜上所述,根據本發明實施例所製作出之基板結構, 其厚度範圍可減薄至約4〇μπι〜Ι30μιη之範圍,相較於傳 統的”2層基板”結構,本發明所提出之基板厚度、及應用 此基板之封裝件的整體厚度都可大為下降,其輕薄的^型 十分適合小尺寸應用產品的需求。再者,本發明所提出此 基板結構及應用其之封裝件之製造方法其製料但 ^車=分適合量產,兼具低製造成本和高產品良率的優 付口制電子產品對於尺寸、外型輕薄化和低價格之 小型料產品,;^件有&^力祕市場價格較低的 所述,雖然本發明已以較佳實施例揭露如上,鈇 :識二本發明所屬技術領域中具有通常 利=定;:準本發明之保護範圍當視後附之申_ 【圖式簡單說明】 第A 1F圖繚不一種傳統整合性基板之製程示意 第2圖為另—種傳統整合性基板之示意圖。 201041105
1 W53Z/PA 第1圖繪示一種傳統内埋式線路之整合性基板之示意圖。 第3A〜3F圖繪示本發明第一實施例之單層金屬層基 板之製造方法。 第4圖係繪示應用本發明第一實施例之第3F圖基板 之封裝件示意圖。 第5A圖繪示依照本發明第一實施例所製作之另一種 單層金屬層基板之示意圖。 第5B圖係繪示應用本發明第一實施例之第5A圖基 板之封裝件示意圖。 第6A圖,其繪示依照本發明第一實施例所製作之再 一種單層金屬層基板之示意圖。 第6B圖係繪示應用本發明第一實施例之第6A圖基 板之封裝件示意圖。 第7A〜7H圖,其繪示本發明第二實施例之單層金屬 層基板之製造方法。 第8圖係繪示應用本發明第二實施例之第7H圖基板 之封裝件示意圖。 第9A圖,其繪示依照本發明第二實施例所製作之另 一種單層金屬層基板之示意圖。 第9B圖係繪示應用本發明第二實施例之第9A圖基 板之封裝件示意圖。 第10A圖,其繪示依照本發明第二實施例所製作之 再一種單層金屬層基板之示意圖。 第10B圖係繪示應用本發明第二實施例之第10A圖 基板之封裝件示意圖。 28 201041105 第UA〜111圖,其繪示本發明第三實施例之單層金 屬層基板之製造方法。 第12圖,其繪示依照本發明第三實施例所製作之另 一種單層金屬層基板之示意圖。 第13圖,其纟會示依照本發明第三實施例所製作之再 一種單層金屬層基板之示意圖。 【主要元件符號說明】 G 102 中心 層 103 第一 導電層 104 第二 導電層 106 孔洞 107、115、116、117 :銅層 108 :圖案化乾膜 202、 202,、302、302’ :芯板 203、 203’ :黏著層 〇 205a、205b、205c、205d、205e、305a、305b、305c、 305d、305e、405a、405b、405c、405d、405e :通孔 207、303、403 :金屬層 207’、303’、403’ :圖案化金屬層 2071、3031、4031 :晶片墊(die pads) 2073、2074、3033、3034、4033、4034 :銲替(bonding pads) 2075、2076、3035、3036、4035、4036 :錫球塾(ball pads) 29 201041105
TW5527PA 209、209a、209b、209c、308、308a、308b、308c、 408、408a、408b、408c :圖案化介電層 210a、210b、310a、310b、410a、410b :第一表面處 理層 210c、310c、410c :第二表面處理層 213、313、413 :黏性物質 215、315 :晶粒 217、218、317、318 :銲線 219、319 :膠體 306、406 :乾膜 306’、406’ :圖案化乾膜 40、50 :載板 402、402’ :基底材 61 ' 62 ' 63 ' 64、65、66、67、68 ' 69 :基板結構 71、72、73、74、75、76、77、78、79 :封裝件結構

Claims (1)

  1. 201041105 七、申請專利範圍: 1. 一種單層金屬層基板,其結構包括: 一基底材,具有一上表面和一下表面; 一黏著層,配置於該基底材的該上表面; 複數個通孔,且該些通孔貫穿該基底材與該黏著層; 一圖案化金屬層(patterned metal layer),配置於該黏 著層之上方,其中至少部份該圖案化金屬層覆蓋於該些通 孔上,以形成下方對外電性連接的複數個第一接點;以及 〇 一圖案化介電層(patterned dielectric layer)配置於該 圖案化金屬層上方,其中該圖案化介電層係至少暴露出部 分該圖案化金屬層,以形成上方對外電性連接的複數個第 二接點。 2. 如申請專利範圍第1項所述之基板,其中該圖案化 金屬層更包括至少一晶片墊(die pads),該晶片墊被該圖案 化介電層至少部分覆蓋。 3. 如申請專利範圍第1項所述之基板,其中至少該些 Ο 第一接點上方被該圖案化介電層部分或完全覆蓋。 4. 如申請專利範圍第1項所述之基板,其中該圖案化 介電層更包括至少一槽狀開口(Slot opening),可暴露出該 些第二接點。 5. 如申請專利範圍第1項所述之基板,更包括: 一第一表面處理層(Surface finish layer),至少覆蓋該 些晶片墊或該些第二接點的任一者或多者之表面及側 壁;和 一第二表面處理層,至少覆蓋該些第一接點的任一者 31 201041105 TW5527PA 或多者之表面。 6. 如申請專利範圍第5項所述之基板,其中該第一和 該第二表面處理層之材料係包括鎳/金、金、錫及其合金、 或銀。 7. 如申請專利範圍第1項所述之基板,其中該基底材 係為一芯板’該芯板之材料包括雙馬來酰亞胺樹脂 (Bismaleimide ’ BT)、聚亞醯胺樹脂(p〇iyimide,pi)、液晶 聚合樹脂(LCP)、環氧樹脂(Ep〇xy)、或具單面銅箔層之樹 脂。 8. 如申請專利範圍第丨項所述之基板,其中該基底材 係為一一氣化銨樹脂(Ammonium Bifluoride,ABF)膜材。 9·如申請專利範圍第8項所述之基板,其中(製法)該 些通孔位於該基底材之該下表面的尺寸大於該些通孔位 於該基底材之該上表面的尺寸。 10. 如申請專利範圍第1項所述之基板,其中該圖案 化金屬層更包括至少一無訊號之金屬導線(Dummy trace)。 11. 如申請專利範圍第1項所述之基板,其中該圖案 化介電層之材料係為防銲綠漆(s〇lder mask,SM)、液晶聚 合物(liquid crystal polyester,LCP)、或聚丙烯 (polypropylene,PP) 〇 12. 如申請專利範圍第1項所述之基板,其厚度範圍 約在40μιη〜130μιη之間。 13. —種單層金屬層基板,其結構包括·· 一基底材’具有一上表面和一下表面; 複數個通孔,且該些通孔貫穿該基底材的該上表面與 32 201041105 該基底材的該下表面; 一圖案化金屬層(patterned metal layer),配置於該基 底材之該上表面,其中至少部份該圖案化金屬層覆蓋於該 些通孔上以形成下方對外電性連接的複數個第一接點; 一圖案化介電層(patterned dielectric layer),配置於該 圖案化金屬層上方,其中該圖案化介電層係至少暴露出部 分該圖案化金屬層以形成上方對外電性連接的複數個第 二接點;以及 〇 一第一表面處理層(Surface finish layer),至少覆蓋於 該些第二接點的任一或多者之表面及側壁。 14. 如申請專利範圍第13項所述之基板,其中該圖案 化金屬層更包括至少一晶片墊(die pads),該晶片墊被該圖 案化介電層至少部分覆蓋。 15. 如申請專利範圍第13項所述之基板,其中至少該 些第一接點上方被該圖案化介電層部分或完全覆蓋。 16. 如申請專利範圍第13項所述之基板,其中該圖案 Ο 化介電層更包括至少一槽狀開口(Slot opening),可暴露出 該些第二接點。 17. 如申請專利範圍第14項所述之基板,其中該第一 表面處理層至少覆蓋該些晶片墊的任一者或多者之表面 及側壁。 18. 如申請專利範圍第13項所述之基板,更包括一第 二表面處理層,至少覆蓋該些第一接點的任一者或多者之 表面。 19. 如申請專利範圍第18項所述之基板,其中該第一 33 201041105 TW5527PA 和該第二表面處理層之材料係包括錄/金、金、錫及其合 金、或銀。 20.如申請專利範圍第13項所述之基板,其中該基底 材係為一芯板,該芯板之材料包括雙馬來酰亞胺樹脂 (Bismaleimide ’ BT)、聚亞醯胺樹脂(polyimide,PI)、液晶 聚合樹脂(LCP)、環氧樹脂(Ep0Xy)、或具單面銅箔層之樹 脂0 21. 如申請專利範圍第13項所述之基板’其中該基底 材係為一二氟化銨樹脂(Ammonium Bifluoride,ABF)膜材。d 22. 如申請專利範圍第21項所述之基板,其中該些通 孔位於該基底材之該下表面的尺寸大於該些通孔位於該 基底材之該上表面的尺寸。 23. 如申請專利範圍第13項所述之基板,其中該圖案 化金屬層更包括至少一無訊號之金屬導線(Dummy trace)。 24. 申請專利範圍第丨3項所述之基板,其中該圖案化 )丨電層之材料係為防鲜綠漆(solder mask,SM)、液晶聚合 物(liquid crystal polyester ,LCP)、或聚丙烯 CJ (polypropylene,PP) 〇 25. 如申請專利範圍第13項所述之基板,其厚度範圍 約在40μιη〜130μιη之間。 26. —種單層金屬層基板之製造方法’包括: 形成一基底材,該基底材具有一上表面和一下表面; 形成一黏著層於該基底材的該上表面; 形成複數個通孔,且該些通孔貫穿該基底材與該黏著 層; 34 201041105 形成一圖案化金屬層(patterned metal layer)於該黏著 層之上方,其中至少部份該圖案化金屬層覆蓋於該些通孔 上’以形成下方對外電性連接的複數個第一接點;和 形成一圖案化介電層(patterned dielectric layer)於該 圖案化金屬層上方,其中該圖案化介電層係至少暴露出部 分該圖案化金屬層,以形成上方對外電性連接的複數個第 二接點。 27.如申請專利範圍第26項所述基板之製造方法,其 〇 中形成該基底材之步驟中,係包括: 提供一銅箔基板(copper clad laminate,CCL),係由一 芯板(Core)和下上表面各貼附一銅箔而成;和 移除該芯板下上表面之兩該銅箔。 28·如申請專利範圍第27項所述基板之製造方法,其 中對該基底材係以機械式鑽孔形成該些通孔。 29. 如申請專利範圍第26項所述基板之製造方法,其 中係以一二氟化銨樹脂(Ammonium Bifluoride,ABF)膜材 〇作為該基底材。 30. 如申請專利範圍第26項所述基板之製造方法,其 中形成該圖案化金屬層之步驟係包括: 形成一金屬層於該基底材之該上表面; 形成一乾膜(dry film)於該金屬層上並圖案化該乾膜; 根據該乾膜之圖案對該金屬層進行影像轉移,以形成 該圖案化金屬層;和 移除該圖案化乾膜。 31·如申請專利範圍第3〇項所述基板之製造方法,其 35 201041105 TW5527PA 中圖案化該乾膜之步驟包括對乾膜進行曝光和顯影,並根 據該乾膜之圖案對該金屬層進行蝕刻以完成影像轉移,形 成該圖案化金屬層。 32. 如申請專利範圍第26項所述基板之製造方法,其 中所形成之該圖案化金屬層更包括至少一晶片墊(die pads),且形成該圖案化介電層於該圖案化金屬層上方後, 該晶片墊被該圖案化介電層至少部分覆蓋。 33. 如申請專利範圍第26項所述基板之製造方法,其 中形成該圖案化介電層於該圖案化金屬層上方後,至少該 些第一接點被該圖案化介電層部分或完全覆蓋。 34. 如申請專利範圍第26項所述基板之製造方法,其 中形成該圖案化介電層之步驟中更包括形成至少一槽狀 開口(Slot opening),以暴露出該些第二接點。 35. 如申請專利範圍第26項所述基板之製造方法,更 包括: 形成一第一表面處理層(Surface finish layer) ’至少覆 蓋該些晶片墊或該些第二接點的任一者或多者之表面及 側壁;和 形成一第二表面處理層,至少覆蓋該些第一接點之表 面。 36. 如申請專利範圍第35項所述基板之製造方法,其 中係選用鎳/金、金、錫及其合金、或銀做為該第一和該第 二表面處理層之材料。 37. 如申請專利範圍第26項所述基板之製造方法,其 中係選用防銲綠漆(solder mask,SM)、液晶聚合物(liquid 36 201041105 crystal polyester,LCP)、或聚丙烯(polypropylene,PP)作 為該圖案化介電層之材料。 38. 如申請專利範圍第26項所述基板之製造方法,所 製成之該基板係具有一厚度約40μιη〜130μιη。 39. —種單層金屬層基板之製造方法,包括: 形成一基底材,具有一上表面和一下表面; 形成複數個通孔,且該些通孔貫穿該基底材的該上表 面與該基底材的該下表面; Ο 形成一圖案化金屬層(patterned metal layer)於該基底 材之該上表面,其中至少部份該圖案化金屬層覆蓋於該些 通孔上,以形成下方對外電性連接的複數個第一接點; 形成一圖案化介電層(patterned dielectric layer)於該 圖案化金屬層上方,其中該圖案化介電層係至少暴露出部 分該圖案化金屬層,以形成上方對外電性連接的複數個第 二接點;和 形成一第一表面處理層(Surface finish layer),至少覆 ❹蓋於該些第二接點任一或多者的表面及側壁。 40. 如申請專利範圍第39項所述基板之製造方法,其 中形成該基底材之步驟中,係包括: 提供一銅箔基板(copper clad laminate,CCL),係由一 芯板(Core)和下上表面各貼附一銅箔而成;和 移除該芯板下上表面之兩該銅箔。 41. 如申請專利範圍第40項所述基板之製造方法,其 中對該基底材係以機械鑽孔形成該些通孔。 42. 如申請專利範圍第39項所述基板之製造方法,其 37 201041105 TW5527PA 中係以一二氟化錢樹脂(Ammonium Bifluoride,ABF)膜材 作為該基底材。 43. 如申請專利範圍第39項所述基板之製造方法,其 中形成該些通孔於該基底材之該上表面與下表面之間 後,更包括步驟: 將該基底材之該下表面設置於一載板(carrier)上;以 及 於上述形成該圖案化金屬層於該基底材之該上表面 及形成該圖案化介電層於該圖案化金屬層上方之後,再移 除該載板。 44. 如申請專利範圍第43項所述基板之製造方法,其 中在形成一基底材之後與形成該些通孔於該基底材之 前,其步驟更包括: 將δ玄基底材之該下表面設置於載板(carrier)上;以 及 並於形成該圖案化金屬層於該基底材之該上表面之 後,移除該載板。 45. 如申請專利範圍第39項所述基板之製造方法,其 中形成該圖案化金屬層之步驟係包括: 形成一金屬層於該基底材之該上表面; 形成一乾膜(dry film)於該金屬層上並圖案化該乾膜; 根據該乾膜之圖案對該金屬層進行影像轉移,以形成 該圖案化金屬層;和 移除該圖案化乾膜。 46. 如申請專利範圍第45項所述基板之製造方法,其 38 201041105 中圖案化該乾膜之步驟包括對該乾膜進行曝光和颟3, 根據該乾祺之圖案對該金屬層進行蝕刻以完: 移,形成_案化金制。 %像轉 47. 如申請專利範圍第39項所述基板之製造方法,其 中所形成之該圖案化金屬層更包括至少一 :、 Α Λ 日日月塾(die Pa s 形成該圖案化介電層於該圖案化金屬層上方後, 該晶片塾被該圖案化介電層至少部分覆蓋。 < ’ Ο
    48. 如申請專利範圍第39項所述基板之製造方法其 中形成該圖案化介電層於該圖案化金屬層上方後,至少該 些第一接點被該圖案化介電層部分或完全覆蓋。 〜 49·如申請專利範圍第39項所述基板之製造方法,其 中該圖案化介電層更包括形成至少一槽狀開口(sw opening) ’以暴露出該些第二接點。 5〇.如申請專利範圍第47項所述基板之製造方法,其 中所形成之該第一表面處理層係至少覆蓋該些晶片墊^ 任一者或多者之表面及侧壁。 51·如申請專利範圍第39項所述基板之製造方法更 包括形成一第二表面處理層,至少覆蓋該些第一接點的任 一者或多者之表面。 52·如申請專利範圍第51項所述基板之製造方法其 中係選用錦/金、金、錫及其合金、或銀做為該第一和該第 二表面處理層之材料。 53.如申請專利範圍第39項所述基板之製造方法,其 中係選用防銲綠漆(solder mask,SM)、液晶聚合物(liquid crystal polyester,LCP)、或聚丙嫦(polypropylene,PP)作 39 201041105 TW5527FA 為該圖案化介電層之材料。 54. 如申請專利範圍第39項所述基板之製造方法,所 製成之該基板係具有一厚度約40μηι〜。 55. —種具有單層金屬層基板之封装件結構,包括: 一單層金屬層基板,其中該基板包含一基底材、一黏 著層、複數通孔、一圖案化金屬層(patterned metal layer) 和一圖案化介電層(patterned dielectric layer),該黏著層配 置於該基底材的一上表面,該些通孔貫穿該基底材與該黏 著層,該圖案化金屬層配置於該黏著層上方,且至少部份 該圖案化金屬層覆蓋於該些通孔上以形成下方對外電性 連接的複數個第一接點,該圖案化介電層配置於該圖案化 金屬層上,且該圖案化介電層係至少暴露出部分該圖案化 金屬層以形成上方對外電性連接的複數個第二接點; 至少一晶粒(die)與該些第二接點電性連接;以及 一膠體(Molding compound),係配置於該基底材之該 上表面上方,並覆蓋該圖案化金屬層、該圖案化介電層和 該晶粒。 56. 如申請專利範圍第55項所述之封裝件結構,其中 該圖案化金屬層更包括至少一晶片墊(die pads),該晶粒係 設置於該些晶片墊之一的上方。 57. 如申請專利範圍第56項所述之封裝件結構,其中 至少該些晶片墊之一被該圖案化介電層部分或完全覆 蓋,該晶粒則設置於該圖案化介電層上。 58. 如申請專利範圍第55項所述之封裝件結構’其中 該圖案化介電層更包括至少一槽狀開口(Slot opening),可 201041105 暴露出該些第二接點。 59.如申請專利範圍第乃項所述之封裝件結構,更包 括: 第表面處理廣(Surface finish layer),至少覆蓋該 些晶片t•或該些第二接點的任一者或多者之表面及側 壁;和 一第二表面處理層,至少覆蓋該些第一接點任一者或 多者之表面。 〇 60.如申請專利範圍第59項所述之封裝件結構,其中 該第一和該第二表面處理層之材料係包括鎳/金、金、錫及 其合金、或銀。 61. 如申請專利範圍第55項所述之封裝件結構,其中 該晶粒係設置於該圖案化介電層之上方,該些第一接點之 位置係對應於該晶粒之下方且被該圖案化介電層部分或 完全覆蓋。 62. 如申請專利範圍第55項所述之封裝件結構,更包 〇括複數條銲線電性連接該晶粒之一主動表面和該些第二 接點。 63. 如申請專利範圍第55項所述之封裝件結構,其中 該基底材係為一芯板’該芯板之材料包括雙馬來酰亞胺樹 脂(Bismaleimide,ΒΤ)、聚亞醯胺樹脂(p〇iyimide,pi)、液 晶聚合樹脂(LCP)、環氧樹脂(Epoxy)、或具單面銅箔層之 樹脂。 64. 如申請專利範圍第55項所述之封裝件結構,其中 該基底材係為一二氟化敍樹脂(Ammonium Bifluoride, 41 201041105 TW5527PA ABF)膜材。 65. 如申請專利範圍第64項所述之封裝件結構,其中 該些通孔位於該基底材之一下表面的尺寸大於該些通孔 位於基底材之該上表面的尺寸。 66. 如申請專利範圍第55項所述之封裝件結構’其中 該些通孔更包括填充一導體材料,真該導體材料係與該些 第一接點電性連接。 67. 如申請專利範圍第55項所述之封裝件結構’其中 該圖案化金屬層更包括至少一無訊號之金屬導線(Dummy trace) 〇 68. 如申請專利範圍第55項所述之封裝件結構,其中 該圖案化介電層之材料係包括防銲綠漆(solder mask, SM)、液晶聚合物(liquid crystal p〇lyester ’ LCP)、或聚丙 稀(polypropylene,PP) ° 69. 如申請專利範圍第55項所述之封裝件結構,其中 該基底材、該圖案化金屬層和該圖案化介電層之一總厚度 範圍約在40μιη〜130μιη之間。 70. 如申請專利範圍第55項所述之封裝件結構,其中 該膠體之側面與該基底材之侧面為一共平面。 71. —種具有單層金屬層基板之封裝件結構,包括: 一單層金屬層基板,其中該基板包含一基底材、複數 通孔、一圖案化金屬層(patterned metal lay er)、一圖案化介 電層(patterned dielectric layer)和一第一表面處理層 (Surface finish layer) ’該些通孔貫穿該基底材,該圖案化 金屬層配置於該基底材之一上表面,且至少部份該圖案化 42 201041105 金屬層覆蓋於該些通孔上以形成下方對外電性連接的複 數個第一接點,該圖案化介電層配置於該圖案化金屬層上 方,且該圖案化介電層係至少暴露出部分該圖案化金屬層 以形成上方對外電性連接的複數個第二接點,而該第一表 面處理層至少覆蓋於該些第二接點的任一或多者之表面 及侧壁; 至少一晶粒(die)與該些第二接點電性連接;以及 一膠體(Molding compound),係配置於該基底材之該 〇 上表面上方,並覆蓋該圖案化金屬層、該圖案化介電層和 該晶粒。 72. 如申請專利範圍第71項所述之封裝件結構,其中 該圖案化金屬層更包括至少一晶片墊,該晶粒係設置於該 些晶片墊之一的上方。 73. 如申請專利範圍第72項所述之封裝件結構,其中 至少該些晶片墊之一被該圖案化介電層部分或完全覆 蓋,該晶粒則設置於該圖案化介電層上。 〇 74·如申請專利範圍第71項所述之封裝件結構,其中 該圖案化介電層更包括至少一槽狀開口(Slot opening),可 暴露出該些第二接點。 75. 如申請專利範圍第72項所述之封裝件結構,其中 該第一表面處理層至少覆蓋該些晶片墊的任一者或多者 之表面及侧壁。 76. 如申請專利範圍第71項所述之封裝件結構,更包 括一第二表面處理層,至少覆蓋該些第一接點的任一者或 多者之表面。 43 201041105 TW5527PA 77. 如申請專利範圍第76項所述之封裝件結構,其中 該第一和該第二表面處理層之材料係包括鎳/金、金、錫及 其合金、或銀。 78. 如申請專利範圍第71項所述之封裝件結構,其中 該晶粒係設置於該圖案化介電層之上方,該些第一接點之 位置係對應於該晶粒之下方且被該圖案化介電層部分或 完全覆蓋。 79. 如申請專利範圍第71項所述之封裝件結構,係包 括複數條銲線電性連接該晶粒之一主動表面和該些第二 接點。 80. 如申請專利範圍第71項所述之封裝件結構,其中 該基底材係為一芯板’該芯板之材料包括雙馬來酰亞胺樹 脂(Bismaleimide,BT)、聚亞醢胺樹脂(p〇iyimide,pi)、液 晶聚合樹脂(LCP)、環氧樹脂(Ep〇xy)、或具單面銅箔層之 樹脂。 81·如申請專利範圍第71項所述之封裝件結構,其中 /基底材係為一氟化錢樹脂(Ammonium Bifluoride, ABF)膜材。 82. 如申請專利範圍第81項所述之封裝件結構,其中 該些通孔位於該基底材之—下表面的尺寸大於該些通孔 位於基底材之該上表面的尺寸。 83. 如申請專利範圍第7ι項所述之封裝件結構,其中 該些通孔更填充-導體材料,且該導體材料與該些第一接 點電性連接。 84. 如申清專利範圍第71項所述之封裝件結構,其中 44 201041105 該圖案化金屬層更包括至少一無訊號之金屬導線(Dummy trace) ° 85. 如申請專利範圍第71項所述之封裝件結構,其中 該圖案化介電層之材料係包括防鮮綠漆(solder mask, SM)、液晶聚合物(liquid crystal polyester,LCP)、或聚丙 烯(polypropylene,PP) ° 86. 如申請專利範圍第71項所述之封裝件結構,其中 該基底材、該圖案化金屬層和該圖案化介電層之一總厚度 Ο 範圍約在40μπι〜130μιη之間。 87. 如申請專利範圍第71項所述之封裝件結構,其中 該膠體之侧面與該基底材之側面為一共平面。 88. —種具有單層金屬層基板之封裝件之製造方法, 包括: 提供一單層金屬層基板,其中該基板包含一基底材、 一黏著層、複數通孔、一圖案化金屬層(patterne(j metal layer)和一圖案化介電層(patterned dielectric layer),該黏 ❹著層形成於該基底材的一上表面,該些通孔貫穿該基底材 與該黏著層,該圖案化金屬層形成於該黏著層上方,且至 少部份該圖案化金屬層覆蓋於該些通孔上以形成下方對 外電性連接的複數個第一接點,該圖案化介電層配置於該 圖案化金屬層上,且該圖案化介電層係至少暴露出部分該 圖案化金屬層以形成上方對外電性連接的複數個第二接 電性連接至少一晶粒與該些第二接點;以及 形成一膠體於該基底材之該上表面上方,並覆蓋該圖 45 201041105 TW5527PA 案化金屬層、該圖案化介電層和該晶粒。 89. 如申請專利範圍第88項所述封裝件之製造方法, 其中該基底材係為一芯板(Core),並以機械鑽孔形成該些 通孔。 90. 如申請專利範圍第88項所述封裝件之製造方法, 其中該基底材係為一二氟化銨樹脂(Ammonium Bifluoride,ABF)膜材,並以雷射鑽孔方式形成該些通孔。 91. 如申請專利範圍第88項所述封裝件之製造方法, 其中所形成之該圖案化金屬層更包括至少一晶片墊(Die pad),且形成該圖案化介電層於該圖案化金屬層上方後, 該晶片墊被該圖案化介電層至少部分覆蓋。 92. 如申請專利範圍第88項所述封裝件之製造方法, 其中形成該圖案化介電層於該圖案化金屬層上方後,至少 該些第一接點被該圖案化介電層部分或完全覆蓋。 93. 如申請專利範圍第88項所述封裝件之製造方法, 其中該圖案化介電層更包括形成至少一槽狀開口(Slot opening) ’可暴露出該些第二接點。 94. 如申請專利範圍第88項所述封裝件之製造方法, 更包括: 形成一第一表面處理層(Surface finish layer),至少覆 蓋該些晶片墊或該些第二接點的任一者或多者之表面及 側壁;和 形成一第二表面處理層,至少覆蓋該些第一接點之表 面。 95. 如申請專利範圍第94項所述封裝件之製造方法, 46 201041105 其中係選用鎳/金、金、錫及其合金、或銀做為該第一和該 第二表面處理層之材料。 96. 如申請專利範圍第88項所述封裝件之製造方法, 更包括形成複數條銲線電性連接該晶粒之一主動表面和 該些第二接點。 97. 如申請專利範圍第項所述封裝件之製造方法, 更包括填充一導體材料於該些通孔,且該導體材料係與該 些第一接點電性連接。 © 98.如申請專利範圍第88項所述封裝件之製造方法, 其中係選用防銲綠漆(s〇lder mask,SM)、液晶聚合物(liquid crystal polyester ’ LCP)、或聚丙烯(p〇iypr〇pyiene,pp)作 為該圖案化介電層之材料。 99_如申請專利範圍第88項所述封裝件之製造方法, 所製成之該基板係具有一厚度約40μηι〜130μιη。 100. —種具有單層金屬層基板之封裝件之製造方 法,包括: ❹ 形成一單層金屬層基板,其中該基板包含一基底材、 複數通孔、一圖案化金屬層(patterned metal layer)、一圖案 化介電層(patterned dielectric layer)和一第一表面處理層 (Surface finish layer) ’該些通孔貫穿該基底材,該圖案化 金屬層配置於該基底材之一上表面,且至少部份該圖案化 金屬層覆蓋於該些通孔上以形成下方對外電性連接的複 數個第一接點,該圖案化介電層配置於該圖案化金屬層上 方,且該圖案化介電層係至少暴露出部分該圖案化金屬層 以形成上方對外電性連接的複數個第二接點,而該第一表 47 201041105 TW5527PA 面處理層至少覆蓋於該些第二接點的任一或多者之表面 及側壁; 電性連接至少一晶粒與該些第二接點;以及 形成一膠體(Molding compound)於該基底材之該上表 面上方,並覆蓋該圖案化金屬層、該圖案化介電層和該晶 粒。 101. 如申請專利範圍第100項所述封裝件之製造方 法,其中對該基底材係為一芯板(Core),並以機械鑽孔形 成該些通孔。 102. 如申請專利範圍第100項所述之封裝件之製造方 法,其中該基底材係為一二氟化銨樹脂(Ammonium Bifluoride,ABF)膜材,並以雷射鑽孔方式形成該些通孔。 103. 如申請專利範圍第100項所述之封裝件之製造方 法,其中所形成之該圖案化金屬層更包括至少一晶片墊 (Die pad)。 104. 如申請專利範圍第103項所述之製造方法,其中 形成該圖案化介電層於該圖案化金屬層上方後,至少該些 晶片墊之一被該圖案化介電層部分或完全覆蓋。 105. 如申請專利範圍第103項所述之製造方法,其中 形成該圖案化介電層於該圖案化金屬層上方後,至少該些 第一接點被該圖案化介電層部分或完全覆蓋。 106. 如申請專利範圍第100項所述封裝件之製造方 法,其中形成之該圖案化介電層更包括形成至少一槽狀開 口(Slot opening),可暴露出該些第二接點。 107. 如申請專利範圍第103項所述之製造方法,其中 48 201041105 形*面處理層至少覆蓋該些晶片墊的任一者 或多者之表面及侧壁。 108.如申請專利籍衝 彳祀圍第1〇〇項所述之製造方法,更包 括形成一苐二表面處理思 处里層’至少覆蓋該些第一接點的任一 者或多者之表面。 109.如申請專利範圍第1〇8項所述之製造方法,其中 係k用鎳/金金、锡及其合金、或銀做為該第一和該第二 表面處理層之材料。 ❹
    no.如U利範圍第刚項所述封裝件之製造方 法,更包括形成複數條銲線電性連接該晶粒之 一主動表面 和該些第二接點。 第刚項所述封裝件之製造方 法’更包括填充-導體材料於該些通孔,且該導體材料係 與該些第一接點電性連接。 112.如申請專利範圍第1〇〇項所述封裝件之製造方 法,其中係選用防銲綠漆(soldermask,SM)、液晶聚合物 (liquid crystal polyester,Lcp)、或聚丙烯(p〇lypr〇pylene, PP)作為該圖案化介電層之材料。 、113.如申請專利範圍第100項所述封裝件之製造方 法所製成之該基板係具有一厚度約40μπ1〜130μ1η。 49
TW098124118A 2009-05-13 2009-07-16 Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package TW201041105A (en)

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US20100288541A1 (en) 2010-11-18
CN101887869B (zh) 2013-08-28
CN101887879B (zh) 2012-11-07
CN101887879A (zh) 2010-11-17
CN101887874A (zh) 2010-11-17
TW201041103A (en) 2010-11-16
CN101887875A (zh) 2010-11-17
CN101887875B (zh) 2013-02-20
CN101887874B (zh) 2012-01-25
TWI569394B (zh) 2017-02-01
TWI379394B (en) 2012-12-11
TW201041106A (en) 2010-11-16
US8399776B2 (en) 2013-03-19
CN101887869A (zh) 2010-11-17

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