CN101887875B - 单层金属层基板结构、应用之封装件结构及其制造方法 - Google Patents

单层金属层基板结构、应用之封装件结构及其制造方法 Download PDF

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CN101887875B
CN101887875B CN2009101704294A CN200910170429A CN101887875B CN 101887875 B CN101887875 B CN 101887875B CN 2009101704294 A CN2009101704294 A CN 2009101704294A CN 200910170429 A CN200910170429 A CN 200910170429A CN 101887875 B CN101887875 B CN 101887875B
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layer
pattern
dielectric layer
substrate
paper tinsel
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CN101887875A (zh
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黄士辅
苏洹漳
陈嘉成
李达钧
陈光雄
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种单层金属层基板结构，至少包括一图案化金属箔层(patterned metal foil)和一图案化介电层(patterned dielectric layer)。其中，部分图案化金属箔层的下表面形成下方对外电性连接的数个第一接点；而位于图案化金属箔层上方的图案化介电层至少暴露出图案化金属箔层的部分上表面，以形成上方对外电性连接的数个第二接点，且部分图案化介电层配置于基板的一切割道的位置。再者，于第二接点的任一或多者的表面上可更形成一第一表面处理层。应用此基板结构于一封装件时，所设置的晶粒与第二接点电性连接，且和图案化介电层位于图案化金属箔层的同一侧，且经过单元切割后所形成的封装件结构，胶体、图案化介电层与图案化金属箔层的侧边为一共平面。

Description

单层金属层基板结构、应用之封装件结构及其制造方法
技术领域
本发明是有关于一种基板结构、应用之封装件结构及其制造方法，且特别是有关于一种单层金属层的基板及其封装件结构和基板的制造方法。
背景技术
集成电路(IC)构装技术是电子产业中重要的一环，电子构装主要的功用在于保护、支撑、线路配置与制造出散热途径，并提供零件一个模块化与规格标准。在1990年代主要是利用球栅数组(Ball Grid Array，BGA)的封装方式进行电子构装，其优点为散热性佳与电性好、接脚数可以大量增加，可有效缩小封装体面积。
然而，随着全球个人计算机、消费性电子产品及通讯产品不断要求轻薄短小更要具备高效能的趋势下，芯片所要求的电气特性不但要愈好，整体体积要愈小，但I/O端口的数目却是往上提高。随着I/O数量增加、集成化线路间距缩小，要想在BGA基板上高效率地布置走线变得困难，例如在点18工艺(线宽0.18μm)或是高速(如800MHz以上)的IC设计上，有大幅增加I/O密度的趋势。因此开发出具有高I/O、细微的线路间距、和优良电性的载板一直是各载板厂争相努力的目标。除了这些需求，下游产品系统整合化的要求将日趋明显，因此多芯片模块(Multi-chipModule，MCM)工艺对MCM载板的需求也大幅提高。而快速增加的微电子系统需求(特别是关于系统大小和芯片整合增益部分)也更加速了芯片级尺寸封装(ChipScale Packaging，CSP)技术的采用。
随着芯片级尺寸封装(CSP)技术的成熟，追求性能与成本的系统型半导体封装方式-系统封装(System in Package，SiP)也成为封装技术的主流，主要是因为产品的尺寸越来越小、功能越趋繁多，必须应用SiP技术以满足市场的需求。系统封装SiP包括了将芯片(chip)或是被动组件(Passive Components)或是其它模块进行构装。系统封装也包括了不同技术如PiP(Package in Package)、PoP(Package on Package)、平面型的多芯片模块封装、或是为节省面积将不同功能芯片堆栈(Stack)起来的3D堆栈封装，这些都属于系统封装(SiP)技术的发展范畴，该用何种型态封装也视应用需求而有所差异。因此SiP的定义十分广泛。在系统封装(SiP)技术中，所使用的接合技术也有很多种，例如是打线连接(Wire bonding)、覆晶式(Flip Chip)接合和使用多种接合技术(Hybrid-type)等等。
以系统封装(System in Package)裸晶为例，它可将不同数字或模拟功能的裸晶，以凸块(bump)或打线(wire bond)方式连结于芯片载板上，该载板中已有部分内埋被动组件或线路设计，此具有电性功能的载板，称为整合性基板(Integrated Substrate)或功能性基板(Functional Substrate)。请参照图1A～1F，其绘示一种传统整合性基板的工艺示意图。首先，提供一铜箔基板(copper clad laminate，CCL)，是在一中心层(core)102的上下表面各形成第一导电层103和第二导电层104，导电层的材料例如是金属铜，如图1A所示。接着，对铜箔基板进行钻孔，形成孔洞106，接着整体镀上铜层107，其铜层107形成于第一导电层103和第二导电层104上方，和孔洞内壁，如图1B、1C所示。之后，对于中心层102上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形。如图1D所示，在中心层102上下两侧的金属铜层上分别形成(ex：曝光显影)图案化干膜108，再如图1E所示对金属铜层进行蚀刻，最后如图1F所示去除图案化干膜108，完成导线(metal traces)的制作。之后可以再进行后续工艺，例如印制上防焊绿漆(solder mask，SM)并对绿漆曝光/显影而暴露出所需的导线表面，再对导线表面进行处理如镀上镍/金(Ni/Au)，而完成最后产品。
另外，也有更高阶的整合性基板在工艺中是将通孔部份直接镀满导电材料(如金属铜)，再对于中心层上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形，如图2所示，其为另一种传统整合性基板的示意图。然而，将通孔镀满的技术较为复杂，也需较长时间镀制，且金属铜层115、116、117厚度控制不易(特别是金属铜层117的部份)。又图1F和图2所示的基板结构主要是有2层导电铜层分别形成于中心层102/112的上下两侧，因此又习称为”2层基板”。
当电子产品的体积日趋缩小，所采用的基板结构的体积和线路间距也必须随的减小。然而，在目前现有的基板结构和工艺技术能力下，不论是如图1F或图2所示的基板态样，要使基板再薄化和线路间距再缩小的可能性很小，不利于应用在小型尺寸的电子产品上。再者，对于定位在较低市场价格的小型电子产品，除了尺寸和性能，其基板的制造成本也是必须考虑的重要因素之一。因此，如何开发出新颖的薄型整合性基板，不但工艺快速简单又适合量产，并可兼具低制造成本和高产品良率的优点，以符合应用电子产品对于尺寸、外型轻薄化和价格的需求，实为相关业者努力的一大重要目标。
发明内容
本发明是有关于一种单层金属层基板及应用其的封装件结构和基板的制造方法。主要是应用单层图案化金属箔层和一图案化介电层形成两层结构的基板。所形成的基板结构整体厚度大幅降低，且工艺简单快速，适合量产，亦可降低制造成本但保有高产品良率，符合市场产品轻薄化和低成本的需求。
根据本发明，提出一种单层金属层基板，包括一图案化金属箔层(patterned metalfoil)、一图案化介电层(patterned dielectric layer)和一第一表面处理层(first surfacefinish layer)。其中，部分图案化金属箔层的下表面形成下方对外电性连接的数个第一接点；而位于图案化金属箔层上方的图案化介电层至少暴露出图案化金属箔层的部分上表面，以形成上方对外电性连接的数个第二接点，且部分图案化介电层配置于基板的一切割道的位置。第一表面处理层则位于该些第二接点的任一或多者的表面上。
根据本发明，提出一种封装件结构，包括：上述的基板结构、至少一晶粒(die)与第二接点电性连接，以及配置于图案化介电层上方的一胶体(Moldingcompound)。其中，晶粒与图案化介电层均位于图案化金属箔层上表面的同一侧；胶体并覆盖图案化介电层、图案化金属箔层和晶粒。其中，胶体、图案化介电层与图案化金属箔层的侧边为一共平面。
根据本发明，提出一种单层金属层基板的制造方法。首先，提供一载板(carrier)，且载板至少形成有一金属箔膜(metal foil)，其中金属箔膜具有一第一表面和一第二表面，且该第二表面与载板接合。之后，在金属箔膜的该第一表面上方形成一图案化介电层，图案化介电层形成有数个开口以暴露出金属箔膜的部分第一表面，以形成上方对外电性连接的数个第二接点，且部分图案化介电层延伸至基板的一切割道的位置。接着，将金属箔膜和图案化介电层所形成的结构体自载板上移除，并反转并重新设置结构体，使图案化介电层设置于载体上。然后，图案化金属箔膜以形成一图案化金属箔层，其中金属箔膜的部分第二表面形成下方对外电性连接的数个第一接点。最后，移除载板。另外，可在形成图案化介电层的步骤后、或是形成图案化金属箔层的步骤后，形成第一表面处理层于该些第二接点的任一或多者的表面上。在一较佳实施例中，亦更可于第一接点的任一或多者的表面处形成一第二表面处理层。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下：
附图说明
图1A～1F绘示一种传统整合性基板的工艺示意图。
图2为另一种传统整合性基板的示意图。
图3A～3G绘示依照本发明第一实施例制造单层金属层基板的方法流程图。
图4A～4F绘示依照本发明第二实施例制造单层金属层基板的方法流程图。
图5是绘示应用本发明第一、二实施例制作的基板的封装件结构示意图。
图6A绘示本发明第三实施例的单层金属层基板的示意图。
图6B是绘示应用本发明第三实施例的图6A基板的封装件示意图。
主要组件符号说明
102：中心层
103：第一导电层
104：第二导电层
106：孔洞
107、115、116、117：铜层
108：图案化干膜
20：载板
201、202：金属箔膜
201’、202’：图案化金属箔层
2013：第二接点
2015：第一接点
2017：芯片垫
37：切割道
301、302：图案化介电层
301a、301b、302a、302b：开口
307a、307b、308a、308b：第一表面处理层
309a、309b：第二表面处理层
41、42、43、44、45、46：结构体
51、52：基板结构
522：芯片容置区域
61、62封装件结构
601黏性物质
602晶粒
605a、605b焊线
607胶体
d1、d2间距
具体实施方式
本发明提出一种单层金属层基板及应用其的封装件结构和基板的制造方法，主要是应用单层图案化金属箔层(patterned metal foil)和一图案化介电层(patterneddielectric layer)形成两层结构的基板。其中图案化金属箔层具有一上表面和一下表面，且部分图案化金属箔层的下表面形成下方对外电性连接的数个第一接点，而位于图案化金属箔层上的图案化介电层至少暴露出图案化金属箔层的部分上表面以形成上方对外电性连接的数个第二接点(例如焊垫，bonding pads)。应用此基板于一封装件结构时，晶粒与图案化介电层均位于图案化金属箔层的同一侧。
相较于如图1F和图2所示的传统基板结构，本发明所提出的基板结构及应用此基板的封装件其整体厚度大为降低，轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出的基板结构制法应用一载板(carrier)完成，不但工艺快速简单、适合量产，亦可降低制造成本，所制作的基板结构及应用此基板的封装件亦具有高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。特别是对于市场价格较低的小型电子产品，更是具有市场竞争力。
以下根据本发明提出实施例，以详细说明本发明的基板结构及应用之封装件的制造方法。然而，实施例中所提出的基板结构仅为举例说明之用，并非作为限缩本发明保护范围之用。应用时可依实际条件的需求对基板的结构态样稍作修改。再者，实施例的图标仅绘示本发明技术的相关组件，省略不必要的组件，以清楚显示本发明的技术特点。
第一实施例
请参照图3A～3G，其绘示依照本发明第一实施例制造单层金属层基板的方法流程图。首先，如图3A所示，提供一载板(carrier)20，且载板20的上下表面皆具有一金属箔膜(metal foil)201、202。每一金属箔膜201/202具有一第一表面和一第二表面，以金属箔膜201为例，其具有第一表面201a和与载板20接触的第二表面201b。
接着，如图3B所示，在金属箔膜201、202的上表面处各形成一图案化介电层(patterned dielectric layer)301、302，图案化介电层301形成有数个开口301a、301b，以暴露出金属箔膜201的部分第一表面201a，且图案化介电层301部分延伸至未来进行单元切割时基板的一切割道的位置，如图中箭号37所示。同样的，图案化介电层302形成有数个开口302a、302b，以暴露出金属箔膜202的部分第一表面201a，且图案化介电层302亦部分延伸至未来进行单元切割时基板的一切割道37的位置。其中，图案化介电层301、302的材料例如是防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、或聚丙烯(polypropylene，PP)等，但本发明不限于此。
之后，将由金属箔膜201和图案化介电层301所形成的结构体41自载板20上移除，并反转和重新设置结构体41，使图案化介电层301设置于载体20上，如图3C所示。同样的，位于载板20另一侧由金属箔膜202和图案化介电层302所形成的结构体42亦自载板20上移除，并反转和重新设置，使图案化介电层302设置于载体20上。
接着，如图3D所示，对金属箔膜201、202进行图案化，以分别形成图案化金属箔层201’、202’。其中，形成图案化金属箔层201’、202’的步骤例如是：分别形成一干膜(未显示)于金属箔膜201、202上，并进行曝光和显影以图案化干膜，根据干膜的图案对金属箔膜201、202进行蚀刻完成影像转移，以形成图案化金属箔层201’、202’，完成影像转移后移除图案化干膜。
之后，可对于基板应用时的接点处再进行表面处理，以提升接点的电性和增加电性连接时连接导线或球体的附着性。
如图3E所示，将由图案化金属箔层201’和图案化介电层301所形成的结构体43自载板20上移除并反转设置，使图案化金属箔层201’设置于载体20上(即原先图3A中的金属箔膜201的第二表面201b现与载板20接触)。同样的，将包括图案化金属箔层202’和图案化介电层302的结构体44自载板20上移除并反转设置，使图案化金属箔层202’设置于载体20上。
接着，如图3F所示，在图案化金属箔层201’裸露于图案化介电层301外的任一或多个表面上，即图案化介电层301的开口301a、301b处，形成第一表面处理层307a、307b。同样的，在图案化金属箔层202’裸露于图案化介电层302外的任一或多个表面上，即图案化介电层302的开口302a、302b处，形成第一表面处理层308a、308b。之后，将两组基板结构自载板20上移除，完成本发明一实施例的基板制作。
以自载板20上侧移除的基板结构51为例，如图3G所示，位于图案化金属箔层201’上方的图案化介电层301具有开口301a、301b以暴露出图案化金属箔层201’的部分上表面(即原先图3A所示的金属箔膜201的第一表面201a)，而形成基板上方对外电性连接的数个第二接点2013，例如某些应用例中的焊垫(bonding pads)；在任一或多个第二接点2013的表面上可更形成第一表面处理层307a、307b。在实际应用时，图案化介电层301、302例如包括至少一槽状开口(Slot opening)，以暴露出该些第二接点2013。而部分图案化金属箔层201’的下表面(即原先图3A所示的金属箔膜201的第二表面201b)形成下方对外电性连接的数个第一接点2015，而第一接点2015的任一或多个表面可更包括一第二表面处理层309a、309b，以与一外部电路板电性连接，例如在应用例中可涂布上锡膏或设置锡球作为锡球垫(ballpads)，或是使用与第二接点2013表面形成第一表面处理层相同的方式和材料以形成第二表面处理层309a、309b。其中，第一表面处理层307a、307b、308a、308b或/和第二表面处理层309a、309b的材料例如是包括镍/金、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、有机保焊剂(OSP；Organic Solderability P reservative)等，本发明对此并不多作限制。再者，如图3G所示的基板结构51，分别位于图案化金属箔层201’的下表面和上表面的第一接点2015、第二接点2013，其位置相对应。
另外，于一应用例中(如图3G所示)，在第二接点2013上所形成的第一表面处理层307a、307b亦可分别与图案化介电层301的侧壁相隔一间距d1、d2，且该些间距d1、d2可以相同或相异，视应用时的实际图形而定。当然，第一表面处理层307a、307b也可紧邻图案化介电层301，本发明对此并不多作限制。
第二实施例
请参照图4A～4F，其绘示依照本发明第二实施例制造单层金属层基板的方法流程图。第二实施例和第一实施例不同的是进行表面处理的步骤顺序略微变更，但可制作出相同的基板结构。其中，第二实施例和第一实施例相同的组件沿用相同标号，以利说明。
首先，如图4A所示，提供具有金属箔膜201、202的一载板20。接着，如图4B所示，在金属箔膜201、202的上表面处各形成一图案化介电层(patterneddielectric layer)301、302。图案化介电层301形成有数个开口301a、301b，以暴露出金属箔膜201的部分第一表面201a，且图案化介电层301部分延伸至未来进行单元切割时基板的一切割道37的位置。同样的，图案化介电层302形成有数个开口302a、302b，以暴露出金属箔膜202的部分第一表面201a，且图案化介电层302部分延伸至未来进行单元切割时基板的一切割道37的位置。
之后，先进行接点的表面处理。如图4C所示，在金属箔膜201裸露于图案化介电层301外的任一或多个表面上，即图案化介电层301的开口301a、301b处，形成第一表面处理层307a、307b。同样的，在金属箔膜202裸露于图案化介电层302外的任一或多个表面上，即图案化介电层302的开口302a、302b处，形成第一表面处理层308a、308b。其中，第一表面处理层307a、307b、308a、308b的材料例如是镍/金、金、锡及其合金(如锡铅合金)、银、或OSP等，本发明对此并不多作限制。
接着，如图4D所示，将由金属箔膜201和图案化介电层301所形成的结构体45自载板20上移除，并反转和重新设置结构体45，使图案化介电层301设置于载体20上。同样的，位于载板20另一侧由金属箔膜202和图案化介电层302所形成的结构体46亦自载板20上移除，并反转和重新设置，使图案化介电层302设置于载体20上。
之后，如图3E所示，对金属箔膜201、202进行图案化，以分别形成图案化金属箔层201’、202’。其中，可利用干膜形成、图案化干膜(曝光和显影)、和根据干膜图案进行蚀刻等步骤完成影像转移，以形成图案化金属箔层201’、202’。
最后，将两组基板结构自载板20上移除，完成如图4F所示的基板51的制作。当然，第一接点2015的任一或多个表面可更包括一第二表面处理层309a、309b，以与一外部电路板电性连接，其中，第一表面处理层307a、307b、308a、308b或/和第二表面处理层309a、309b的材料例如是包括镍/金、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、OSP等，本发明对此并不多作限制。根据本发明第二实施例的方式所制作的基板，如图4F所示，与第一实施例所制作的基板具有相同结构，请参考图3G及其相关说明，在此不再赘述。
图5绘示应用本发明第一、二实施例制作的基板的封装件结构示意图。如图5的封装件结构61所示，制作时应用一黏性物质(例如环氧树脂)601将一晶粒602黏附在图案化介电层301上方，并且经由焊线605a、605b电性连接晶粒602的一主动表面与第二接点2013处的第一表面处理层307a、307b。其中，晶粒602与图案化介电层301均位于图案化金属箔层201’的同一侧。之后，再形成一胶体(MoldingCompound)607于图案化介电层301的上方，以密封图案化介电层301、图案化金属箔层201’、晶粒602和焊线605a、605b。其中，焊线605a、605b的材质包括金、银、铜、铝及其合金；胶体607的材料一般为绝缘的封装材料，常见的例如是环氧树脂。而图案化金属箔层201’的下表面处的第一接点2015可对外电性连接，例如是以第二表面处理层309a、309b与一外部电路板电性连接。再者，经过单元切割后，每一封装件结构的胶体607、图案化介电层301与图案化金属箔层201’的侧边为一共平面。
根据上述，在第一、二实施例中所制作的基板结构51，如图3G和4F所示，主要包括了单层图案化金属箔层(201’/202’，作为导线层)和单层图案化介电层(301/302)，相较于其它直接使用已成型的钉架(Leadframe)的传统制作基板方式，本发明利用载板而层层制作出基板的方式，包括如前述在载板上形成金属层、形成图案化导电层、对金属层进行图案化等等多项步骤，本案所制作出的图案化导电层的厚度可小于传统使用Leadframe作为导电层的厚度，所完成的基板结构51厚度减少很多。若是相较于如图1F或图2所示的传统的基板结构，整体厚度也是大幅降低。依照本发明所制作的基板结构51，其厚度仅约40μm～130μm，均非传统基板结构可以比拟。因此，依照本发明所制作与提出的基板结构，其轻薄的外型十分适合小尺寸应用产品的需求。另外，相较于传统工艺，上述实施例所提出的工艺更为简易迅速，并可制作出细微的线路间距。
再者，虽然在上述实施例中为提高生产力，在流程中于载板20的两侧同时制作出两组基板结构作说明，但本发明并不受限于此，实际应用时可视操作状况而进行调整，例如在图3A～3G或图4A～4F中仅在载板20的单一侧进行工艺亦可形成如实施例图3G和4F所示的基板结构51，因此本发明对此并不多作限制。
第三实施例
除了第一、二实施例中所制作的基板结构51(图3G和4F)，也可稍加变化上述工艺而制作出本发明其它态样的基板。请参照图6A，其绘示本发明第三实施例的单层金属层基板的示意图。第一、三实施例中，相同组件沿用相同标号。
制作如图6A所示的基板结构52时，同样可应用如图3A～3G或图4A～4F所示的步骤进行基板制作，在此不再赘述。
第三实施例的图案化金属箔层201’除了第一接点2015和第二接点2013，还包括了至少一芯片垫(die pad)2017。因此在第三实施例中，图案化金属箔层201’包括了芯片垫2071、多个第一接点2015(如焊垫，可连接晶粒)和多个第二接点2013(对外接点，如锡球垫)。与第一、二实施例不同的是，在第三实施例中形成图案化介电层301(第3B、4B图)时，图案化介电层301更在对应芯片垫2017的位置形成一芯片容置区域(die-receiving area)522。如图6A所示，芯片容置区域522是完全暴露出芯片垫2017。
图6B是绘示应用本发明第三实施例的图6A基板的封装件示意图。如图6B的封装件结构62所示，制作时亦应用一黏性物质(例如环氧树脂)601将一晶粒602设置在芯片容置区域522内并黏附于图案化金属箔层201’的芯片垫2017上方，并且经由焊线605a、605b电性连接晶粒602的一主动表面与第二接点2013处的第一表面处理层307a、307b；之后，再形成一胶体607(如环氧树脂)于第一图案化介电层301上方，以密封图案化介电层301、图案化金属箔层201’、晶粒602和焊线605a、605b。再者，经过单元切割后，每一封装件结构的胶体607、图案化介电层301与图案化金属箔层201’的侧边亦为一共平面。单元化后，此封装件可利用第一接点2015的任一或多个表面上的第二表面处理层309a、309b以与一外部电路板电性连接。由于晶粒602是位于芯片容置区域522内且设置在图案化金属箔层201’的表面上，因此可再降低封装后的整体厚度。
同样的，对于图6A和图6B的基板结构而言，主要包括了单层图案化金属箔层(201’/202’，作为导线层)和单层图案化介电层(301/302)，相较于传统的基板结构，依照本发明所制作的基板结构52，其厚度很薄，且封装件整体厚度更为降低，如此轻薄的外型十分适合小尺寸应用产品的需求。
值得注意的是，虽然上述实施例中提出两种制法(第一、二实施例)、两种基板结构51、52和相关封装件61、62作举例说明，但其最终结构仍是依照实际应用条件而作相关调整，例如封装时晶粒连接可采用打线或覆晶方式连接，介电层图案、金属层图案、…等等，该些选择并不局限于上述图式所绘制的态样。
综上所述，根据本发明实施例所制作出的内埋式基板结构，其厚度范围约在40μm～130μm，相较于传统的基板结构，本发明所提出的基板厚度、及应用此基板的封装件的整体厚度都可大为下降，其轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出此基板结构及应用其的封装件的制造方法，其工艺不但快速简单又十分适合量产，兼具低制造成本和高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。因此，比起传统的基板结构，本发明所提出的基板结构及应用其的封装件更是适合应用于市场价格较低的小型电子产品，十分具有市场竞争力。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视后附的权利要求书所界定者为准。

Claims (19)

1.一种单层金属层基板，包括：
一图案化金属箔层，具有一上表面和一下表面，且部分该图案化金属箔层的该下表面形成下方对外电性连接的数个第一接点；
一图案化介电层，是位于该图案化金属箔层的上方，部分该图案化介电层配置于该基板的一切割道的位置，且该图案化介电层至少暴露出该图案化金属箔层的部分该上表面，以形成上方对外电性连接的数个第二接点；和
一第一表面处理层，位于所述第二接点的任一或多者的表面上。
2.如权利要求1所述的基板，包括一第二表面处理层，形成于所述第一接点的任一或多者的表面。
3.如权利要求2所述的基板，其中该第一与该第二表面处理层的材料包括镍金叠层、镍银叠层、金、锡及锡合金、银或有机保焊剂。
4.如权利要求1所述的基板，其中该图案化介电层的材料为防焊绿漆、液晶聚合物、或聚丙烯。
5.如权利要求1所述的基板，其厚度范围在40μm～130μm之间。
6.一种具有单层金属层基板的封装件结构，包括：
一单层金属层基板，该基板包含一图案化金属箔层、位于该图案化金属箔层的上方的一图案化介电层和一第一表面处理层，其中该图案化金属箔层具有一上表面和一下表面，且部分该图案化金属箔层的该下表面形成下方对外电性连接的数个第一接点，而该图案化介电层至少暴露出该图案化金属箔层的部分该上表面，以形成上方对外电性连接的数个第二接点，该第一表面处理层则位于所述第二接点的任一或多者的表面上；
至少一晶粒与所述第二接点电性连接，且该晶粒与该图案化介电层均位于该图案化金属箔层的该上表面的一侧；以及
一胶体，配置于该图案化介电层上方，并覆盖该图案化介电层、该图案化金属箔层、和该晶粒，其中该胶体、该图案化介电层与该图案化金属箔层的侧边齐平。
7.如权利要求6所述的封装件结构，其中该图案化介电层包括至少一槽状开口，可暴露出所述第二接点。
8.如权利要求6所述的封装件结构，包括一第二表面处理层，形成于所述第一接点的任一或多者的表面。
9.如权利要求8所述的封装件结构，其中该第一与该第二表面处理层的材料包括镍金叠层、镍银叠层、金、锡及锡合金、银或有机保焊剂。
10.如权利要求6所述的封装件结构，其中该图案化介电层的材料为防焊绿漆、液晶聚合物、或聚丙烯。
11.如权利要求6所述的封装件结构，其厚度范围在40μm～130μm之间。
12.如权利要求6所述的封装件结构，包括数个条焊线电性连接该晶粒的一主动表面和所述第二接点。
13.如权利要求12所述的封装件结构，其中所述焊线的材质包括金、银、铜、铝及其合金。
14.一种单层金属层基板的制造方法，包括：
提供一载板，且该载板至少形成有一金属箔膜，其中该金属箔膜具有一第一表面和一第二表面，且该第二表面与载板接合；
在该金属箔膜的该第一表面上方形成一图案化介电层，且部分该图案化介电层延伸至该基板的一切割道的位置，该图案化介电层形成有数个开口以暴露出该金属箔膜的部分该第一表面，以形成上方对外电性连接的数个第二接点；
将该金属箔膜和该图案化介电层所形成的一结构体自该载板上移除，并反转和重新设置该结构体，使该图案化介电层设置于该载体上；
图案化该金属箔膜，以形成一图案化金属箔层，其中该金属箔膜的部分该第二表面形成下方对外电性连接的数个第一接点；和
移除该载板。
15.如权利要求14所述基板的制造方法，包括：形成一第一表面处理层于所述第二接点的任一或多者的表面上的步骤。
16.如权利要求15所述基板的制造方法，其中在形成该图案化介电层的步骤后，对该图案化介电层暴露出该金属箔膜的部分该第一表面而形成所述第二接点处，形成该第一表面处理层。
17.如权利要求15所述基板的制造方法，其中在形成该图案化金属箔层后，将该图案化金属箔层和该图案化介电层所形成的一结构体自该载板上移除，并反转设置该结构体，使该图案化金属箔层的该第一表面设置于该载体上；
在所述第二接点的任一或多者的表面处形成该第一表面处理层；和
移除该载板。
18.如权利要求15所述的制造方法，其中包括于所述第一接点的任一或多者的表面处形成一第二表面处理层。
19.如权利要求14所述基板的制造方法，其中在提供的该载板的上下两侧各形成一金属箔膜，并接着在该载板的上下两侧同时进行形成该图案化介电层、反转并重新设置该结构体于该载板、形成该图案化金属箔层和移除该载板，以同时形成两组基板结构。
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