CN104701191A - 生产制造载体的系统和方法 - Google Patents

生产制造载体的系统和方法 Download PDF

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Publication number
CN104701191A
CN104701191A CN201410858127.7A CN201410858127A CN104701191A CN 104701191 A CN104701191 A CN 104701191A CN 201410858127 A CN201410858127 A CN 201410858127A CN 104701191 A CN104701191 A CN 104701191A
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China
Prior art keywords
methods according
carrying part
basal surface
current
repetitive
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CN201410858127.7A
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English (en)
Inventor
张家骅
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Enablink Technologies Ltd
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Enablink Technologies Ltd
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Publication of CN104701191A publication Critical patent/CN104701191A/zh
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

一种制造BGA载体的方法，该方法包括将导电部分和模制的介电部分组合，介电部分具有顶表面、底表面和内表面，内表面与所述预表面和所述底表面相交，内表面形成腔，用于容纳半导体管芯；选择性地将半导体管芯接合至导电部分的顶表面上；选择性地蚀刻导电部分的一部分；并将焊料抗蚀剂施加到导电部分的底表面上。

Description

生产制造载体的系统和方法
相关申请
本申请要求2014年12月06日提交的美国专利申请61/912737的优先权，要求此较早提交的申请的优先权并且通过引用将该较早提交的申请的全部内容并入于此。
发明领域
本发明一般涉及集成电路封装，以及更具体地涉及用于制造管芯向下倒装芯片(down flip)载体的系统和方法。
背景技术
存在各种方法用于形成制造载体。例如，可通过借助于粘合剂层制造使用金属箔层压的聚酰亚胺载体来制造，接着图案化该金属和选择性电镀金属部分，接着将聚酰亚胺载体层压到厚金属片上以形成管芯容腔(receptacle)，其中厚金属片上有与聚酰亚胺载体的开口对准的部分蚀刻腔。因为聚酰亚胺是相对昂贵的，所以制造这样的载体不是经济有效的方法。此外，聚酰亚胺是相对薄的，并且为了建立足够深的容腔以容纳半导体器件，需要具有部分蚀刻腔的相对厚的金属片，并因此需要附加的蚀刻步骤。
发明内容
本发明的目的是提供一种新颖的管芯向下倒装芯片(die down flip)载体及其制造方法，其消除和减轻至少一种现有技术的上述确定的缺点。
这些连同其它方面和优点随后将是显而易见，存在于更全面地在下文中描述并要求保护的结构和操作上的细节，参照的附图构成本发明的一部分，其中相似的标号通篇指代相似的部件。
附图说明
图1示出根据一个实施方式的球栅阵列载体的示图；
图2示出根据一个实施方式的球栅载体制造方法的流程图；
图3示出根据一个实施方式的载体的板；
图4，包括图4(a)-(c)，示出了根据一个实施方式的板的重复单元；
图5，包括图5(a)-(c)，示出了根据一个实施方式的板的重复单元；
图6示出了接合到载体的芯片管芯的截面图；
图7，包括图7(a)-(c)，示出了根据一个实施方式的板的重复单元；
图8，包括图8(a)-(c)，示出了根据一个实施方式的板的重复单元；
图9，包括图9(a)-(c)，示出了根据一个实施方式的板的重复单元；
图10，包括图10(a)-(c)，示出了根据一个实施方式的板的重复单元；
图11，包括图11(a)-(c)，示出了根据一个实施方式的板的重复单元；
图12，包括图12(a)-(c)，示出了根据一个实施方式的板的重复单元；
图13，包括图13(a)-(c)，示出了根据一个实施方式的板的重复单元；
图14，包括图14(a)-(c)，示出了根据一个实施方式的板的重复单元；
图15，包括图15(a)-(c)，示出了根据一个实施方式的板的重复单元；
图16，包括图16(a)-(c)，示出了根据一个实施方式的板的重复单元；
图17，包括图17(a)-(c)，示出了根据一个实施方式的板的重复单元；
图18，包括图18(a)-(c)，示出了根据一个实施方式的板的重复单元；
图19，包括图19(a)-(c)，示出了根据一个实施方式的板的重复单元；
图20，包括图20(a)-(c)，示出了根据一个实施方式的板的重复单元；
图21示出了根据一个实施方法的板的重复单元；
图22，包括图22(a)-(c)，示出了根据一个实施方式的板的重复单元；
图23，包括图23(a)-(c)，示出了根据一个实施方式的板的重复单元；
图24，包括图24(a)-(c)，示出了根据一个实施方式的板的重复单元；
图25示出了根据一个实施方法的叠层载体的截面图；
图26，包括图26(a)-(c)，示出了根据一个实施方式的板的重复单元；
图27，包括图27(a)-(c)，示出了根据一个实施方式的板的重复单元；
图28，包括图28(a)-(c)，示出了根据一个实施方式的板的重复单元；以及
图29，包括图29(a)-(c)，示出了根据一个实施方式的板的重复单元。
发明内容
图1示出根据一个实施方式的管芯向下倒装芯片(down flip)载体125的底视图。现在参考图2，一种制造管芯向下倒装芯片载体的方法，通常表示为200。应当理解的是，方法200可以被改变，而不必精确地如在此所述执行，并且变化在本领域技术人员所熟知的范围内。
在一些实施方式中，可以形成预模制板以制造一个或多个载体125。现在参考图3，示出预模制板101的顶视图。虽然在此示例实施方式中是矩形，但是能被本领域技术人员所理解的是，该板101可采取各种形状，如条状，圆形晶圆和其他。板101包含许多重复单元125’，所述重复单元125’在本实施方式中排列成矩阵的形式，每个重复单元125’是不完整的载体125。
方法200开始，在210，介电部分与导电部分结合。参考图4，可以使用各种技术将可以由如铜或铬的金属制成的导电部分10与介电部分120相结合。图4(a)示出了重复单元125’的顶视图，图4(b)示出了重复单元125’的底视图，以及图4(c)示出了具有顶表面135和底表面140的重复单元125’的横截面。
介电部分120可以由聚合模制化合物组成，聚合模制化合物基于，例如，诸如环氧树脂的粘合材料并填充如二氧化硅或碳化硅的无机填料，或者它可以是模制成适合于制造管芯向下倒装芯片载体的预定形状的任何合适的塑料化合物。介电部分120可通过模制处理形成为任何预定的厚度。介电部分120的示例厚度为大约为0.1毫米。介电部分120可以成形为在中间形成腔或容腔(receptacle)110，以使导电部分105在腔110处从重复单元125’的顶表面135和底表面140两者露出。
腔110可通过介电部分120的内表面111形成，其相交于底表面140和顶表面135，形成了顶部入口112和底部入口113。在一些实施方式中，诸如图3中所示的实施方式，内表面111可以基本上垂直于顶表面和底表面。在其他实施方式中，内表面111可以以不同于正交，即非正交的方式成角度，使得顶部入口112和底部入口113可以具有不同的周向尺寸。例如，内表面111相对于底表面135的角度可以大于90度，使底部入口113相对于顶部入口112具有较小的周向尺寸。在这样的示例中，内表面111将以小于90度的角度相交于顶表面135。内表面111可以以任何预定的方式设置，以允许形成由内表面111与顶表面和/或底表面的相交限定的任何预定周向形状的入口。周向形状的例子包括正方形，矩形，三角形，圆形或不规则形状。此外，通过以允许这样不同的形状的方式形成内表面111，顶部入口112可以具有与底部入口113不同的周向形状。
在一些实施方式中，如图4所示，导电部分105可以是如铜箔的金属箔。箔的厚度可变化，例如18微米，10微米或更薄。在进一步实施方式中，形成介电部分120的模制化合物，可以通过暴露于高温被模制，以降低粘度，从而允许通过模制工具模制模制化合物。在进一步实施方式中，由于介电部分120可以直接粘结到箔，而不需更借助于介电部分120和箔之间的附加粘合剂层，介电部分120可以直接与箔相结合。例如，在变形中，包含在模制材料中的粘结材料可以促进介电部分120和箔的直接粘结。
现在参考图5和图2，在220，通过本领域中已知的方法，例如热压缩接合，热声波接合，焊料回流，各向异性导电接合以及本领域技术人员已知的其他方法将例如倒装芯片管芯122的半导体芯片接合到铜箔上。在一个实施方式中，如图5所示，利用倒装芯片连接123。图5(a)表示重复单元125’的顶视图，图5(b)表示重复单元125’的底视图，图5(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。
图6描绘了根据一个实施方式的横截面的倒装芯片连接123的特写，其中，用如焊料或银环氧树脂的导电粘结材料131将倒装芯片连接123附接到导电部分105的顶表面135。导电粘结材料131和该倒装芯片122之间是凸块132，它包括铜柱凸块，铜钉头(stud)凸块或本领域技术人员已知的其他部件。
继续参照方法200，在230填充管芯与导电部分之间的间隙。如图7所示，可以将底层填料(underfill)134插入到腔110没有被倒装芯片管芯122和倒装芯片连接123所占据的剩余空间的部分或全部中。在一些实施方式中，使用诸如液体分配的本领域已知的方法将包括非导电或绝缘材料(例如具有如SiO2的非常细的填料颗粒的液体环氧树脂)的底层填料提供到管芯122和导电部分105之间的腔110中。图7(a)表示重复单元125’的顶视图，图7(b)表示重复单元125’的底视图，图7(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。
再次参照图2所示的方法200，在240，在一些实施方式中，导电部分105的暴露的底表面140，即重复单元125’的底表面，可以如图8(b)和8(c)所示出的那样被选择性电镀，其中，所述选择性电镀在155处标示。金属电镀155可以选择性地沉积在导电部分105的至少一部分上，其在图示的例子中是金属箔。在一些实施方式中，电镀155可以被成形为形成球栅阵列(BGA)焊盘。图8(a)表示重复单元125’的顶视图，图8(b)表示重复单元125’的底视图，以及图8(c)表示具有顶表面135和底表面140的重复单元125’沿着线B-B的横截面。在一些变形中，为了进行选择性电镀，将可光成像的电镀抗蚀剂施加到重复单元125’的底表面上。随后将底表面140暴露于预定的或选择的图像图案。接着，将电镀抗蚀剂显影，以及指定的金属图案如在155处标示的被电镀。使用的金属可以是银，镍/金，镍/金/钯以及其它本领域技术人员已知的金属。最后，将电镀抗蚀剂剥离。
继续该方法200，在250中，至少一些导电部分105如图9所示被选择性地蚀刻掉。在一些实施方式中，预定图案蚀刻允许从倒装芯片连接123到BGA球焊盘163形成连接通路157。图9(a)表示重复单元125’的顶视图，图9(b)表示重复单元125’的底视图，以及图9(c)表示具有顶表面135和底表面140的重复单元125’沿着线B-B的横截面。
在一些实施方式中，为了按照预定图案对导电部105进行选择性地蚀刻，将可光成像的抗蚀剂施加到所述底表面140，以及曝光选择的图像图案。然后，抗蚀剂被显影并且由抗蚀剂限定的金属图案被保护，将不需要的金属部分暴露于化学蚀刻。最后，将底表面140上的抗蚀剂剥离。
在方法200的260处，可以使用常规方法按照预定的形状或图案将焊料抗蚀剂选择性地施加于底表面140。图10示出了在160处表示的施加到重复单元125’的底表面140的焊料抗蚀剂。在一些实施方式中，焊料抗蚀剂施加被成形，使得形成BGA焊盘163的所述导电部分的区域暴露在重复单元125’的底表面140，而蚀刻出的金属图案的其余部分，如连接通路被钝化。
在方法200的270处，可以使用助焊剂并随后回流而将焊料球197附接到露出的BGA焊盘163，例如如图11所示。
方法200的变化是可能的。在一些变形中，如图12所示，在210，板101的介电部分120可以通过例如层压的方式与耐高温带106或相似的材料进行结合。带106的一侧可以包括促进与所述介电部分120接合的粘合剂层。图12(a)表示重复单元125’的顶视图，图12(b)表示重复单元125’的底视图，以及图12(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。
如图13所示，继续所示实施例，将倒装芯片管芯122暂时接合到耐高温带106的粘合剂层。图13(a)表示重复单元125’的顶视图，图13(b)表示重复单元125’的底视图，以及图13(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。如图13(b)和13(c)所示，在一些实施方式中，可使用包括铜柱凸块、金钉头(stud)凸块或本领域技术人员已知的其他部件的倒装芯片连接123将管芯122附接到带106。在其他实施方式中，如图26所示，管芯122可以暂时直接接合至带106。在这样的实施方式中，管芯122可以包括引线接合焊盘124，其也可暂时接合到带106上。
继续所示实施例，以及如图14所示，随后可以施加底部填料134。图14(a)表示重复单元125’的顶视图，图14(b)表示重复单元125’的底视图，以及图14(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。具体地，可以将底部填料以类似于上面方法200的步骤230描述的方式施加到腔110。随后可以通过高温固化来固化分配的底部填料。在管芯122包括线接合焊盘124并且直接接合到带126的实施方式中，如图27所示，底部填料可以只施加到管芯122和内表面111之间的间隙。
在固化完成后，可以去除耐高温带106，如图15所示。例如，可以通过简单的剥离去除带106。
去除带106后，如图16所示单元125’的底表面140可被金属化或完全电镀，从而形成导电部分105并将导电部分105与介电部分120相结合。图16(a)表示重复单元125’的顶视图，图16(b)表示重复单元125’的底视图，以及图16(c)表示具有顶表面135和底表面140的重复单元125’沿虚线A-A的横截面。在一些实施方式中，可以通过金属化介电部分120的底表面140，连接123的暴露部分和底部填料134的底表面140来形成导电部分105。可以通过或者溅射金属籽晶(seed)层(例如铜或铬或钛)或者通过使用诸如铜的金属的浸渍金属电镀来实现金属化。在籽晶层或者浸渍电镀之后可以通过使用铜或类似金属的进一步电解电镀以达到所需的厚度。使用具有引线接合焊盘的管芯122的金属化的替代实施方式示于图28。
在重复单元125’被金属化后，可以先可选择地进行选择性电镀，然后选择性地蚀刻，然后通过选择性施加焊料抗蚀剂进行选择性地钝化，最后施加焊料，所有的步骤，例如可以按照上述描述中关于方法200的步骤240至270的方式实施。
在方法200的进一步变化中，板101的重复单元125’可以被模制以包括除了腔110之外的腔。例如，如图17所示，接触腔130可以包括在通过模制处理形成的介电部分120内。可根据任何所需的预定形状形成类似于腔110的接触腔130。在这个例子中，它们是梯形的横截面，在介电部分120的顶表面135上具有较大的入口。图17(a)表示重复单元125’的顶视图，图17(b)表示重复单元125’的底视图，以及图17(c)表示具有顶表面135和底表面140的重复单元125’沿着线A-A的横截面。
如图18中表示，接触腔130可填充有焊料117。图18(a)表示重复单元125’的顶视图，图18(b)表示重复单元125’的底视图，以及图18(c)表示重复单元125’沿虚线A-A的横截面，具有顶表面135和底表面140。
通过采用倒装芯片连接123将芯片接合到导电部分105，随后可以将倒装芯片管芯122附接到重复单元125’，如图19所示，并且例如，如关于方法200的步骤220所描述的。然后单元125’可以被底部填充，接着温度固化底部填料，可选择地金属电镀，导电部分选择性地蚀刻，焊料抗蚀剂和焊料球可以被施加，如图20至24示出的，以及上面关于方法200的步骤230至270所讨论的。包括具有引线接合焊盘的管芯的一个实施方式示于图29。
现在参照图25，示出了堆叠载体125的横截面。通过焊料190将载体125”粘结到其上的载体125”’。将焊料190选择性施加到125”’的BGA球焊盘，其被连接到在它下面的载体125”的焊料117的部分的一个端部，所述焊料117通过载体125”的一个或多个接触腔130的顶部入口而暴露。在另一端，焊料190被施加至在它上面的载体125”’的一个或多个暴露的BGA焊盘163，这样形成载体125”与125”’之间的接合。类似地，通过将焊料190施加至通过125”’的接触腔130露出的焊料117将载体125”’粘结到它上面的载体125””，，以便将其粘结到载体125””的暴露球焊盘。在变形中，导电环氧树脂可被用来代替焊料190以粘结两个载体125。进一步变形中，可以将焊料球施加到载体125的底表面140的焊料球焊盘。当下方的载体125的接触腔130填充有焊料117时，随后焊料球可与紧接其下的另一个载体125的焊料117焊接。在进一步的变形中，可使用该方法堆叠少于三个或多于三个载体125。
应当注意的是，虽然使用接触腔130的方法200的变形的上述讨论，是根据将金属箔用作导电部分105进行讨论的，但是在进一步的变形中，如上所述的带106和金属化，也可以用于形成具有接触腔的载体125，并相应地，可堆叠的载体。对于本领域技术人员其它变形现在将发生。
以上描述的实施例旨在是示例，以及可以由本领域技术人员对其进行改变和修改，而不偏离由所附权利要求书单独所限定的范围。例如，可以变化和组合讨论的方法、系统和实施例的全部或一部分。

Claims (28)

1.一种制造BGA载体的方法，所述方法包括：
组合导电部分和模制的介电部分，所述介电部分具有顶表面，底表面和内表面，所述内表面与所述顶表面和所述底表面相交，所述内表面形成用于容纳半导体管芯的腔；
选择性地将所述半导体管芯接合至所述导电部分的顶表面；
选择性地蚀刻所述导电部分的一部分；以及
将焊料抗蚀剂施加至所述导电部分的底表面。
2.根据权利要求1所述的方法，其中所述介电部分由聚合模制化合物模制。
3.根据权利要求2所述的方法，其中所述聚合模制化合物包括粘结材料。
4.根据权利要求2所述的方法，其中所述粘结材料包含填充有无机填料的环氧树脂。
5.根据权利要求4所述的方法，其中所述无机填料包括或者二氧化硅或碳化硅中至少一个或者塑料化合物中的一个。
6.根据权利要求1所述的方法，其中所述介电部分的内表面与所述顶表面和所述底表面正交相交。
7.根据权利要求1所述的方法，其中所述介电部分的内表面与所述顶表面和所述底表面非正交相交。
8.根据权利要求1所述的方法，其中所述腔的形状是或者正方形、矩形、三角形、圆形或者不规则形状中的一个。
9.根据权利要求1所述的方法，还包括：选择性地电镀所述导电部分的底表面的暴露部分。
10.根据权利要求9所述的方法，其中所述选择性地电镀被成形为形成BGA焊盘。
11.根据权利要求9所述的方法，其中所述选择性地电镀包括将可光成像的电镀抗蚀剂施加至所述导电部分的底表面，将所述可光成像电镀抗蚀剂暴露于图像图案，显影所述抗蚀剂，在所述电镀抗蚀剂的未暴露部分上沉积金属，并剥离所述电镀抗蚀剂。
12.根据权利要求11所述的方法，其中所述金属是或者银、镍/金或者钯中的一个。
13.根据权利要求9所述的方法，其中选择性地蚀刻步骤包括将可光成像抗蚀剂施加到所述导电部分的底表面，将可光成像抗蚀剂暴露于图像图案，显影所述抗蚀剂，并剥离所述抗蚀剂。
14.根据权利要求1所述的方法，其中按照预定的形状将焊料抗蚀剂选择性地施加到所述导电部分的底表面。
15.根据权利要求14所述的方法，其中所述预定形状是这样的：形成BGA焊盘的所述导电部分的区域被留下暴露在导电部分的底表面处。
16.根据权利要求15所述的方法，进一步包括使用助焊剂随后回流将焊料球附接到BGA焊盘，以及去除临时带。
17.根据权利要求15所述的方法，其中
选择性地将所述半导体管芯接合至所述导电部分的顶表面进一步包括：
将粘合剂层施加到所述介电部分的底表面；
将所述管芯临时接合到所述腔内的粘合剂层的顶表面；
在所述管芯、所述介电部分的内表面以及所述粘合剂层之间分配底部填料；以及
去除所述粘合剂层，并且其中
组合导电部分和模制的介电部分还包括：
金属化所述模制的介电部分的底表面以及所述底部填料的底表面，以形成所述导电部分。
18.根据权利要求17所述的方法，还包括和固化所述底部填料。
19.根据权利要求17所述的方法，其中所述粘合剂层包含或者热固性环氧树脂或者膜中的一个。
20.根据权利要求17所述的方法，还包括将散热器施加至所述粘合剂层。
21.根据权利要求17所述的方法，其中所述管芯的临时接合包括以下之一：用芯片连接附接所述管芯；以及将所述管芯直接附接到所述粘合剂层，将包括引线接合焊盘的管芯也暂时附接于所述粘合剂层。
22.根据权利要求17所述的方法，其中金属化包括溅射金属籽晶层和浸渍金属电镀中的一个。
23.根据权利要求22所述的方法，还包括金属化之后选择性地电镀所述导电部分的底表面。
24.根据权利要求10所述的方法，其中所述介电部分包括多个接触腔。
25.根据权利要求24所述的方法，进一步包括用焊料填充所述接触腔，每一个接触腔焊料与BGA焊盘中的一个电接触。
26.根据权利要求25所述的方法，进一步包括将通过所述介电部分的顶表面暴露的所述接触腔焊料连接至第二BGA载体的BGA焊盘以堆叠两个BGA载体。
27.根据权利要求1所述的方法，还包括：在所述管芯，所述介电部分的内表面和所述导电部分之间分配底部填料。
28.根据权利要求1所述的方法制造的BGA载体。
CN201410858127.7A 2013-12-06 2014-12-05 生产制造载体的系统和方法 Pending CN104701191A (zh)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0702404A2 (en) * 1994-09-14 1996-03-20 Nec Corporation Semiconductor device
JP2001274203A (ja) * 2000-03-24 2001-10-05 Hitachi Cable Ltd ２メタル基板とｂｇａ構造
CN1359150A (zh) * 2002-01-15 2002-07-17 威盛电子股份有限公司 球脚阵列封装基板及其制造方法
US6448506B1 (en) * 2000-12-28 2002-09-10 Amkor Technology, Inc. Semiconductor package and circuit board for making the package
JP2003037244A (ja) * 2001-07-24 2003-02-07 Hitachi Cable Ltd 半導体装置用テープキャリア及びそれを用いた半導体装置
US6734535B1 (en) * 1999-05-14 2004-05-11 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic instrument
US20040150118A1 (en) * 2003-02-03 2004-08-05 Nec Electronics Corporation Warp-suppressed semiconductor device
US20060084254A1 (en) * 2004-01-06 2006-04-20 Attarwala Abbas I Method for making electronic packages

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3541491B2 (ja) * 1994-06-22 2004-07-14 セイコーエプソン株式会社 電子部品
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
JP3752949B2 (ja) 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
US6528869B1 (en) 2001-04-06 2003-03-04 Amkor Technology, Inc. Semiconductor package with molded substrate and recessed input/output terminals
TW498516B (en) * 2001-08-08 2002-08-11 Siliconware Precision Industries Co Ltd Manufacturing method for semiconductor package with heat sink
US20040175582A1 (en) 2002-12-05 2004-09-09 Olin Corporation, A Corporation Of The Commonwealth Of Virginia Laser ablation resistant copper foil
US6936922B1 (en) * 2003-09-26 2005-08-30 Amkor Technology, Inc. Semiconductor package structure reducing warpage and manufacturing method thereof
US7157791B1 (en) 2004-06-11 2007-01-02 Bridge Semiconductor Corporation Semiconductor chip assembly with press-fit ground plane
JPWO2007126090A1 (ja) 2006-04-27 2009-09-17 日本電気株式会社 回路基板、電子デバイス装置及び回路基板の製造方法
US20090102050A1 (en) 2007-10-17 2009-04-23 Phoenix Precision Technology Corporation Solder ball disposing surface structure of package substrate
TW201041105A (en) 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
US8432022B1 (en) * 2009-09-29 2013-04-30 Amkor Technology, Inc. Shielded embedded electronic component substrate fabrication method and structure
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8642897B2 (en) * 2010-10-12 2014-02-04 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US8837872B2 (en) * 2010-12-30 2014-09-16 Qualcomm Incorporated Waveguide structures for signal and/or power transmission in a semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0702404A2 (en) * 1994-09-14 1996-03-20 Nec Corporation Semiconductor device
US6734535B1 (en) * 1999-05-14 2004-05-11 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic instrument
JP2001274203A (ja) * 2000-03-24 2001-10-05 Hitachi Cable Ltd ２メタル基板とｂｇａ構造
US6448506B1 (en) * 2000-12-28 2002-09-10 Amkor Technology, Inc. Semiconductor package and circuit board for making the package
JP2003037244A (ja) * 2001-07-24 2003-02-07 Hitachi Cable Ltd 半導体装置用テープキャリア及びそれを用いた半導体装置
CN1359150A (zh) * 2002-01-15 2002-07-17 威盛电子股份有限公司 球脚阵列封装基板及其制造方法
US20040150118A1 (en) * 2003-02-03 2004-08-05 Nec Electronics Corporation Warp-suppressed semiconductor device
US20060084254A1 (en) * 2004-01-06 2006-04-20 Attarwala Abbas I Method for making electronic packages

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