CN103426855B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

Info

Publication number
CN103426855B
CN103426855B CN201210192571.0A CN201210192571A CN103426855B CN 103426855 B CN103426855 B CN 103426855B CN 201210192571 A CN201210192571 A CN 201210192571A CN 103426855 B CN103426855 B CN 103426855B
Authority
CN
China
Prior art keywords
layer
line layer
semiconductor package
sub
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210192571.0A
Other languages
English (en)
Other versions
CN103426855A (zh
Inventor
萧惟中
林俊贤
白裕呈
洪良易
孙铭成
唐绍祖
蔡瀛洲
蓝章益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN103426855A publication Critical patent/CN103426855A/zh
Application granted granted Critical
Publication of CN103426855B publication Critical patent/CN103426855B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)

Abstract

一种半导体封装件及其制法，该半导体封装件的制法包括先于第一承载板上制作封装基板，再结合第二承载板于该封装基板上；接着，移除该第一承载板；之后于该封装基板上进行置晶与封装工艺；最后移除该第二承载板。借由该第一与第二承载板提供该封装基板于工艺中足够的刚性，使该封装基板可朝薄型化作设计，且不会发生碎裂或翘曲的情况。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，特别是关于一种提升可靠度的半导体封装件及其制法。
背景技术
随着行动装置于电子产业中的蓬勃发展，电子产品也逐渐迈向薄型化的趋势，而半导体封装件的高度包括用以包覆芯片的封装胶体的厚度、基板厚度及锡球高度。为了满足半导体封装件微型化(miniaturization)的封装需求，降低封装基板厚度已成为半导体封装件微型化其中一个重要的发展方向。
早期半导体封装件的制法中，是以具有核心层的封装基板提升整体结构的刚性，以利于后续置晶与封装工艺。然而，因封装基板具有核心层，所以该封装基板的厚度增加，导致整体封装结构的高度增加，而难以符合微小化的需求。
因此，遂发展出无核心层(coreless)的封装基板，以达到微小化的需求。请参阅第7795071号美国专利或如图1A至图1C所示现有半导体封装件1的制法的剖面示意图。
如图1A所示，于一承载件(图略)上形成一无核心层(coreless)的封装基板1a，再移除该承载件。该封装基板1a包含一绝缘保护层14与一埋设于该绝缘保护层14中的线路层13，该线路层13的下表面与该绝缘保护层14的表面齐平，且该绝缘保护层14具有开孔140，以令该线路层13的部分上表面外露于该些开孔140。
如图1B所示，置放至少一芯片17于该绝缘保护层14下侧，且该芯片17借由导电凸块170电性连接该线路层13。
如图1C所示，形成一表面处理层12于该开孔140中的线路层13上。
然而，现有半导体封装件1的制法中，依该封装基板1a的薄型化设计，虽可省去核心层的材料成本及形成开孔140的制作时间，但该封装基板1a的厚度越薄，其刚性越小，所以随着薄化的需求，该封装基板1a已不具有足够的刚性作承载之用，致使于后续置晶或封装工艺时，该封装基板1a容易碎裂，导致产品的良率不佳，而影响产品的可靠度。
此外，当移除承载件后，薄型化的封装基板1a容易发生翘曲，致使该线路层13与绝缘保护层14间发生脱层的问题，因而需将封装基板1a作废，以致材料成本的浪费。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的不足，本发明的主要目的在于提供一种半导体封装件及其制法，以使该封装基板可朝薄型化作设计，且不会发生碎裂或翘曲的情况。
本发明的半导体封装件包括：封装基板，其包含绝缘保护层与埋设于该绝缘保护层中的线路层，该线路层具有相对的第一表面与第二表面，且该线路层包含第一子线路层、第二子线路层与第三子线路层，其中，该线路层的第一表面外露于该绝缘保护层，又该绝缘保护层具有至少一开孔，以令该线路层的部份第二表面外露于该开孔；芯片，其设于该封装基板上，且电性连接该线路层的第一表面；以及封装胶体，其形成于该封装基板上，且包覆该芯片，并外露该开孔。
本发明还提供一种半导体封装件的制法，其包括：形成线路层于第一承载板上，该线路层具有相对的第一表面与第二表面，且该线路层的第一表面与该第一承载板结合；形成绝缘保护层于该第一承载板与该线路层上，且于该绝缘保护层上形成有至少一开孔，以令该线路层的部份第二表面外露于该开孔；结合第二承载板于该绝缘保护层上；移除该第一承载板，以外露该线路层的第一表面与该绝缘保护层；置放芯片于该绝缘保护层上，且电性连接该芯片与线路层的第一表面；形成封装胶体于该绝缘保护层与该线路层的第一表面上，以包覆该芯片；以及移除该第二承载板。
前述的制法中，形成该第一及第二承载板的材质可为玻璃纤维板(FR4)、玻璃或金属。
前述的制法中，该线路层还包括第一子线路层、第二子线路层与第三子线路层。
前述的半导体封装件及其制法中，该线路层的第一表面可齐平于该绝缘保护层的表面。
前述的半导体封装件及其制法中，该绝缘保护层可为防焊层或封装胶材。
另外，前述的半导体封装件及其制法中，依该线路层的材质结构，选择性形成表面处理层或金属层。
例如，该第一子线路层为金或银，该第二子线路层为镍，且该第三子线路层为铜，所以该线路层的第二表面上形成有表面处理层，且该表面处理层的材质为金或银。
或者，该第一子线路层为金，该第二子线路层为镍，且该第三子线路层为钯，所以该线路层的第二表面上形成有金属层，该金属层的材质为铜，且选择性形成表面处理层于该金属层上，且该表面处理层的材质为锡、银、镍、钯、金、焊锡、无铅焊锡或其组合的其中一者。
由上可知，本发明的半导体封装件及其制法，借由该第一承载板作为制作该封装基板的支撑件，可避免薄型化的封装基板于工艺中发生翘曲，所以相比于现有技术，本发明的线路层与绝缘保护层间不会发生脱层的问题，因而无需将封装基板作废。
此外，待结合该第二承载板于该薄型化的封装基板上之后，再移除该第一承载板，以借由该第二承载板提供所需的刚性，使该薄型化的封装基板可有效进行置晶与封装工艺而不会碎裂，以大幅提升封装件的生产良率。
附图说明
图1A至图1C为现有半导体封装件的制法的剖面示意图；
图2A至图2J为本发明的半导体封装件的制法的第一实施例的剖面示意图；其中，图2I’为图2I的另一实施例，图2J’为图2J的不同实施例；以及
图3A至图3D为本发明的半导体封装件的制法的第二实施例的剖面示意图；其中，图3C’为图3C的另一实施例。
主要组件符号说明
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟知本领域技术的人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟知本领域技术的人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、“第三”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
请参阅图2A至图2J，其为本发明的半导体封装件的制法的第一实施例的剖面示意图。
如图2A所示，提供一第一承载板20，再形成导电层201于该第一承载板20上。
于本实施例中，形成该第一承载板20的材质为玻璃纤维板(FR4)、玻璃或金属，且该导电层201作为后续电镀工艺时的电流路径。
接着，形成阻层21于该导电层201的表面上，且图案化该阻层21而形成多个开口210，以外露部份的导电层201。
如图2B所示，形成一具有相对的第一表面221与第二表面222的线路层22于该导电层201上，其中，该线路层22包含依序形成的第一子线路层22a、第二子线路层22b以及第三子线路层22c。
于本实施例中，形成该第一子线路层22a的材质为金或银，形成该第二子线路层22b的材质为镍，且形成该第三子线路层22c的材质为铜。
如图2C所示，移除该阻层21及其上的导电层201。
如图2D所示，形成一绝缘保护层24于该第一承载板20与该线路层22上，且于该绝缘保护层24上形成有多个开孔240，以令线路层22部份的第二表面222外露于该些开孔240，以完成薄型化的封装基板2a。于本实施例中，该绝缘保护层24为防焊层。于另一实施例中，该绝缘保护层24为封装胶材。
如图2E所示，形成一表面处理层23于该开孔240中的线路层22的第二表面222上，其中，形成该表面处理层23的材质为金或银。
如图2F所示，利用粘着层25结合一第二承载板26于该绝缘保护层24上，以作为薄型化的封装基板的支撑，供于后续封装工艺中具有较佳的刚性，进而提高封装件的生产良率。
于本实施例中，形成该第二承载板26的材质为玻璃或金属。
如图2G所示，移除该第一承载板20及剩余的导电层201，以外露该线路层22的第一表面221与该绝缘保护层24。
于本实施例中，该线路层22的第一表面221齐平于该绝缘保护层24的表面。
如图2H所示，置放至少一芯片27于该绝缘保护层24上，且该芯片27借由焊线270电性连接该线路层22。
接着，形成封装胶体28于该绝缘保护层24上，以包覆该芯片27、焊线270与该线路层22。
于本实施例中，形成该封装胶体28的材质可为亚聚酰胺(Polyimide，PI)，其利用涂布方式所形成。或者，可利用压合(lamination)或模压(molding)方式形成该封装胶体28。又有关该封装胶体28的材料并不限于上述。
如图2I所示，移除该第二承载板26及粘着层25，以外露该表面处理层23，以完成本发明的半导体封装件2。于其它实施例中，如图2I’所示，当制作该线路层22时，可选择性地一并制作置晶垫220，以供置放该芯片27。
如图2J所示，植球于该表面处理层23上并回焊，以形成多个如焊球的导电组件29于该线路层22的第二表面222上，使该半导体封装件2借由该些导电组件29接置于如电路板的电子装置上。
本发明的制法中，于形成该绝缘保护层24之后，先设置该第二承载板26，再移除该第一承载板20，以于后续置晶与封装工艺时，可借由该第二承载板26作支撑用，所以本发明的绝缘保护层24与线路层22可朝薄化作设计，而无需担忧因厚度过薄而无法进行置晶与封装工艺的问题。
因此，本发明的制法可提供厚度极薄的封装基板2a，且于置晶与封装工艺时，该封装基板2a借由该第二承载板26具有足够的刚性，以避免破裂，因而可提升产品的良率，进而提升产品的可靠度。
此外，借由该第一承载板20与该第二承载板26的设置，当移除该第一承载板20后，该第二承载板26仍可提供支撑的功能，使该薄型化的封装基板2a于制作后仍具有足够的刚性，因而可确保不会发生翘曲，以有效避免该绝缘保护层24与该线路层22之间发生脱层的问题，所以可降低该封装基板2a作废的可能性，以降低材料成本。
另外，如图2J’所示，该芯片27’也可以覆晶方式借由导电凸块270’电性连接该线路层22。
请参阅图3A至图3D，其为本发明的半导体封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于线路层的结构与表面处理层的结构，其它相关工艺均大致相同，所以不再赘述。
如图3A所示，其为接续图2A的工艺，形成一具有相对的第一表面321与第二表面322的线路层32于该阻层21开口210中的导电层201上，其中，该线路层32包含依序形成的第一子线路层32a、第二子线路层32b以及第三子线路层32c。
于本实施例中，形成该第一子线路层32a的材质为金，形成该第二子线路层32b的材质为镍，且形成该第三子线路层32c的材质为钯。
如图3B所示，移除该阻层21，再于该第一承载板20及该线路层32上以无电电镀方式形成金属层301。于本实施例中，该金属层301的材质为铜。
如图3C所示，形成一绝缘保护层24于该第一承载板20与该线路层32上，且于该绝缘保护层24上形成有多个开孔240，以令部份该金属层301外露于该些开孔240，以完成薄型化的封装基板3a。
于另一实施例中，如图3C’所示，可选择性形成一表面处理层33于该开孔240中的金属层301上，且形成该表面处理层33的材质为锡、银、镍、钯、金、焊锡、无铅焊锡或其组合的其中一者。
如图3D所示，如图2F至图2J的工艺，进行封装与置晶作业，以形成半导体封装件3。
本发明提供一种半导体封装件2，3，其包括：一封装基板2a，3a、设于该封装基板2a，3a上的一芯片27、以及形成于该封装基板2a，3a上且包覆该芯片27的封装胶体28。
所述的封装基板2a，3a包含一绝缘保护层24与一埋设于该绝缘保护层24中且具有相对的第一表面221，321与第二表面222，322的线路层22，32，该线路层22，32的第一表面221，321外露且齐平于该绝缘保护层24，且该线路层22，32的第二表面222，322上形成有表面处理层23，33或金属层301，又该绝缘保护层24具有多个开孔240，以令部份的该表面处理层23，33或金属层301外露于该些开孔240。
于本实施例中，该线路层22，32包含有第一子线路层22a，32a、第二子线路层22b，32b以及第三子线路层22c，32c，其中，该第一子线路层22a的材质为金或银，该第二子线路层22b的材质为镍，且该第三子线路层22c的材质为铜。于另一实施例中，该该第一子线路层32a的材质为金，该第二子线路层32b的材质为镍，且该第三子线路层32c的材质为钯。又该绝缘保护层24为防焊层或封装胶体。
所述的芯片27电性连接该线路层22，32。于本实施例中，该芯片27借由多个焊线270电性连接该线路层22，32，所以该线路层22也可具有置晶垫220，以供置放该芯片27。于另一实施例中，该芯片27’借由多个导电凸块270’以覆晶接合方式电性连接该线路层22。
另外，该封装胶体28还外露该开孔240中的表面处理层23，33或金属层301，以结合导电组件29，以供接置如电路板的电子装置。于本实施例中，该外露的金属层301为铜。综上所述，本发明的半导体封装件及其制法，主要借由第一与第二承载板作为支撑，以于制作封装基板与封装件时，该封装基板均接置有承载板，使该封装基板于每一工艺阶段均保持良好的刚性，以避免发生翘曲或破裂的情况，所以有效提高产品的可靠度及节省材料成本。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟知本领域技术的人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种半导体封装件，其包括：
封装基板，其包含绝缘保护层与埋设于该绝缘保护层中的线路层，该线路层具有相对的第一表面与第二表面，且该线路层包含从该线路层的第一表面侧至第二表面侧依序形成的第一子线路层、第二子线路层与第三子线路层，其中，该线路层的第一表面外露于该绝缘保护层，又该绝缘保护层具有至少一开孔，以令该线路层的部份第二表面外露于该开孔，其中该线路层的第二表面上形成有表面处理层，该第一子线路层为金或银，该第二子线路层为镍，且该第三子线路层为铜；
芯片，其设于该封装基板上，且电性连接该线路层的第一表面；以及
封装胶体，其形成于该封装基板上，且包覆该芯片，并外露该开孔。
2.根据权利要求1所述的半导体封装件，其特征在于，该线路层的第一表面齐平于该绝缘保护层的表面。
3.根据权利要求1所述的半导体封装件，其特征在于，该表面处理层的材质为金或银。
4.根据权利要求1所述的半导体封装件，其特征在于，该绝缘保护层为防焊层或封装胶材。
5.一种半导体封装件，其包括：
封装基板，其包含绝缘保护层与埋设于该绝缘保护层中的线路层，该线路层具有相对的第一表面与第二表面，且该线路层包含从该线路层的第一表面侧至第二表面侧依序形成的第一子线路层、第二子线路层与第三子线路层，其中，该线路层的第一表面外露于该绝缘保护层，又该绝缘保护层具有至少一开孔，以令该线路层的部份第二表面外露于该开孔，其中该线路层的第二表面上形成有表面处理层，该第一子线路层为金，该第二子线路层为镍，且该第三子线路层为钯；
芯片，其设于该封装基板上，且电性连接该线路层的第一表面；以及
封装胶体，其形成于该封装基板上，且包覆该芯片，并外露该开孔。
6.根据权利要求5所述的半导体封装件，其特征在于，该线路层的第二表面上与该表面处理层之间形成有金属层。
7.根据权利要求6所述的半导体封装件，其特征在于，该金属层的材质为铜。
8.根据权利要求6所述的半导体封装件，其特征在于，该表面处理层的材质为锡、银、镍、钯、金、含铅焊锡、无铅焊锡或其组合的其中一者。
9.根据权利要求5所述的半导体封装件，其特征在于，该绝缘保护层为防焊层或封装胶材。
10.一种半导体封装件的制法，其包括：
形成线路层于第一承载板上，该线路层具有相对的第一表面与第二表面，且该线路层的第一表面与该第一承载板结合；
形成绝缘保护层于该第一承载板与该线路层上，且于该绝缘保护层上形成有至少一开孔，以令该线路层的部份第二表面外露于该开孔；
结合第二承载板于该绝缘保护层上；
移除该第一承载板，以外露该线路层的第一表面与该绝缘保护层；
置放芯片于该绝缘保护层上，且电性连接该芯片与线路层的第一表面；
形成封装胶体于该绝缘保护层与该线路层的第一表面上，以包覆该芯片；以及
移除该第二承载板。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，形成该第一承载板及第二承载板的材质为玻璃纤维板、玻璃或金属。
12.根据权利要求10所述的半导体封装件的制法，其特征在于，该线路层的第一表面齐平于该绝缘保护层的表面。
13.根据权利要求10所述的半导体封装件的制法，其特征在于，该线路层还包括从该线路层的第一表面侧至第二表面侧依序形成的第一子线路层、第二子线路层与第三子线路层。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该第一子线路层为金或银，该第二子线路层为镍，且该第三子线路层为铜。
15.根据权利要求14所述的半导体封装件的制法，其特征在于，该制法还包括形成表面处理层于该开孔中的线路层的第二表面上。
16.根据权利要求15所述的半导体封装件的制法，其特征在于，该表面处理层的材质为金或银。
17.根据权利要求13所述的半导体封装件的制法，其特征在于，该第一子线路层为金，该第二子线路层为镍，且该第三子线路层为钯。
18.根据权利要求17所述的半导体封装件的制法，其特征在于，该制法还包括形成金属层于该线路层上。
19.根据权利要求18所述的半导体封装件的制法，其特征在于，该金属层的材质为铜。
20.根据权利要求18所述的半导体封装件的制法，其特征在于，该制法还包括形成表面处理层于该金属层上。
21.根据权利要求20所述的半导体封装件的制法，其特征在于，该表面处理层的材质为锡、银、镍、钯、金、含铅焊锡、无铅焊锡或其组合的其中一者。
22.根据权利要求10所述的半导体封装件的制法，其特征在于，该绝缘保护层为防焊层或封装胶材。
CN201210192571.0A 2012-05-18 2012-06-12 半导体封装件及其制法 Active CN103426855B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101117728 2012-05-18
TW101117728A TWI471989B (zh) 2012-05-18 2012-05-18 半導體封裝件及其製法

Publications (2)

Publication Number Publication Date
CN103426855A CN103426855A (zh) 2013-12-04
CN103426855B true CN103426855B (zh) 2016-09-07

Family

ID=49580682

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210192571.0A Active CN103426855B (zh) 2012-05-18 2012-06-12 半导体封装件及其制法

Country Status (3)

Country Link
US (2) US8796867B2 (zh)
CN (1) CN103426855B (zh)
TW (1) TWI471989B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170084519A1 (en) * 2015-09-22 2017-03-23 Freescale Semiconductor, Inc. Semiconductor package and method of manufacturing same
TWI582903B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
TWI575619B (zh) * 2015-12-09 2017-03-21 南茂科技股份有限公司 半導體封裝結構及其製作方法
US10879144B2 (en) 2018-08-14 2020-12-29 Texas Instruments Incorporated Semiconductor package with multilayer mold

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101409238A (zh) * 2007-10-11 2009-04-15 全懋精密科技股份有限公司 无核层封装基板的制作方法
CN102104007A (zh) * 2009-12-21 2011-06-22 北大方正集团有限公司 一种特种电路板的制造方法和设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291971B1 (ko) * 1993-10-26 2001-10-24 야마자끼 순페이 기판처리장치및방법과박막반도체디바이스제조방법
JP3915992B2 (ja) * 2004-06-08 2007-05-16 ローム株式会社 面実装型電子部品の製造方法
DE102005034011B4 (de) * 2005-07-18 2009-05-20 Infineon Technologies Ag Halbleiterbauteil für Hochfrequenzen über 10 GHz und Verfahren zur Herstellung desselben
DE102007034402B4 (de) * 2006-12-14 2014-06-18 Advanpack Solutions Pte. Ltd. Halbleiterpackung und Herstellungsverfahren dafür
US8552570B2 (en) * 2008-01-09 2013-10-08 Renesas Electronics Corporation Wiring board, semiconductor device, and method for manufacturing wiring board and semiconductor device
TW201021658A (en) * 2008-11-28 2010-06-01 Phoenix Prec Technology Corp Circuit board with embedded trace structure and method for preparing the same
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same
JP2011003764A (ja) * 2009-06-19 2011-01-06 Renesas Electronics Corp 半導体装置及びその製造方法
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8786062B2 (en) * 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
TWI453844B (zh) * 2010-03-12 2014-09-21 矽品精密工業股份有限公司 四方平面無導腳半導體封裝件及其製法
US8524577B2 (en) * 2011-10-06 2013-09-03 Stats Chippac, Ltd. Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more eWLB packages per wafer with encapsulant deposited under temperature and pressure
US8836136B2 (en) * 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101409238A (zh) * 2007-10-11 2009-04-15 全懋精密科技股份有限公司 无核层封装基板的制作方法
CN102104007A (zh) * 2009-12-21 2011-06-22 北大方正集团有限公司 一种特种电路板的制造方法和设备

Also Published As

Publication number Publication date
US20130307152A1 (en) 2013-11-21
US8796867B2 (en) 2014-08-05
US9112063B2 (en) 2015-08-18
US20140308780A1 (en) 2014-10-16
CN103426855A (zh) 2013-12-04
TW201349407A (zh) 2013-12-01
TWI471989B (zh) 2015-02-01

Similar Documents

Publication Publication Date Title
CN207781575U (zh) 经封装的电子装置
CN101315917B (zh) 配线基板及其制造方法
US20110014747A1 (en) Stackable packages for three-dimensional packaging of semiconductor dice
CN101887874A (zh) 单层金属层基板结构及其制造方法、和应用之封装件结构
CN104009006B (zh) 半导体封装件的制法
CN102456648B (zh) 封装基板的制法
TWI446508B (zh) 無核心式封裝基板及其製法
US7459345B2 (en) Packaging method for an electronic element
CN103426855B (zh) 半导体封装件及其制法
CN103021969B (zh) 基板、半导体封装件及其制法
US20240178006A1 (en) Leadless semiconductor package with wettable flanks and method for manufacturing the same
CN105990268A (zh) 电子封装结构及其制法
TW201320276A (zh) 封裝基板及其製法
CN103579173A (zh) 半导体封装件及其制法
US20020003308A1 (en) Semiconductor chip package and method for fabricating the same
US20110110058A1 (en) Board on chip package substrate and manufacturing method thereof
CN103137581B (zh) 具有导电凸块的半导体装置、封装结构及制法
CN103107145A (zh) 半导体封装件、预制导线架及其制法
CN102751203A (zh) 半导体封装结构及其制作方法
CN100349288C (zh) 无外引脚封装结构
CN100585844C (zh) 具嵌埋半导体元件的电路板叠接结构
CN101764118B (zh) 封装用基板及半导体封装构造
CN104064530A (zh) 半导体封装件及其制法
CN103247578A (zh) 半导体承载件暨封装件及其制法
KR101097292B1 (ko) 패키지 기판 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant