CN1864254A - 电子器件及其制造方法 - Google Patents

电子器件及其制造方法 Download PDF

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Publication number
CN1864254A
CN1864254A CNA2004800292729A CN200480029272A CN1864254A CN 1864254 A CN1864254 A CN 1864254A CN A2004800292729 A CNA2004800292729 A CN A2004800292729A CN 200480029272 A CN200480029272 A CN 200480029272A CN 1864254 A CN1864254 A CN 1864254A
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China
Prior art keywords
insulating resin
resin layer
layer
chip part
wiring
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Granted
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CNA2004800292729A
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English (en)
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CN100543953C (zh
Inventor
渡边真司
山口幸雄
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Lenovo Innovations Co ltd Hong Kong
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NEC Corp
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Publication of CN1864254A publication Critical patent/CN1864254A/zh
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Publication of CN100543953C publication Critical patent/CN100543953C/zh
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract

本发明的半导体芯片具有配线基板和芯片部分。配线基板具有：绝缘树脂层，其具有第一主表面和第二主表面；以及第一配线层，其布置在第二主表面侧的绝缘树脂层上。芯片部分在底面上具有突出电极。绝缘树脂层如此保持芯片部分，以致于芯片部分的底面和侧面接触到绝缘树脂层，并且在第一主表面侧的绝缘树脂层上暴露芯片部分的顶面。芯片部分的突出电极和第一配线层连接。

Description

电子器件及其制造方法
技术领域
本发明涉及电子器件及其制造方法，并且具体地，涉及其中通过倒装芯片法在配线基板上安装半导体芯片的结构及其安装方法。
背景技术
传统上，在倒装芯片法的半导体芯片和配线基板的连接结构中，连接部分的可靠性成为重要问题之一。
作为增加可靠性的手段，通常在半导体芯片和配线基板之间注入密封树脂，以减轻连接部分上的应力。在大多数情况下使用底部填充(underfill)方法作为树脂注入方法，在所述方法中，通过倒装芯片法在配线基板上安装半导体芯片，然后灌注液态树脂并进行硬化(例如日本专利公开2000-156386：第一传统例子)。
参考图1A到1C，给出倒装芯片安装法的解释，在所述方法中，根据第一传统例子，稍后注入底部填充树脂。如图1A所示，配线基板包括绝缘层12上形成的配线图案2和覆盖配线图案2的阻焊剂3。通常，绝缘层12和配线图案2是多层的。
在安装半导体芯片的步骤中，如图1B所示，在半导体芯片4的电路表面上布置的焊盘(电极)上形成凸起5，并且对准并连接配线基板上的配线图案2的暴露部分和用于半导体芯片4的凸起5。
在图1C显示的随后的步骤中，液态树脂被注入到半导体芯片4和配线基板之间的间隔中，并且被硬化以形成密封半导体芯片4的底部填充17，然后就完成了倒装芯片安装结构的半导体封装。
然而，在稍后注入底部填充树脂的第一传统例子中，作为连接手段，使用了各种技术，诸如金属扩散结、金属熔化结、含金属树脂糊的结之类。在任何技术中，在安装期间向半导体芯片和配线基板施加了热量。因此，特别地，在有机基板用作配线基板的情况下，半导体芯片和配线基板的热膨胀系数之间的差造成应力，并且在已安装半导体芯片之后温度降低时，应力集中在连接部分上。因此，存在下述问题：连接部分易于破裂，并且可靠性改进困难。
作为另一种制造方法，提出了一种技术，其中，在配线基板上预先施加树脂，并且在安装半导体芯片期间，半导体芯片和配线基板之间的树脂和结同时硬化，同时通过向芯片施加压力，维持半导体芯片上形成的凸起与配线基板上形成的焊盘接触(例如，日本专利公开4-82241：第二传统例子)。
参考图2A和2B解释根据第二传统例子的技术中的制造方法。首先，如图2A所示，向在配线基板上安装半导体芯片的位置施加液态树脂17。通常，气压型滴涂装置(air-type dispensing device)用于施加树脂。
然后，具有吸附孔19的芯片安装工具18吸附并保持在其上形成凸起5的半导体芯片4，并且半导体芯片4与配线基板上的配线对准。接着，如图2B所示，向下移动芯片安装工具18，以使凸起5接触到配线图案2，同时吸附并保持半导体芯片4。在维持这种状态的同时，向半导体芯片4施加热量和压力，以连接凸起和配线并硬化半导体芯片和配线基板之间的树脂，从而形成底部填充17。在第二传统例子中，尽管安装期间基板的热膨胀没有变化，但是由于基板返回到室温时收缩而生成的应力在底部填充17之上分散了。因此，可以防止半导体芯片和配线基板的热膨胀系数之间的差造成的连接不良，亦即，可以防止在安装之后注入并硬化树脂的上述技术中的问题。进一步，这个例子具有这样的特征，其中，只有通过凸起5和配线基板上的配线的接触，低温连接才是可用的。然而，近年来，对供便携式终端装置之用的需要已变得严重，并且制造具有薄轮廓的分立半导体芯片已变得必需。重要的问题浮现出来：当在薄芯片的情况下安装芯片时，树脂爬上了半导体芯片安装装置的芯片安装工具，并且树脂粘附到了工具。
随着近来电子器件在性能和功能性方面变得更加复杂，对更高频率和更高密度的需要不断增加。特别地，在包括生成大量噪声的模拟电路的电子装置中，例如移动电话和无线LAN，以及在用于具有较高时钟速度的个人计算机的母板中，向配线基板中的导线传输的噪声可能取决于噪声的水平而造成故障。因此，如何减少或阻挡噪声是重要的问题。
为了减少噪声造成的影响，使用了这样的技术，其中，在核心层的配线层中布置电源和接地图案(ground pattern)，并且在最外配线层中尽可能多地布置与接地相连的填充图案(filled-in pattern)。参考图3A和3B来解释根据这个传统技术的用于安装半导体芯片的例子。图3A是最上配线层的平面图，而图3B则是在半导体芯片的安装部分周围的区域的截面图。用于半导体芯片4的凸起连接到最上配线层上形成的焊盘20，并且通过配线图案2与通孔焊盘21连接。此外，在最上配线层中，在填充图案中形成用于减少噪声造成的上述影响的接地图案2a。在配线基板的内部层中，传输来自连接到焊盘20的半导体芯片4的信号的写入图案2被形成，并且通过配线基板中的这些配线图案连接到其他电子零件的终端。在这个例子中，连接到其他电子零件的写入图案2穿过最上层中布置的接地图案2a的较低层，从而减少了噪声造成的上述影响。
通过通孔22执行用于具有多个配线层的配线基板中的配线图案的层间连接。每个配线图案通过通孔22穿过内部配线层，并且再次通过通孔22被拉到表面层，以与其他零件的相应终端连接。
同样，图4A和4B显示了这样的例子，在所述例子中，根据传统安装方法，层压半导体芯片，并且制造BGA(球栅阵列)。图4A是最上层的配线层的平面图，而图4B则是传统BGA的截面图。类似于图3A和3B中显示的例子，用于半导体芯片4的凸起通过焊盘20并且通过最上配线层中形成的配线图案2被拉出到通孔焊盘21，并且落到较低配线层。在最上层的绝缘层12的外围部分上形成用于导线焊接的焊盘23。在半导体芯片4上，以面朝上的状态安装另一个半导体芯片16。另一个半导体芯片16的电极(未显示)和焊盘23用焊线24连接。
在根据图1A到1C中显示的第一传统例子的制造方法中，特别地，当有机材料用作用于配线基板的绝缘层时，半导体芯片的热膨胀系数近似为2到3ppm/℃，而有机配线基板的热膨胀系数则近似为10到50ppm/℃，存在大的差异。在安装期间，在加热之后，配线基板收缩比芯片收缩的5倍还多，并且这样一来在结部分中就产生了大量应力集中。这种应力集中造成各种结破裂的问题，亦即芯片上的电极上形成的凸起和电极之间的破裂、电极的破裂、凸起和配线基板上的焊盘之间的连接界面破裂，并且应力集中还造成可靠性降低的问题。进一步，由于这些故障由热膨胀系数之间的差造成，所以故障发生的比率在大芯片中增加；特别地，非常难以将这个例子应用于具有外围结构的大芯片，其中，仅在芯片的外围布置凸起。
下一步，将解释根据图2A和2B中显示的第二传统例子的制造方法中的问题。在这种方法中，在安装期间基板的热膨胀没有变化。然而，在安装半导体芯片期间，因为树脂被硬化的同时芯片正由芯片安装工具保持，所以基板在返回到室温时的收缩造成的应力被树脂分散。因此，半导体芯片和配线基板的热膨胀系数之间的差造成的连接故障，亦即在安装之后注入树脂的上述方法中的问题，能够被防止。然而，近年来，对具有供便携式终端装置之用的薄轮廓的半导体器件的需要已变得严重，并且制造具有薄轮廓的分立半导体芯片已变得必需。随着芯片更薄，问题变得明显：在安装期间，树脂爬上了半导体芯片安装装置的芯片安装工具，并且粘附到工具。这造成下述问题：当基板上预先施加的树脂在向半导体芯片施加压力和热量的步骤期间被挤出并泄漏到芯片的外围时，树脂从芯片的侧面攀爬，并且接触到吸附芯片并向芯片施加压力的安装装置的加热工具，所以树脂变硬，然后下一次之后的安装就变得不可能。
参考图5解释这个问题发生的原因，图5是芯片安装工具吸附薄芯片的状态的示意图。考虑到流注量的变化使树脂爬上半导体芯片4的顶面的情况，芯片安装工具18被设计得充分小于半导体芯片4。然而，在半导体芯片4的厚度充分薄的情况下，如图18所示，并且芯片安装工具小于凸起5的形成部分，发生下述问题：当芯片安装工具18向半导体芯片4施加压力时，芯片破裂。因此，对于薄芯片，芯片安装工具18必须被做大，以便至少覆盖凸起5，并且下述可能性显著增加：爬上芯片顶面的树脂粘附到芯片安装工具并变硬。
进一步，因为芯片薄，所以树脂易于攀爬，从而流注的树脂的量的变化必须减少到固定的限度。众所周知，当芯片的厚度为15mm或以下时，在液态树脂的情况下控制树脂的量是困难的，并且减少流注的树脂的量的变化变得困难。
从防止树脂粘附到芯片安装工具和控制恰当的树脂量的观点，提出了膜状树脂，并且正在研究各种树脂材料，诸如热固性的、热塑性的、以及热固性和热塑性混和的树脂材料之类。然而，用于底部填充的膜状树脂材料负担有膜状所特有的许多问题，例如，当膜状树脂粘附到配线基板时的粘附适合性、气泡的生成、以及硬化之后的连接可靠性。这些膜状树脂具有下述问题：不仅它们仍然处于正在开发状态，而且材料成本也非常昂贵。当使用膜状树脂材料时发生的进一步的其他问题在于，不能使用传统的树脂滴涂装置，并且必须对新的膜粘附装置进行资本投资，而这就意味着减少制造成本存在困难。
下一步，解释关于根据传统安装方法制造的电子器件的结构问题。在用于基板表面层导线的部分被安装的传统芯片安装结构中，如图3A、3B、4A和4B所示，许多信号线必须落在内部层的配线层中，并且表面层导线和内部层导线通过用于层间连接的通孔连接。因此，即使安装具有几百个管脚的普通半导体芯片，也需要巨大数目的通孔。特别地，如图3A和3B中显示的传统例子那样，当在基板的最上层中形成接地图案以便处理更高的频率时，这变得更加显著，并且几乎所有的信号线都必须落在内部层中。
这里，在前缘(leading-edge)中需要200μm等级的通孔焊盘直径。随着通孔的数目增加，通孔所占的面积增加。因此，非常难以走线，因为配线面积受限，并且需要可替代的配线，配线层的数目在某些情况下必须增加，并且配线长度进一步增加。因此，为了能够使用更高的频率，有必要使通孔的数目最小化。
进一步，由于通孔数目的增加造成最上层中通孔布置面积和配线面积占有率增加，所以这造成零件之间的安装间隔方面的许多限制，并且对零件的更高密度安装具有有害影响。例如，在图4A和4B显示的BGA中，由于远离半导体芯片16布置焊盘，所以焊线变得更长，并且以芯片尺寸封装变得困难。
此外，关于成本，在许多情况下通孔由激光或其类似物在绝缘层中一个接一个地形成，因为过程的数目与通孔数目的增加成比例地增加，理所当然地，因而用于基板的生产成本增加。层数目的增加显著造成成本增加。
另一方面，从可靠性观点，通孔是基板中易于破裂的部分。根据诸如生产可变性之类的品质，更加优选地是具有较少数目的通孔。通孔的增加使可靠性变弱。
发明内容
作为其目标，本发明首先必须防止在安装后由半导体芯片和配线基板的热膨胀系数之间的差造成的连接部分的破裂，第二，防止当密封树脂爬上时造成的树脂粘附到芯片安装工具，第三，使安装步骤中树脂材料的供应不必要，第四，将通孔的数目减少到最小，第五，使传输线长度最短以处理更高的频率，第六，改善器件的可靠性，第七，使电子器件能够以低成本制造，以及第八，使电子器件更薄、更小。
为了达到上述目标，根据本发明的电子器件包括：配线基板，其包括具有第一主表面和第二主表面的绝缘树脂层以及在所述第二主表面侧的所述绝缘树脂层上布置的第一配线层；以及芯片部分，其包括底面上的突出电极，并且安装在所述配线基板上。绝缘树脂层以这样的方式保持芯片部分：芯片部分的底面以及至少侧面的一部分接触到绝缘树脂层，并且在第一主表面侧的绝缘树脂层上暴露芯片部分的顶面，而且芯片部分的突出电极和第一配线层接触。
换言之，本发明提供电子器件，其包括安装在配线基板上的芯片部分，该芯片部分具有突出电极，而且配线基板包括具有第一主表面和第二主表面的绝缘树脂层以及在第二主表面侧的所述绝缘树脂层上布置的第一配线层，并且其特征在于，芯片部分从第一主表面侧进入绝缘树脂层，而且芯片部分的突出电极穿透绝缘树脂层并连接到第一配线层。
为了达到上述目标，本发明提供一种制造电子器件的方法，其包括以下步骤：制备具有第一主表面和第二主表面的绝缘树脂层、具有在第二主表面侧的所述绝缘树脂层上布置的第一配线层的配线基板、以及包括突出电极的芯片部分；将芯片部分从第一主表面推挤到绝缘树脂层中；以及使芯片部分的突出电极穿过绝缘树脂层以与第一配线层连接，并且用绝缘树脂层的树脂至少密封在其上形成突出电极的芯片部分的表面。
根据本发明，在通过倒装芯片法在配线基板上安装芯片的方法中，使充当在半导体芯片的终端上形成的突出电极的凸起穿过配线基板的绝缘树脂层，并且把为内部层的配线层形成的连接焊盘和突出电极连接起来，从而达到了防止在安装之后由半导体芯片和配线基板的热膨胀系数之间的差造成的连接部分破裂的效果，亦即防止了稍后注入并硬化树脂的方法中的问题，并且从而达到了防止当树脂爬上时造成的树脂粘附到芯片安装工具的效果，亦即防止了作为安装半导体芯片之前供应的底部填充材料而施加的液态树脂的问题。
进一步，由于用于封装半导体芯片的树脂材料由配线基板的材料制成，所以不必要在安装步骤中供应树脂材料。因此，树脂材料的成本、诸如树脂供应和硬化之类的处理成本、以及与这些相关的资本投资是不必要的，并且能够显著减少安装成本。
此外，在这个芯片安装结构中，能够在配线基板中埋入半导体芯片，并且可以实现薄而且小的半导体封装和电子零件基板，使三维高密度芯片安装结构成为可能，在所述三维高密度芯片安装结构中，在埋入的芯片上安装其他零件。
进一步，通过采用电子零件的电极连接到内部层图案的芯片安装结构，能够显著减少通孔的数目。因此，根据本发明，能够获得以下优点：
(1)能够确保配线区域，并且能够考虑到它们的特性而容易地走线；
(2)传输线长度和悬空导线长度能够被最小化；
(3)通过减少通孔的数目，能够减少制造基板的成本，并且通过减少配线层中层的数目，能够使基板更薄且更便宜；
(4)能够实现尺寸减少(基板具有减少的尺寸和薄的轮廓以及用于安装零件的更高密度)；以及
(5)能够改善可靠性。
附图说明
图1A是为了解释根据第一传统例子的安装方法的配线基板的截面图。
图1B是为了解释根据第一传统例子的安装方法的半导体芯片连接到配线基板的状态的截面图。
图1C是为了解释根据第一传统例子的安装方法的在连接到配线基板的半导体芯片和配线基板之间形成底部填充的状态的截面图。
图2A是为了解释根据第二传统例子的安装方法的在半导体芯片连接到配线基板之前向配线基板施加液态树脂的状态的截面图。
图2B是为了解释根据第二传统例子的安装方法的半导体芯片连接到配线基板的状态的截面图。
图3A是在最上层上具有接地图案的传统配线基板的最上配线层的平面图。
图3B是在图3A中显示的配线基板上安装半导体芯片的状态的截面图。平面图和截面图显示了根据传统方法安装倒装芯片的状态。
图4A是传统BGA中使用的配线基板的平面图。
图4B是使用图4A中显示的配线基板的传统BGA的截面图。
图5是芯片安装工具吸附并保持薄半导体芯片的状态的示意图。
图6A是根据本发明第一实施例的配线基板的截面图。
图6B是根据本发明第一实施例的在配线基板上安装半导体芯片的状态的截面图。
图7A是根据本发明第二实施例的配线基板的截面图。
图7B是根据本发明第二实施例的在配线基板上安装半导体芯片的状态的截面图。
图8A是根据本发明安装的具有凸起的半导体芯片的截面图。
图8B是显示在半导体芯片上形成凸起的方法的一个例子的示图。
图8C是显示在半导体芯片上形成凸起的方法的另一个例子的示图。
图9是本发明的应用1的截面图。
图10是本发明的应用2的截面图。
图11是本发明的应用3的截面图。
图12是本发明的应用4的截面图。
图13是本发明的应用5的截面图。
图14是本发明的应用6的截面图。
图15是本发明的应用7的截面图。
图16是本发明的应用8的截面图。
图17A是本发明的应用9的平面图。
图17B是本发明的应用9的截面图。
图18A是本发明的应用10的平面图。
图18B是本发明的应用10的截面图。
具体实施方式
图6A和6B是显示本发明的第一实施例的截面图。图6A是配线基板的截面图，其具有凸起穿过的作为核心层的热塑性绝缘树脂层1，亦即本发明的特征之一。配线基板通过使用敷铜箔基板来制造，在所述敷铜箔基板中，在绝缘树脂层1的两个表面上形成薄铜箔，并且具有通过消去法或其类似方法形成图案的配线图案2，以及在两个表面的最外层上覆盖的阻焊剂3，亦即，配线基板通过典型的制造方法制造。
敷铜箔配线基板可以通过热压层压方法或金属蒸发后植入的方法形成。抗氧化的材料、亦即Au被选为蒸发金属，其直接接触或金属连接到凸起以导电，从而导致预期的可靠性改善。
进一步，优选地，具有和半导体芯片的热膨胀系数接近的热膨胀系数的材料被选为绝缘树脂层1，以确保半导体芯片和凸起连接部分的可靠性。通过添加诸如硅石之类的填料，或者通过使用当自由控制热膨胀系数时能够制造的液晶聚合物，来调节热膨胀系数。
图8A是在本发明中的基板上安装的半导体芯片4的截面图。在半导体芯片4的电路表面上，形成连接到内部电路的焊盘(图8A中未显示)，并且在焊盘(电极)上形成具有尖锐尖端的凸起5。这些凸起能够通过丝焊法或通过冲压法形成，如图8B、8C所示。特别地，如图8B所示，在毛细管6保持的金丝7的尖端部分处形成金球8，然后向半导体芯片4的电路表面上形成的焊盘4a推挤金球8以便连接，并且拉拔金丝7以形成凸起5。当金丝从毛细管伸出时，在吹管(torch)和金丝7之间施加高电压以产生火花，从而在金被熔化并凝结时通过表面张力将金球8形成为球状。
替代地，如图8C所示，具有圆锥形凹入部分9a和冲模10的冲压机9冲压带状材料11，并且冲压的部分连接到在半导体芯片4的电路表面上形成的焊盘4a以形成凸起5。随便提及，由于在半导体芯片4的安装期间通过加热充分软化了热塑性绝缘树脂层1，所以凸起的尖端不必要尖锐，并且在可能使用的材料以及高温焊料凸起、铜凸起和金凸起方面没有限制。然而，当凸起具有尖锐尖端时，提供了用于工艺操作条件的裕量，例如，能够使凸起容易地穿过绝缘树脂层，并且能够容易地确保连接可靠性。因此，在初始屈服(initial yield)和可靠性方面有优点。
图6B是显示在图6A中显示的配线基板上安装图8A中显示的半导体芯片的状态的截面图。具有凸起5的半导体芯片4安装在热塑性绝缘树脂层1上，其为配线基板的核心材料，以便凸起5穿过绝缘树脂层1以与较低层导线连接并且埋入在绝缘树脂层1中。
接下来，解释这个安装结构的安装方法。为了改善半导体芯片4和配线基板的绝缘树脂层1之间的粘附性，优选地，通过等离子处理或者通过紫外线照射预先活化绝缘树脂层1的表面。
没有向在配线基板上安装半导体芯片4的任何部分施加阻焊剂3，并且所述部分是开口的。配线基板上提供的定位标记(register mark)和由安装装置的芯片安装工具吸附并保持的并且要被对准的半导体芯片4经历图像处理。在这种情况下，可以在上层的配线层上形成定位标记，然而，由于难以在上层和较低层中准确地形成图案位置，所以当终端节距(terminal pitch)精细时，优选地在较低层的配线上形成定位标记。此外，当要被施加的热塑性树脂不透明时，为了使标记从上面可见，在覆盖铜之前，对绝缘树脂层1通过冲孔或类似工艺在对准标记部分中配备通孔，或者，在铜覆盖/图案形成之后，通过激光技术、光/蚀刻技术或类似技术在定位标记部分中给绝缘树脂层1开口。安装装置的芯片安装工具能够施加热量和压力，并且这种工具在向对准的配线基板施加压力的同时向吸附的半导体芯片4施加热量，而且保持在绝缘树脂层1被充分软化的温度。在这种情况下，为了有效地向配线基板传送施加到半导体芯片4的热量，优选地，向保持配线基板的平台施加热量。当加热的半导体芯片4接触到绝缘树脂层1时，绝缘树脂层1被软化，因此半导体芯片上形成的凸起5容易地穿过绝缘树脂层1，并且凸起5和配线图案2连接。在用于连接凸起5和配线图案2的步骤中，可以向半导体芯片或配线基板施加超声波振动。此外，由于与凸起5连接的配线的连接表面已经由绝缘树脂层1覆盖，所以在制造步骤期间防止了连接表面经受氧化和污染。凸起5和较低层配线之间的连接可以既适用于金属扩散粘结，又适用于仅通过与绝缘树脂接触的接触保持法。
凸起的尖端形成尖锐的形状，并且尖端在将绝缘树脂层1推开的同时变形。因此，进一步改善了连接可靠性。当半导体芯片4被埋入到希望的深度并且完成凸起和导线之间的连接时，结束对芯片安装工具的热量施加。维持压力的施加，直到充分硬化绝缘树脂层为止，然后升起芯片安装工具。根据上述材料和安装方法，能够实现图6B中的芯片安装结构。
进一步，这种安装结构和制造方法能够适用于在芯片的电路表面上第二次布线的半导体芯片、诸如晶片级CSP之类的封装电子器件、以及无源电子零件。
图7A和7B是显示第二实施例的截面图。图7A显示了配线基板，其中，在绝缘层12、亦即核心层的前后表面上形成配线图案2，在后表面上覆盖阻焊剂3，并且在前表面上形成绝缘树脂层1，其起到阻焊剂的作用并由热塑性树脂制成。图7B是显示根据第一实施例中解释的方法的在图7A中的配线基板上安装半导体芯片的截面图。根据这个实施例，绝缘树脂层1能够既起到阻焊剂又起到密封树脂的作用。
如上所述，热塑性树脂用作绝缘树脂层，通过再加热使修复成为可能，而当应用传统底部填充时这是很困难的。此外，半导体芯片可以通过诸如环氧树脂之类的预硬化材料而不是热塑性树脂来安装，尽管不能执行修复。作为热塑性树脂，可以使用诸如液晶聚合物、丙烯酸树脂、聚酯、ABS、聚碳酸酯、苯氧基、聚砜、聚醚酰亚胺、聚丙烯酸酯、降冰片烯基之类的树脂。作为热固性树脂，可以应用诸如双酚A型、联环戊二烯型、甲酚酚醛清漆型、联苯型、以及萘型之类的环氧树脂，诸如甲阶酚醛树脂型、酚醛清漆型之类的酚醛树脂。可以使用包括多种这些树脂的树脂混合物。
例如，通过使用SUMITOMO BAKELITE Co.Ltd生产的“IBF-3021”，树脂材料包括作为主要成分的热塑性树脂和作为微量添加剂的热固性树脂，能够获得优选的结果。特别地，使用这种树脂材料制造图7B中的器件，在循环测试中(-40到125℃)，亦即从而是加速测试中，可靠性确保在能够适用于用户装置的水平。
在下文中，解释上述实施例的应用。
(应用1)
图9是显示图6A中的配线基板应用于具有多层配线层的基板的例子的截面图。在这个例子中，在核心层13的两个表面上层压配线图案2和绝缘层，以形成多层配线基板。热塑性绝缘树脂层1仅应用于安装半导体芯片4的层。绝缘树脂层1的厚度近似为30到100μm。
除了绝缘树脂层1之外，设想典型的基板结构，亦即，玻璃环氧基板用作核心层13，合成(built-up)绝缘树脂用作绝缘层12，并且热固性树脂用于每个树脂层。只有绝缘树脂层1由热塑性树脂制成，而其他的绝缘树脂层则由热固性树脂制成。在半导体芯片4的安装期间由热量造成的绝缘层12和核心层13的软化变形非常小，并且能够使用与图6B那样的相同的安装技术。因此，这个例子能够容易地应用于多层配线基板。
(应用2)
图10显示了通过滴涂(dispensing)或丝网印刷方法在图6B的实施例中形成涂面树脂14，并且半导体芯片的顶面由树脂加强以使表面平坦。
这种结构具有的优越性在于，当由落下冲击、振动、温度循环或类似情形造成的外部应力给予这种芯片安装结构时，防止了应力集中在半导体芯片4的端面上。因此，能够改善连接可靠性并且能够增加使用范围。
(应用3)
图11是显示封装的电子零件15覆盖并安装在埋入配线基板中的半导体芯片4上的例子的截面图。乳酪焊剂被印刷供应(print-supply)给配线基板的焊盘电极，所述配线基板通过图6B中的安装技术制造，并且在其中包括半导体芯片，安装并回流焊接电子零件15以形成表面安装配线基板。
然而，在这种情况下，作为由热塑性树脂制成的绝缘树脂层1，必须选择具有高软化开始温度点的材料，以便半导体芯片4的连接部分在回流温度下不破裂。
例如，具有相对高抗热性、亦即大约300℃的液晶转变点的液晶聚合物材料可以作为用于绝缘树脂层1的材料而被应用。
(应用4)
图12是显示另一个半导体芯片16覆盖并安装在埋入配线基板中的半导体芯片4上的例子的截面图。半导体芯片4通过图6B中的安装技术安装。半导体芯片16通过倒装芯片的压焊技术或压接(crimping)技术、亦即传统技术安装。然而，为了防止在半导体芯片16的安装期间由热量造成的半导体芯片4中连接部分的破裂，具有相对高液晶转变点的液晶聚合物材料或其类似物可用作用于绝缘树脂层1的材料。
进一步，在安装半导体芯片16的步骤中，半导体芯片16的较低部分处的突出和凹陷在底部填充的流动性方面有影响，并且导致空隙的产生。因此，优选地，半导体芯片4的顶面由涂面树脂14平整，如图10中的例子中的那样。此外，当能够在相对低的温度下安装芯片的倒装芯片安装技术与超声波结合使用作为半导体芯片16的安装技术时，能够被选择用于绝缘树脂层1的材料的范围能够增加。
(应用5)
图13是显示电子器件的截面图，所述电子器件使用通过在芯片安装结构的上、下层的一个或两个中覆盖一个或多个绝缘树脂层和配线层而形成的多层结构的配线基板，同时应用图6B中的芯片安装结构及其制造方法，并且其特征在于，在配线基板中布置半导体芯片。在这个例子中，热塑性树脂或PREPREG(预浸渍薄板材料)可以用作绝缘树脂层1。绝缘树脂层1的厚度近似为30到100μm。
根据图6B中显示的芯片安装结构，结构能够减少成本，如上所述。根据通过与在典型基板上安装半导体芯片中使用的相同的技术在配线基板上安装零件的比较，不仅能够减少最终产品的成本，而且通过在配线基板上内部安装零件，还能够增加安装零件的密度。因此，能够以低成本容易地制造小且纤细的产品。
(应用6)
图14是显示电子器件的截面图，所述电子器件通过应用图6B中的芯片安装结构及其制造方法制造，并且使用在配线基板的两个表面上形成芯片安装结构的多层结构的配线基板。在这个例子中，在核心层13的前、后表面上形成配线层和绝缘层12，并且图6B中的安装结构被应用到每个表面上，以形成双面安装结构的多层配线基板。
(应用7)
图15是显示电子器件的截面图，所述电子器件通过应用图6B中的安装结构及其制造方法制造，使用通过覆盖安装结构而形成的多层结构的配线基板，并且其特征在于，在多层中安装半导体芯片。在这个例子中，热塑性树脂或PREPREG(预浸渍薄板材料)可以用作上层中的绝缘树脂层1。
(应用8)
图16是显示图6B中的配线基板应用于多层结构的配线基板的例子的截面图。在这个例子中，类似于图9中显示的应用1，在核心层13的两个表面上层压配线图案2和绝缘层以形成多层配线基板，并且以这样的方式安装半导体芯片4：使得其凸起5穿过两个热塑性绝缘树脂层1。在这种情况下，可以在每个绝缘树脂层中形成配线图案，并且与图9中的例子相比，能够改善结构和配线中的灵活性。
(应用9)
图17A和17B是显示例子的截面图，所述例子通过应用图6B中的安装结构及其制造方法制造，并且形成多层结构的配线基板，同时上配线层被认为是接地图案。图17A是显示移去半导体芯片的状态的平面图(在图17A中点线指示用于半导体芯片的安装部分)。在这个例子中，半导体芯片的凸起直接连接到内部层配线图案的焊盘20，连接到半导体芯片4的凸起的配线图案直接连接到另一个半导体芯片的凸起，或者通过通孔22落入到较低配线层中。在这个例子中，在使用最上配线层作为接地图案2a的配线基板中，半导体芯片4的凸起连接到内部层的配线层。因此，在半导体芯片附近不需要形成通孔，并且能够减少通孔的数目，而且能够实现高密度安装。给出这一点的具体解释。当在基板上安装两个或更多半导体芯片时，并且特别地，当在表面上布置填充接地图案以阻挡噪声时，所有终端中的1/3到1/2典型地用作信号线，而其他的则用作电源和接地终端。这里，假定具有100个管脚的外部终端的芯片中的50个终端是信号线，在表面层上安装的传统结构中，为了阻挡噪声，所有的信号线都必须通过通孔一次来连接到内部层，并且必须穿过表面层中接地图案的较低层以阻挡噪声，然后必须通过通孔连接到半导体芯片，其为连接目的地。对用于从表面到内部层进行连接的具有信号线的50个终端，以及对用于从内部层到表面进行连接的50个终端，总共需要100个通孔，亦即信号线数目的两倍。另一方面，在根据本发明的在内部层上直接安装芯片的结构中，由于内部层中的直接连接成为可能，所以不需要表面层和内部层之间的通孔。因此，能够消除表面层和内部层之间的所有100个通孔。
同样，根据这个例子，未被接地图案2a覆盖的区域能够被最小化，并且能够增加屏蔽效果。
(应用10)
图18A和18B是显示例子的截面图，所述例子通过应用图6B中的芯片安装结构及其制造方法制造，并且在其中形成层压芯片结构的BGA。图18A是显示移去半导体芯片的状态的平面图(在图18A中点线指示用于半导体芯片的安装部分)。在这个例子中，半导体芯片4的凸起连接到内部层配线图案中的焊盘20，并且另一个半导体芯片16以面朝上的状态安装在半导体芯片4上。另一个半导体芯片16的电极(未显示)和布置在绝缘树脂层1的外围的焊盘23通过焊线24连接。在配线基板的后表面上，在未被阻焊剂3覆盖的区域中形成焊球25。在这个例子中，由于半导体芯片4的凸起连接到内部层的配线层，所以在半导体芯片附近不需要通孔。因此，能够减少通孔的数目，并且能够靠近半导体芯片4布置用于丝焊的焊盘23。因此，能够使焊线24的长度最短。进一步，根据这个例子，能够实现高密度安装，并且能够减少配线层的数目。

Claims (16)

1.一种电子器件，包含：
配线基板，其包括：绝缘树脂层，具有第一主表面和第二主表面；以及第一配线层，布置在所述第二主表面侧的所述绝缘树脂层上；
芯片部分，其包括底面上的突出电极，并且安装在所述配线基板上；并且
其中所述绝缘树脂层如此保持所述芯片部分，使得所述芯片部分的底面以及侧面的至少一部分接触所述绝缘树脂层，而且在所述第一主表面侧的所述绝缘树脂层上暴露所述芯片部分的顶面，并且其中所述芯片部分的所述突出电极与所述第一配线层连接。
2.根据权利要求1所述的电子器件，其中，在所述绝缘树脂层的所述第一主表面上形成第二配线层。
3.根据权利要求2所述的电子器件，其中，在所述第二配线层中形成接地图案。
4.根据权利要求1所述的电子器件，进一步包含用于保持所述芯片部分的多个绝缘树脂层。
5.根据权利要求4所述的电子器件，其中，用于保持所述芯片部分的所述绝缘树脂层被如此层压，使得第一主表面面向相同的方向。
6.根据权利要求1所述的电子器件，其中，在所述配线基板的两个表面上布置用于保持所述芯片部分的所述绝缘树脂层。
7.一种电子器件，包含：
配线基板，包括：多个绝缘树脂层，其被层压，并且具有第一主表面和第二主表面；以及第一配线层，其布置在所述绝缘树脂层中的从最低层到最内层的所述第二主表面侧的所述绝缘树脂层上；
芯片部分，其包括底面上的突出电极，并且安装在所述配线基板上；并且
其中所述绝缘树脂层如此保持所述芯片部分，使得所述芯片部分的底面和侧面接触最外层中的所述绝缘树脂层，而且在所述第二主表面侧的所述绝缘树脂层上暴露所述芯片部分的顶面，并且其中所述芯片部分的所述突出电极与所述第一配线层连接。
8.根据权利要求1或7所述的电子器件，其中，所述配线基板进一步包含除了所述绝缘树脂层之外的绝缘层，并且进一步包含除了所述第一配线层或第一和第二配线层之外的配线层。
9.根据权利要求1或7所述的电子器件，其中，进入所述配线基板中最外层的绝缘树脂层的所述芯片部分的从所述绝缘树脂层暴露的部分，由涂面树脂覆盖。
10.根据权利要求1或7所述的电子器件，其中，所述芯片部分的所述突出电极配备有具有尖锐尖端的部分。
11.根据权利要求1或7所述的电子器件，其中，所述芯片部分的所述突出电极是通过丝焊技术形成的金电极。
12.根据权利要求1或7所述的电子器件，其中，所述绝缘树脂层由热塑性树脂或在其中向热塑性树脂添加热固性树脂的材料制成。
13.一种制造电子器件的方法，包含以下步骤：
制备配线基板和包括突出电极的芯片部分，所述配线基板具有：绝缘树脂层，其具有第一主表面和第二主表面；以及第一配线层，其布置在所述第二主表面侧的所述绝缘树脂层上；
将所述芯片部分从所述第一主表面推挤到所述绝缘树脂层中；以及
使所述芯片部分的所述突出电极穿过所述绝缘树脂层以与所述第一配线层连接，并且用所述绝缘树脂层的树脂至少密封在其上形成所述芯片部分的所述突出电极的表面。
14.根据权利要求13所述的方法，其中，推挤所述芯片部分的所述步骤包含推挤所述芯片部分同时加热。
15.根据权利要求13所述的方法，其中，推挤所述芯片部分的所述步骤包含推挤所述芯片部分同时向所述芯片部分或向所述配线基板施加超声波振动。
16.根据权利要求13所述的方法，进一步包含以下步骤：在推挤所述芯片部分的所述步骤之前，向要被所述芯片部分推挤到所述绝缘树脂层的所述第一主表面上的至少一部分施加等离子处理或紫外线照射。
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