JP4396641B2 - フェイスダウン型半導体装置及びその製造方法 - Google Patents
フェイスダウン型半導体装置及びその製造方法 Download PDFInfo
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- JP4396641B2 JP4396641B2 JP2006000289A JP2006000289A JP4396641B2 JP 4396641 B2 JP4396641 B2 JP 4396641B2 JP 2006000289 A JP2006000289 A JP 2006000289A JP 2006000289 A JP2006000289 A JP 2006000289A JP 4396641 B2 JP4396641 B2 JP 4396641B2
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- 239000004065 semiconductor Substances 0.000 title claims description 82
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000011347 resin Substances 0.000 claims description 40
- 229920005989 resin Polymers 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 8
- 239000003960 organic solvent Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims 21
- 239000012044 organic layer Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 4
- 229920000742 Cotton Polymers 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 238000007790 scraping Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81052—Detaching bump connectors, e.g. after testing
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- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- H01L2224/8121—Applying energy for connecting using a reflow oven
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- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/92—Specific sequence of method steps
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
2 ;配線基板
21;パッド
22;レベル表示パッド用金属層
3 ;はんだバンプ
4 ;アンダーフィル樹脂
5 ;レベル表示パッド
5a;レベル表示パッドの第1層
5b;レベル表示パッドの第2層
6 ;フェイスダウン型半導体装置
7 ;工具
8 ;綿棒
Claims (4)
- 基板電極が設けられた配線基板と、前記基板電極上にフェイスダウンで搭載された半導体素子と、前記半導体素子と前記配線基板との間を充填するアンダーフィル樹脂と、前記配線基板上に所定の高さとなるように順次積層された第1層と第2層とを備え前記アンダーフィル樹脂に埋め込まれて配置されたレベル表示パッドと、を有し、前記アンダーフィル樹脂と前記第1層と前記第2層とは、各々の断面が露出したときに目視で互いに識別可能であり、前記所定の高さは、前記第1層と前記第2層との合計の高さが前記配線基板と前記半導体素子との間隔よりも小さく、かつ前記第1層の高さが前記配線基板の反り及びうねり並びに前記基板電極の高さよりも大きくなるように定められた高さである、ことを特徴とするフェイスダウン型半導体装置。
- 前記レベル表示パッドは、前記第1層が前記配線基板の前記基板電極と同時に形成され前記基板電極とは異なる金属層の上にめっきによって形成された金属層であり、前記第2層が前記第1層の上に形成され有機溶剤によって除去される材質からなる層であることを特徴とする請求項1に記載のフェイスダウン型半導体装置。
- 前記レベル表示パッドは、前記基板電極が配置された領域を囲む前記配線基板の表面の縁部及び前記配線基板の前記表面における前記基板電極の間の位置に複数個配置されていることを特徴とする請求項1又は2に記載のフェイスダウン型半導体装置。
- 配線基板上に基板電極とレベル表示パッド形成用の金属層とを同時に形成する工程と、前記レベル表示パッド形成用の金属層の上に前記レベル表示パッドの第1層である金属層をめっきによってその前記配線基板からの高さが前記配線基板の反り及びうねり並びに前記基板電極の高さよりも大きくなるように形成する工程と、前記第1層である金属層の上に有機溶剤によって除去される材質からなる前記レベル表示パッドの第2層をその前記配線基板からの高さが前記配線基板とこの配線基板上に素子電極を介して搭載される半導体素子との間隔よりも小さくなるように形成する工程と、前記半導体素子をその下面の前記素子電極と前記配線基板の前記基板電極とが接続されるように前記配線基板上に搭載する工程と、前記半導体素子と前記配線基板との間に前記レベル表示パッドを埋め込むようにアンダーフィル樹脂を充填する工程と、を有することを特徴とするフェイスダウン型半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006000289A JP4396641B2 (ja) | 2006-01-04 | 2006-01-04 | フェイスダウン型半導体装置及びその製造方法 |
US11/646,439 US20070152347A1 (en) | 2006-01-04 | 2006-12-28 | Face down type semiconductor device and manufacturing process of face down type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006000289A JP4396641B2 (ja) | 2006-01-04 | 2006-01-04 | フェイスダウン型半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007184331A JP2007184331A (ja) | 2007-07-19 |
JP4396641B2 true JP4396641B2 (ja) | 2010-01-13 |
Family
ID=38223527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006000289A Expired - Fee Related JP4396641B2 (ja) | 2006-01-04 | 2006-01-04 | フェイスダウン型半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
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US (1) | US20070152347A1 (ja) |
JP (1) | JP4396641B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW557536B (en) * | 2002-05-27 | 2003-10-11 | Via Tech Inc | High density integrated circuit packages and method for the same |
TW561602B (en) * | 2002-09-09 | 2003-11-11 | Via Tech Inc | High density integrated circuit packages and method for the same |
CN100543953C (zh) * | 2003-10-06 | 2009-09-23 | 日本电气株式会社 | 电子器件及其制造方法 |
-
2006
- 2006-01-04 JP JP2006000289A patent/JP4396641B2/ja not_active Expired - Fee Related
- 2006-12-28 US US11/646,439 patent/US20070152347A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2007184331A (ja) | 2007-07-19 |
US20070152347A1 (en) | 2007-07-05 |
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